yosys.git
4 years agoMerge branch 'master' of https://github.com/YosysHQ/yosys
Rodrigo Alejandro Melo [Mon, 3 Feb 2020 13:56:11 +0000 (10:56 -0300)]
Merge branch 'master' of https://github.com/YosysHQ/yosys

Solved a conflict into the CHANGELOG

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
4 years agoReplaced strlen by GetSize into simplify.cc
Rodrigo Alejandro Melo [Mon, 3 Feb 2020 13:30:33 +0000 (10:30 -0300)]
Replaced strlen by GetSize into simplify.cc

As recommended in CodingReadme.

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
4 years agoMerge pull request #1516 from YosysHQ/dave/dotstar
David Shah [Sun, 2 Feb 2020 18:12:28 +0000 (18:12 +0000)]
Merge pull request #1516 from YosysHQ/dave/dotstar

sv: Add support for wildcard port connections (.*)

4 years agoUpdate CHANGELOG and README
David Shah [Fri, 22 Nov 2019 15:32:46 +0000 (15:32 +0000)]
Update CHANGELOG and README

Signed-off-by: David Shah <dave@ds0.me>
4 years agosv: Improve handling of wildcard port connections
David Shah [Fri, 22 Nov 2019 15:07:55 +0000 (15:07 +0000)]
sv: Improve handling of wildcard port connections

Signed-off-by: David Shah <dave@ds0.me>
4 years agosv: More tests for wildcard port connections
David Shah [Fri, 22 Nov 2019 12:57:51 +0000 (12:57 +0000)]
sv: More tests for wildcard port connections

Signed-off-by: David Shah <dave@ds0.me>
4 years agohierarchy: Correct handling of wildcard port connections with default values
David Shah [Fri, 22 Nov 2019 09:21:35 +0000 (09:21 +0000)]
hierarchy: Correct handling of wildcard port connections with default values

Signed-off-by: David Shah <dave@ds0.me>
4 years agosv: Add tests for wildcard port connections
David Shah [Fri, 22 Nov 2019 09:16:37 +0000 (09:16 +0000)]
sv: Add tests for wildcard port connections

Signed-off-by: David Shah <dave@ds0.me>
4 years agohierarchy: Resolve SV wildcard port connections
David Shah [Fri, 22 Nov 2019 09:04:54 +0000 (09:04 +0000)]
hierarchy: Resolve SV wildcard port connections

Signed-off-by: David Shah <dave@ds0.me>
4 years agosv: Add lexing and parsing of .* (wildcard port conns)
David Shah [Fri, 22 Nov 2019 08:24:01 +0000 (08:24 +0000)]
sv: Add lexing and parsing of .* (wildcard port conns)

Signed-off-by: David Shah <dave@ds0.me>
4 years agoRemoved 'synth' into tests/memfile/run-test.sh
Rodrigo Alejandro Melo [Sun, 2 Feb 2020 15:33:34 +0000 (12:33 -0300)]
Removed 'synth' into tests/memfile/run-test.sh

Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
4 years agoAdded content1.dat into tests/memfile
Rodrigo Alejandro Melo [Sun, 2 Feb 2020 15:18:34 +0000 (12:18 -0300)]
Added content1.dat into tests/memfile

Modified run-test.sh to use it.

Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
4 years agoMerge pull request #1647 from YosysHQ/dave/sprintf
David Shah [Sun, 2 Feb 2020 14:53:46 +0000 (14:53 +0000)]
Merge pull request #1647 from YosysHQ/dave/sprintf

ast: Add support for $sformatf system function

4 years agoMerge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly
David Shah [Sun, 2 Feb 2020 14:53:32 +0000 (14:53 +0000)]
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly

synth_xilinx: add -dsp-multonly

4 years agoxilinx: use RAM32M/RAM64M for memories with two read ports
Marcin Kościelnicki [Sun, 2 Feb 2020 10:26:00 +0000 (11:26 +0100)]
xilinx: use RAM32M/RAM64M for memories with two read ports

This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).

4 years agoRemoved a line jump into the CHANGELOG
Rodrigo Alejandro Melo [Sun, 2 Feb 2020 01:48:03 +0000 (22:48 -0300)]
Removed a line jump into the CHANGELOG

Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
4 years agoAdded tests/memfile to 'make test' with an extra testcase
Rodrigo Alejandro Melo [Sun, 2 Feb 2020 01:44:06 +0000 (22:44 -0300)]
Added tests/memfile to 'make test' with an extra testcase

Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
4 years agoAdded a test for the Memory Content File inclusion using $readmemb
Rodrigo Alejandro Melo [Sat, 1 Feb 2020 20:41:10 +0000 (17:41 -0300)]
Added a test for the Memory Content File inclusion using $readmemb

Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
4 years agoFixed a bug in the new feature of $readmem[hb] when an empty string is provided
Rodrigo Alejandro Melo [Sat, 1 Feb 2020 20:03:56 +0000 (17:03 -0300)]
Fixed a bug in the new feature of $readmem[hb] when an empty string is provided

Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
4 years agoxilinx_dsp: Add multonly scratchpad var to bypass
David Shah [Mon, 27 Jan 2020 11:19:27 +0000 (11:19 +0000)]
xilinx_dsp: Add multonly scratchpad var to bypass

Signed-off-by: David Shah <dave@ds0.me>
4 years agojson: remove the 32-bit parameter special case
Marcin Kościelnicki [Sat, 1 Feb 2020 09:21:19 +0000 (10:21 +0100)]
json: remove the 32-bit parameter special case

Before, the rules for encoding parameters in JSON were as follows:

- if the parameter is not a string:

  - if it is exactly 32 bits long and there are no z or x bits, emit it
    as an int
  - otherwise, emit it as a string made of 0/1/x/z characters

- if the parameter is a string:

  - if it contains only 0/1/x/z characters, append a space at the end
    to distinguish it from a non-string
  - otherwise, emit it directly

However, this caused a problem in the json11 parser used in nextpnr:
yosys emits unsigned ints, and nextpnr parses them as signed, using
the value of INT_MIN for values that overflow the signed int range.
This caused destruction of LUT5 initialization values.  Since both
nextpnr and yosys parser can also accept 32-bit parameters in the
same encoding as other widths, let's just remove that special case.
The old behavior is still left behind a `-compat-int` flag, in case
someone relies on it.

4 years agoModified the new search for files of $readmem[hb] to be backward compatible
Rodrigo Alejandro Melo [Sat, 1 Feb 2020 01:10:51 +0000 (22:10 -0300)]
Modified the new search for files of $readmem[hb] to be backward compatible

Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
4 years ago$readmem[hb] file inclusion is now relative to the Verilog file
Rodrigo Alejandro Melo [Fri, 31 Jan 2020 21:20:22 +0000 (18:20 -0300)]
$readmem[hb] file inclusion is now relative to the Verilog file

Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
4 years agoMerge pull request #1668 from gsomlo/gls-abc9-external
Eddie Hung [Fri, 31 Jan 2020 09:34:13 +0000 (09:34 +0000)]
Merge pull request #1668 from gsomlo/gls-abc9-external

abc9: Fix regression breaking support for use of ABCEXTERNAL

4 years agoabc9: restore ability to use ABCEXTERNAL
Gabriel Somlo [Thu, 30 Jan 2020 20:12:43 +0000 (15:12 -0500)]
abc9: restore ability to use ABCEXTERNAL

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
4 years agoMerge pull request #1667 from YosysHQ/clifford/verificnand
Claire Wolf [Thu, 30 Jan 2020 18:55:53 +0000 (19:55 +0100)]
Merge pull request #1667 from YosysHQ/clifford/verificnand

Add Verific support for OPER_REDUCE_NAND

4 years agoMerge pull request #1503 from YosysHQ/eddie/verific_help
Claire Wolf [Thu, 30 Jan 2020 17:05:16 +0000 (18:05 +0100)]
Merge pull request #1503 from YosysHQ/eddie/verific_help

`verific` pass to print help message when command syntax error

4 years agoMerge pull request #1654 from YosysHQ/eddie/sby_fix69
Claire Wolf [Thu, 30 Jan 2020 17:03:35 +0000 (18:03 +0100)]
Merge pull request #1654 from YosysHQ/eddie/sby_fix69

verific: unflatten struct ports

4 years agoAdd Verific support for OPER_REDUCE_NAND
Claire Wolf [Thu, 30 Jan 2020 17:01:13 +0000 (18:01 +0100)]
Add Verific support for OPER_REDUCE_NAND

Signed-off-by: Claire Wolf <clifford@clifford.at>
4 years agoMerge branch 'vector_fix' of https://github.com/Kmanfi/yosys
Claire Wolf [Wed, 29 Jan 2020 16:01:24 +0000 (17:01 +0100)]
Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys

Also some minor fixes to the original PR.

4 years agoMerge pull request #1662 from YosysHQ/dave/opt-reduce-move-check
Claire Wolf [Wed, 29 Jan 2020 14:27:11 +0000 (15:27 +0100)]
Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-check

opt_reduce: Call check() per run rather than per optimised cell

4 years agoMerge pull request #1665 from YosysHQ/clifford/edifkeep
Claire Wolf [Wed, 29 Jan 2020 14:25:56 +0000 (15:25 +0100)]
Merge pull request #1665 from YosysHQ/clifford/edifkeep

Preserve wires with keep attribute in EDIF back-end

4 years agoMerge pull request #1659 from YosysHQ/clifford/experimental
Claire Wolf [Wed, 29 Jan 2020 14:25:03 +0000 (15:25 +0100)]
Merge pull request #1659 from YosysHQ/clifford/experimental

Add log_experimental() and experimental() API and "yosys -x"

4 years agoMerge pull request #1510 from pumbor/master
N. Engelhardt [Wed, 29 Jan 2020 14:21:28 +0000 (15:21 +0100)]
Merge pull request #1510 from pumbor/master

handle anonymous unions to fix #1080

4 years agoPreserve wires with keep attribute in EDIF back-end
Claire Wolf [Wed, 29 Jan 2020 13:07:11 +0000 (14:07 +0100)]
Preserve wires with keep attribute in EDIF back-end

Signed-off-by: Claire Wolf <clifford@clifford.at>
4 years agoMerge pull request #1559 from YosysHQ/efinix_test_fix
Miodrag Milanović [Wed, 29 Jan 2020 10:18:06 +0000 (11:18 +0100)]
Merge pull request #1559 from YosysHQ/efinix_test_fix

Fix for non-deterministic test

4 years agoAdd "help -all" and "help -celltypes" sanity test
Eddie Hung [Wed, 29 Jan 2020 02:11:34 +0000 (18:11 -0800)]
Add "help -all" and "help -celltypes" sanity test

4 years agosynth_xilinx: cleanup help
Eddie Hung [Wed, 29 Jan 2020 01:48:43 +0000 (17:48 -0800)]
synth_xilinx: cleanup help

4 years agosynth_xilinx: fix help when no active_design; fixes #1664
Eddie Hung [Wed, 29 Jan 2020 01:41:57 +0000 (17:41 -0800)]
synth_xilinx: fix help when no active_design; fixes #1664

4 years agoxilinx: Add simulation model for DSP48 (Virtex 4).
Marcin Kościelnicki [Thu, 21 Nov 2019 12:05:30 +0000 (13:05 +0100)]
xilinx: Add simulation model for DSP48 (Virtex 4).

4 years agoMerge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
Eddie Hung [Tue, 28 Jan 2020 19:55:51 +0000 (11:55 -0800)]
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts

Unpermute LUT ordering for ice40/ecp5/xilinx

4 years agoAdd and use SigSpec::reverse()
Eddie Hung [Tue, 28 Jan 2020 18:37:16 +0000 (10:37 -0800)]
Add and use SigSpec::reverse()

4 years agoFix unresolved conflict from #1573
Eddie Hung [Tue, 28 Jan 2020 18:17:47 +0000 (10:17 -0800)]
Fix unresolved conflict from #1573

4 years agoUpdated test to use assert-max
Miodrag Milanovic [Tue, 28 Jan 2020 17:26:10 +0000 (18:26 +0100)]
Updated test to use assert-max

4 years agoImprove logging use of experimental features
Claire Wolf [Tue, 28 Jan 2020 16:51:50 +0000 (17:51 +0100)]
Improve logging use of experimental features

Signed-off-by: Claire Wolf <clifford@clifford.at>
4 years agoMerge pull request #1567 from YosysHQ/eddie/sat_init_warning
Claire Wolf [Tue, 28 Jan 2020 16:40:28 +0000 (17:40 +0100)]
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning

sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx

4 years agoMerge pull request #1573 from YosysHQ/eddie/xilinx_tristate
N. Engelhardt [Tue, 28 Jan 2020 16:24:54 +0000 (17:24 +0100)]
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate

synth_xilinx: error out if tristate without '-iopad'

4 years agoopt_reduce: Call check() per run rather than per optimised cell
David Shah [Tue, 28 Jan 2020 09:42:01 +0000 (09:42 +0000)]
opt_reduce: Call check() per run rather than per optimised cell

Signed-off-by: David Shah <dave@ds0.me>
4 years agoredirect fuser stderr to /dev/null
Pepijn de Vos [Tue, 26 Nov 2019 11:56:06 +0000 (12:56 +0100)]
redirect fuser stderr to /dev/null

4 years agoMerge pull request #1553 from whitequark/manual-dffx
Claire Wolf [Tue, 28 Jan 2020 08:41:08 +0000 (09:41 +0100)]
Merge pull request #1553 from whitequark/manual-dffx

Document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells

4 years agoFix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
Eddie Hung [Mon, 27 Jan 2020 22:02:13 +0000 (14:02 -0800)]
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards

Just like Verilog...

4 years agoImport tests from #1628
Eddie Hung [Mon, 27 Jan 2020 21:56:16 +0000 (13:56 -0800)]
Import tests from #1628

4 years agoxilinx/ice40/ecp5: undo permuting LUT masks in lut_map
Eddie Hung [Tue, 21 Jan 2020 20:29:07 +0000 (12:29 -0800)]
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map

Now done in read_aiger

4 years agoMerge pull request #1619 from YosysHQ/eddie/abc9_refactor
Eddie Hung [Mon, 27 Jan 2020 21:29:15 +0000 (13:29 -0800)]
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor

Refactor `abc9` pass

4 years agoabc9_ops: add comments
Eddie Hung [Mon, 27 Jan 2020 19:18:21 +0000 (11:18 -0800)]
abc9_ops: add comments

4 years agoMerge remote-tracking branch 'origin/master' into eddie/verific_help
Eddie Hung [Mon, 27 Jan 2020 18:34:10 +0000 (10:34 -0800)]
Merge remote-tracking branch 'origin/master' into eddie/verific_help

4 years agoverific: no help() when no YOSYS_ENABLE_VERIFIC
Eddie Hung [Mon, 27 Jan 2020 18:32:18 +0000 (10:32 -0800)]
verific: no help() when no YOSYS_ENABLE_VERIFIC

4 years agoverific: also unflatten for 'hierarchy' flow as per @cliffordwolf
Eddie Hung [Mon, 27 Jan 2020 18:15:22 +0000 (10:15 -0800)]
verific: also unflatten for 'hierarchy' flow as per @cliffordwolf

4 years agoMerge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings
Eddie Hung [Mon, 27 Jan 2020 17:54:04 +0000 (09:54 -0800)]
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings

ice40: reduce ABC9 internal fanout warnings with a param for CI->I3

4 years agoAdd log_experimental() and experimental() API and "yosys -x"
Claire Wolf [Mon, 27 Jan 2020 17:27:47 +0000 (18:27 +0100)]
Add log_experimental() and experimental() API and "yosys -x"

Signed-off-by: Claire Wolf <clifford@clifford.at>
4 years agoMerge pull request #1658 from YosysHQ/clifford/smtbmcsolvernotfound
Claire Wolf [Mon, 27 Jan 2020 16:59:58 +0000 (17:59 +0100)]
Merge pull request #1658 from YosysHQ/clifford/smtbmcsolvernotfound

Improve yosys-smtbmc "solver not found" handling

4 years agoImprove yosys-smtbmc "solver not found" handling
Claire Wolf [Mon, 27 Jan 2020 16:48:56 +0000 (17:48 +0100)]
Improve yosys-smtbmc "solver not found" handling

Signed-off-by: Claire Wolf <clifford@clifford.at>
4 years agoMerge pull request #1613 from porglezomp-misc/version-flag-alias
Claire Wolf [Mon, 27 Jan 2020 11:59:27 +0000 (12:59 +0100)]
Merge pull request #1613 from porglezomp-misc/version-flag-alias

Add --version and -version as aliases for -V

4 years agoread_aiger: set abc9_box_seq attr
Eddie Hung [Fri, 24 Jan 2020 21:11:43 +0000 (13:11 -0800)]
read_aiger: set abc9_box_seq attr

4 years agoice40: add SB_SPRAM256KA arrival time
Eddie Hung [Fri, 24 Jan 2020 20:16:05 +0000 (12:16 -0800)]
ice40: add SB_SPRAM256KA arrival time

4 years agoice40: reduce ABC9 internal fanout warnings with a param for CI->I3
Eddie Hung [Fri, 24 Jan 2020 19:59:48 +0000 (11:59 -0800)]
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3

4 years agoverific: unflatten struct ports
Eddie Hung [Fri, 24 Jan 2020 18:12:52 +0000 (10:12 -0800)]
verific: unflatten struct ports

4 years agoabc9: -reintegrate recover type from existing cell, check against boxid
Eddie Hung [Fri, 24 Jan 2020 06:45:34 +0000 (22:45 -0800)]
abc9: -reintegrate recover type from existing cell, check against boxid

4 years agosimple_abc9 tests to discard whitebox before write for sim
Eddie Hung [Fri, 24 Jan 2020 03:55:11 +0000 (19:55 -0800)]
simple_abc9 tests to discard whitebox before write for sim

4 years agosimple_abc9 tests to discard whitebox before write for sim
Eddie Hung [Fri, 24 Jan 2020 03:55:11 +0000 (19:55 -0800)]
simple_abc9 tests to discard whitebox before write for sim

4 years agoabc_box_id -> abc9_box_id in test
Eddie Hung [Fri, 24 Jan 2020 02:53:14 +0000 (18:53 -0800)]
abc_box_id -> abc9_box_id in test

4 years agoabc9: warning message if no modules selected
Eddie Hung [Fri, 24 Jan 2020 03:08:51 +0000 (19:08 -0800)]
abc9: warning message if no modules selected

4 years agoFix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
Eddie Hung [Wed, 22 Jan 2020 22:22:03 +0000 (14:22 -0800)]
Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0

4 years agoTest for (* keep *)-ed abc9_box_id
Eddie Hung [Fri, 24 Jan 2020 02:56:25 +0000 (18:56 -0800)]
Test for (* keep *)-ed abc9_box_id

4 years agoabc9_ops: -prep_xaiger to skip (* keep *) cells
Eddie Hung [Fri, 24 Jan 2020 02:56:06 +0000 (18:56 -0800)]
abc9_ops: -prep_xaiger to skip (* keep *) cells

4 years agoabc_box_id -> abc9_box_id in test
Eddie Hung [Fri, 24 Jan 2020 02:53:14 +0000 (18:53 -0800)]
abc_box_id -> abc9_box_id in test

4 years agoabc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_*
Eddie Hung [Thu, 23 Jan 2020 22:58:56 +0000 (14:58 -0800)]
abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_*

4 years agoalumacc: undo accidental commit
Eddie Hung [Thu, 23 Jan 2020 04:54:03 +0000 (20:54 -0800)]
alumacc: undo accidental commit

4 years agoFix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
Eddie Hung [Wed, 22 Jan 2020 22:22:03 +0000 (14:22 -0800)]
Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0

4 years agoread_aiger: also parse abc9_mergeability
Eddie Hung [Wed, 22 Jan 2020 22:21:25 +0000 (14:21 -0800)]
read_aiger: also parse abc9_mergeability

4 years agoMerge remote-tracking branch 'origin/eddie/abc9_fixes' into eddie/abc9_refactor
Eddie Hung [Wed, 22 Jan 2020 20:30:14 +0000 (12:30 -0800)]
Merge remote-tracking branch 'origin/eddie/abc9_fixes' into eddie/abc9_refactor

4 years agoMerge pull request #1652 from YosysHQ/eddie/abc9_fixes
Eddie Hung [Wed, 22 Jan 2020 20:27:41 +0000 (12:27 -0800)]
Merge pull request #1652 from YosysHQ/eddie/abc9_fixes

Eddie/abc9 fixes

4 years agoabc9: error out if flip-flop init is 1'b1 for '-dff'
Eddie Hung [Wed, 22 Jan 2020 18:08:48 +0000 (10:08 -0800)]
abc9: error out if flip-flop init is 1'b1 for '-dff'

Due to ABC sequential synthesis restriction

4 years agoabc9: fix scratchpad entry abc9.verify
Eddie Hung [Wed, 22 Jan 2020 17:36:54 +0000 (09:36 -0800)]
abc9: fix scratchpad entry abc9.verify

4 years agoMerge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Eddie Hung [Wed, 22 Jan 2020 00:27:40 +0000 (16:27 -0800)]
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor

4 years agoread_aiger: discard LUT inputs with nodeID == 0; not < 2
Eddie Hung [Tue, 21 Jan 2020 19:56:01 +0000 (11:56 -0800)]
read_aiger: discard LUT inputs with nodeID == 0; not < 2

4 years agoread_aiger: ignore constant inputs on LUTs
Eddie Hung [Tue, 21 Jan 2020 19:16:50 +0000 (11:16 -0800)]
read_aiger: ignore constant inputs on LUTs

4 years agowrite_xaiger: fix for (* keep *) on flop output
Eddie Hung [Tue, 21 Jan 2020 17:43:04 +0000 (09:43 -0800)]
write_xaiger: fix for (* keep *) on flop output

4 years agoMerge pull request #1637 from YosysHQ/mwk/fix-1634
Claire Wolf [Tue, 21 Jan 2020 17:37:06 +0000 (18:37 +0100)]
Merge pull request #1637 from YosysHQ/mwk/fix-1634

fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.

4 years agoMerge pull request #1629 from YosysHQ/mwk/edif-z
Claire Wolf [Tue, 21 Jan 2020 17:35:15 +0000 (18:35 +0100)]
Merge pull request #1629 from YosysHQ/mwk/edif-z

edif: Just ignore connections to 'z

4 years agoMerge pull request #1621 from YosysHQ/clifford/fminit
Claire Wolf [Mon, 20 Jan 2020 21:01:57 +0000 (22:01 +0100)]
Merge pull request #1621 from YosysHQ/clifford/fminit

Add fminit pass

4 years agoast: Add support for $sformatf system function
David Shah [Sun, 19 Jan 2020 21:15:51 +0000 (21:15 +0000)]
ast: Add support for $sformatf system function

Signed-off-by: David Shah <dave@ds0.me>
4 years agoMerge pull request #1643 from YosysHQ/eddie/cleanup_arith_map
Eddie Hung [Sat, 18 Jan 2020 17:11:52 +0000 (09:11 -0800)]
Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_map

Cleanup +/xilinx/arith_map.v

4 years agoMerge pull request #1602 from niklasnisbeth/ice40-init-vals-warning
David Shah [Sat, 18 Jan 2020 09:47:17 +0000 (09:47 +0000)]
Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warning

ice40: Demote conflicting FF init values to a warning

4 years agoMerge pull request #1645 from YosysHQ/eddie/fix1644
Eddie Hung [Sat, 18 Jan 2020 03:25:59 +0000 (19:25 -0800)]
Merge pull request #1645 from YosysHQ/eddie/fix1644

{ice40,xilinx}_dsp: improve robustess

4 years agoxilinx_dsp: another typo; move xilinx specific test
Eddie Hung [Sat, 18 Jan 2020 01:07:03 +0000 (17:07 -0800)]
xilinx_dsp: another typo; move xilinx specific test

4 years agoice40_dsp: fix typo
Eddie Hung [Sat, 18 Jan 2020 00:08:04 +0000 (16:08 -0800)]
ice40_dsp: fix typo

4 years agoConsistency
Eddie Hung [Sat, 18 Jan 2020 00:06:20 +0000 (16:06 -0800)]
Consistency

4 years agoxilinx_dsp: add parameter defaults
Eddie Hung [Sat, 18 Jan 2020 00:05:10 +0000 (16:05 -0800)]
xilinx_dsp: add parameter defaults

4 years agoAdd #1644 testcase
Eddie Hung [Fri, 17 Jan 2020 23:57:52 +0000 (15:57 -0800)]
Add #1644 testcase