r600/eg: rework atomic counter emission with flushes

With the current code, we didn't do the space checks prior
to atomic counter setup emission, but we also didn't add
atomic counters to the space check so we could get a flush
later as well.

These flushes would be bad, and lead to problems with
parallel tests. We have to ensure the atomic counter copy in,
draw emits and counter copy out are kept in the same command
submission unit.

This reworks the code to drop some useless masks, make the
counting separate to the emits, and make the space checker
handle atomic counter space.

[airlied: want this in 18.2]

Fixes: 06993e4ee (r600: add support for hw atomic counters. (v3))

virgl: ARB_enhanced_layouts support

We need to handle the gaps in the streamout bindings on the guest
side and enable if it the host has the rest enabled.

Reviewed-by: Jakob Bornecrantz <jakob@collabora.com>

i965: Implement EGL_KHR_mutable_render_buffer

Testing:
  - Manually tested a low-latency handwriting demo that toggles
    EGL_RENDER_BUFFER. Toggling changed the display latency as expected.
    Used Android on Chrome OS, Kabylake GT2.
  - No change in dEQP-EGL.functional.* on Fedora 27, Wayland, Skylake
    GT2.  Used deqp at tag android-p-preview-5.
  - No regressions in dEQP-EGL.functional.*, ran on Android on Chrome
    OS, Kabylake GT2. Some dEQP-EGL.functional.mutable_render_buffer.*
    test change from NotSupported to Pass.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

egl/android: Implement EGL_KHR_mutable_render_buffer

Specifically, implement the extension DRI_MutableRenderBufferLoader.
However, the loader enables EGL_KHR_mutable_render_buffer only if the
DRI driver implements its half of the extension,
DRI_MutableRenderBufferDriver.

Testing:
  - No change in dEQP-EGL.functional.* on Fedora 27, Wayland, Skylake
    GT2.  Used deqp at tag android-p-preview-5.
  - No change in dEQP-EGL.functional.*, ran on Android on Chrome OS,
    Kabylake GT2.
  - Manually inspected Android apps on same Chrome OS device.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

util/xmlpool: make indentation coherent

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

egl: add helper to combine two u32 into one u64

Use a helper to avoid the common issues of upcasting after the right shift
(losing the upper bits) and shifting signed values (sign gets shifted too).

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

docs: trivial s/>/&gt;/ html fix

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

autotools: don't ship the git_sha1.h generated in git in the tarballs

This file is regenerated at build time anyway, so this would just get
overwritten anyway. No reason to ship it in the tarball.

Fixes: 44df06211cf2c301f6ef "autotools: include git_sha1.h in dist tarball"
Fixes: 471f708ed6f4787813d0 "git_sha1: simplify logic"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

intel/genxml: minor python style fix

Suggested-by: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>

appveyor: Set git core.autocrlf setting to true.

The git core.autocrlf setting defaults to true (ie, all text files get
checked out as CRLF on Windows), except on Appveyor where's set to
"input" (ie, all text files get checked out with the upstream
repository's line endings, which for us typically means LF.)

And this was masking on Appveyor a regression in gen_xmlpool.py
processing t_options.h with CRLF line endings.

This change makes core.autocrlf to be true, which would have enabled to
immediately catch the issue, as seen in
https://ci.appveyor.com/project/jrfonseca/mesa/build/51

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: move legacy hyperz option from dri config

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: remove unused dri config option disable_shader_bit_encoding

This was added as a workaround for Heaven 3.0 but was later removed
by 5ead448719f3 to allow Heaven 4.0 to work correctly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: drop legacy no_rast dri option

Add enviroment var overrides to legacy drivers instead.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: remove unused no_rast bool

Forcing software fallbacks for i965 hasn't been an option since
5e3c093ff866.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i915: remove early_z dri option

This driver is in maintenance mode so lets remove this hidden
unsafe option.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

Add NV_fragment_shader_interlock support.

The main purpose for having NV_fragment_shader_interlock
extension is because that extension is also for GLES31 while
the ARB extension is for GL only.

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>

autotools: include git_sha1.h in dist tarball

This fixes `make distcheck`.

Fixes: 471f708ed6 ("git_sha1: simplify logic")
CC: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

swr: bump minimum supported LLVM version to 6.0

RADV now requires LLVM 6.0 or greater, and thus we can't build dist
tarball because swr requires LLVM 5.0.

Let's bump required LLVM to 6.0 in swr too.

v2: bump also in meson.build (Eric)

Fixes: fd1121e839 ("amd: remove support for LLVM 5.0")
Cc: Tim Rowley <timothy.o.rowley@intel.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Cc: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

i965: Advertise 8 bits subpixel precision for viewport bounds on gen6+

We use floating-points for viewport bounds so VIEWPORT_SUBPIXEL_BITS
should reflect this.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105975

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

freedreno: fix context teardown race

We could still have batches queued up to flush, so fd_context_destroy()
(which will kill and sync on the flush_queue) before deleting buffers
that might be referenced from fdN_gmem() from context of flush_queue.

Signed-off-by: Rob Clark <robdclark@gmail.com>

intel/decoder: mark total_length as MAYBE_UNUSED in gen_spec_load

Only used, when asserts are enabled.

Fixes an unused-variable warning with GCC 8:
 ../../../src/intel/common/gen_decoder.c: In function 'gen_spec_load':
 ../../../src/intel/common/gen_decoder.c:535:47: warning: variable 'total_length' set but not used [-Wunused-but-set-variable]
     uint32_t text_offset = 0, text_length = 0, total_length;
                                                ^~~~~~~~~~~~

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/tools: initialise bo_addr to 0 in main

Supresses a maybe-uninitialized warning with GCC 8.

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel: aubinator: mark ftruncate_res as MAYBE_UNUSED in ensure_phys_mem

Only used, when asserts are enabled.

Fixes an unused-variable warning with GCC 8:
 ../../../src/intel/tools/aubinator.c: In function 'ensure_phys_mem':
 ../../../src/intel/tools/aubinator.c:209:11: warning: unused variable 'ftruncate_res' [-Wunused-variable]
        int ftruncate_res = ftruncate(mem_fd, mem_fd_len += 4096);
            ^~~~~~~~~~~~~

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/aubinator_error_decode: mark ret as MAYBE_UNUSED in main

Only used, when asserts are enabled.

Fixes an unused-but-set-variable warning with GCC 8:
 ../../../src/intel/tools/aubinator_error_decode.c: In function 'main':
 ../../../src/intel/tools/aubinator_error_decode.c:759:11: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
        int ret;
            ^~~

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

radv: do not use CP predication for DCC decompressions

This fixes a regression with some Unity demos. Not sure
what the root cause of the problem is, especially because
the driver doesn't perform any fast color clears. So, it
shouldn't be needed to decompress DCC. RadeonSI says that
the decompression is relatively cheap if the surface has
been decompressed already.

One possible improvement is to two use predicates, one for
DCC and one for FCE that could be cleared when DCC, FMASK
or CMASK are performed by the driver. That might skip some
unnecessary decompression passes (not DCC though).

Fixes: ff7daadca1 ("radv: enable/disable predication for the DCC decompression pass")
CC: 18.2 <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107563
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

egl: implement EXT_surface_SMPTE2086_metadata and EXT_surface_CTA861_3_metadata

Patch implements common bits for EXT_surface_SMPTE2086_metadata
and EXT_surface_CTA861_3_metadata extensions by adding new required
attributes and eglQuerySurface + eglSurfaceAttrib changes.

Currently none of the drivers are utilizing this data but this patch
is enabler in getting there.

v2: don't enable extension globally, should be only enabled by
    EGL drivers that can transfer metadata to the window system (Jason)
    use EGLint instead of uint16_t (Eric)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

mesa: move legacy dri config option texture_units

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove unused dri config option texture_heaps

This seems to have only been used by DRI1 drivers which were
removed with e4344161bde2.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: move legacy dri config option texture_blend_quality

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

util: remove unused S3TC translation for dri config

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove dri configs unused software-fallback options

These seems to have only been used by DRI1 drivers which were
removed with e4344161bde2.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove unused dri config option excess_mipmap

This seems to have only been used by DRI1 drivers which were
removed with e4344161bde2.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove unused dri config option performance_boxes

This seems to have only been used by DRI1 drivers which were
removed with e4344161bde2.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

docs: update the default mesa shader cache dir

We renamed the dir in commit 28b326238bcc, this just updates the
website to reflect the change.

vulkan/wsi: initialise image_index to 0 in x11_manage_fifo_queues

Supresses a maybe-uninitialized warning with GCC 8.

Note: image_index should always be initialised due to the result check,
      but the compiler doesn't see that.

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

nir: mark *prev_block as MAYBE_UNUSED in opt_peel_loop_initial_if

Only used, when asserts are enabled.

Fixes an unused-variable warning with gcc-8:
 ../../../src/compiler/nir/nir_opt_if.c: In function 'opt_peel_loop_initial_if':
 ../../../src/compiler/nir/nir_opt_if.c:109:15: warning: unused variable 'prev_block' [-Wunused-variable]
     nir_block *prev_block =
                ^~~~~~~~~~

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

util: mark s as MAYBE_UNUSED in _mesa_half_to_unorm8

Only used, when asserts are enabled.

Fixes an unused-variable warning with gcc-8:
 ../../../src/util/half_float.c: In function '_mesa_half_to_unorm8':
 ../../../src/util/half_float.c:189:14: warning: unused variable 's' [-Wunused-variable]
     const int s = (val >> 15) & 0x1;
               ^

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

util: add drirc workarounds for RAGE

This allows the game to run on wine (tested on radeonsi where we
have compat profile support).

util: better handle program names from wine

For some reason wine will sometimes give us a windows style path
for an application. For example when running the 64bit version
of Rage wine gives a Unix style path, but when running the 32bit
version is gives a windows style path.

If we detect no '/' in the path at all it should be safe to
assume we have a wine application and instead look for a '\'.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

nir: allow more nested loops to be unrolled

The innermost check was added to stop us from unrolling multiple
loops in a single pass, and to stop outer loops from unrolling.

When we successfully unroll a loop we need to run the analysis
pass again before deciding if we want to go ahead an unroll a
second loop.

However the logic was flawed because it never tried to unroll any
nested loops other than the first innermost loop it found.
If this innermost loop is not unrolled we end up skipping all
other nested loops.

This unrolls a loop in a Deus Ex: MD shader on ultra settings and
also unrolls a loop in a shader from the game Prey when running
on DXVK.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

gallium/winsys/kms: don't unmap what wasn't mapped

At the moment, depending on pipe transfer flags, the dumb
buffer map address can end up at either kms_sw_dt->ro_mapped
or kms_sw_dt->mapped.

When it's time to unmap the dumb buffer, both locations get unmapped,
even though one is probably initialized to 0.

That leads to the code segment getting unmapped at runtime and
crashes when trying to call into unrelated code.

This commit addresses the problem by using MAP_FAILED instead of
NULL for ro_mapped and mapped when the dumb buffer is unmapped,
and only unmapping mapped addresses at unmap time.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107098
Signed-off-by: Ray Strode <rstrode@redhat.com>
Fixes: d891f28df9a ("gallium/winsys/kms: Fix possible leak in map/unmap.")
Cc: Lepton Wu <lepton@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

loader: add dri_driver option to override dri driver to load

drirc implementation of MESA_LOADER_DRIVER_OVERRIDE which can be
used to override dri driver to load.

Usage:

override dri driver for device with spec kernel driver name:

<device kernel_driver="kernel_driver_name">
  <option name="dri_driver" value="new_dri_driver" />
</device>

or

<device driver="loader" kernel_driver="kernel_driver_name">
  <option name="dri_driver" value="new_dri_driver" />
</device>

v2:
  add kernel_driver device attribute to specify kernel
  driver name instead of reuse driver attribute

v3:
  seperate loader_get_kernel_driver_name into another patch
  seperate add kernel_driver attribute into another patch

Suggested-by: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[v4 Emil: add HAVE_LIBDRM guard around __driConfigOptionsLoader and
loader_get_dri_config_driver]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

xmlconfig: add kernel_driver device attribute

This attribute can be used by loader to apply different
option to device use specific kernel driver.

Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

loader: abstract loader_get_kernel_driver_name for reuse

This function can be shared by the following kernel_driver
drirc patch.

Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

driconf: move ${sysconfdir}/drirc to ${datadir}/drirc.d/00-mesa-defaults.conf

${sysconfdir} is for store admin config files, so move
this mesa default config file to ${datadir}/drirc.d.

Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

xmlconfig: read more config files from drirc.d/

Driver and application can put their drirc files in
${datadir}/drirc.d/ with name xxx.conf. Config files
will be read and applied in file name alphabetic order.

So there are three places for drirc listed in order:
1. /usr/share/drirc.d/
2. /etc/drirc
3. ~/.drirc

v4:
  fix meson build

v3:
  1. seperate driParseConfigFiles refine into another patch
  2. fix entries[i] mem leak

v2:
  drop /etc/drirc.d

Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

xmlconfig: refine driParseConfigFiles to use parseOneConfigFile

Also prepare for the usage of following parseConfigDir patch.

Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[Emil: add #include <limits.h>]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

anv/pipeline: Lower pipeline layouts etc. after linking

This allows us to use the link-optimized shader for determining binding
table layouts and, more importantly, URB layouts.  For apps running on
DXVK, this is extremely important as DXVK likes to declare max-size
inputs and outputs and this lets is massively shrink our URB space
requirements.

VkPipeline-db results (Batman pipelines only) on KBL:

    total instructions in shared programs: 820403 -> 790008 (-3.70%)
    instructions in affected programs: 273759 -> 243364 (-11.10%)
    helped: 622
    HURT: 42

    total spills in shared programs: 8449 -> 5212 (-38.31%)
    spills in affected programs: 3427 -> 190 (-94.46%)
    helped: 607
    HURT: 2

    total fills in shared programs: 11638 -> 6067 (-47.87%)
    fills in affected programs: 5879 -> 308 (-94.76%)
    helped: 606
    HURT: 3

Looking at shaders by hand, it makes the URB between TCS and TES go from
containing 32 per-vertex varyings per tessellation shader pair to a more
reasonable 8-12.  For a 3-vertex patch, that's at least half the URB
space no matter how big the patch section is.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

anv/pipeline: Set tess IO read/written key fields in compile_*

We want these to be set as close to the final compile as possible so
that they are guaranteed to happen after nir_shader_gather_info is
called.  The next commit is going to move nir_shader_gather_info to
after the linking step which makes this necessary.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

anv/pipeline: Use more fields from stage in compile_cs

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/apply_pipeline_layout: Add to the bind map instead of replacing it

This commit makes three changes.  One is to only walk the descriptors once
and set bind map sizes at the same time as filling out the entries.  The
second is to make the pass additive so that we can put stuff in the bind
map before applying the pipeline layout.  Third, we switch to using
designated initializers.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/lower_ycbcr: Use the binding array size for bounds checks

Because lower_ycbcr gets called before apply_pipeline_layout, the
indices are all logical and the binding layout HW size is actually too
big for the bounds check.  We should just use the regular logical array
size instead.

Fixes: f3e91e78a33 "anv: add nir lowering pass for ycbcr textures"
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

python: Open the template as text, with an explicit encoding

In commit bd27203f4d808763ac24ac94eb677cacf3e7cb99 we changed this to
open in binary mode, to then explicitly decode the lines with the right
encoding.

Unfortunately, that broke the build on Windows, where the template file
can have '\r\n' as line terminators: opening in binary mode would keep
those terminators and break the regexp.

We need to go back to text mode, where the "universal newlines" mode
takes care of this.

However, to fix the initial issue, let's specify the encoding explicitly
when opening the file, and make sure it is open in text mode, so we only
get unicode strings.

Reviewed-by: Jose Fonseca <jfonseca@vmware>

python: Help Python 2 print the line

Reviewed-by: Jose Fonseca <jfonseca@vmware>

freedreno/a6xx: streamout

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a6xx: fragz fixes

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a6xx: scissor fixes

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: update generated headers

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a6xx: fix srgb

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: fix dEQP-GLES3.functional.fence_sync.*

Signed-off-by: Rob Clark <robdclark@gmail.com>

radv/winsys: fix creating the BO list for virtual buffers

When the number of unique BO is 0, we optimize the list creation
by copying all buffers of the current CS directly into it. But
this is only valid if the CS doesn't have virtual buffers,
otherwise they are not added and hw might report VM faults.

This fixes VM faults with:
dEQP-VK.sparse_resources.image_sparse_binding.2d.rgba8ui.1024_128_1

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

freedreno: Add a6xx backend

This adds a freedreno backend for the a6xx generation GPUs, which at
the time of this commit is about 98% GLES2 conformant. Much remains to
be done - both performance work and feature work towards more recent
GLES versions, but this is a good start.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: update generated headers

pull in a6xx registers

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: Fix warnings

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

scons: Check for mako 0.8.0

v2: - Use distutils to do the version checking

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107565
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

scons: Require python 2.7

less than 2.7 is not supported.

v2: - Remove check for python >= 2.0, since we've already enforced 2.7

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

meson: use python3 module to find python3

This handy helper is nice for OSes that are not linux or BSD like (mac
and windows) as it knows how to find python3 in odd places.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

meson: Ensure that mako is >= 0.8.0

It's what autotools has required for a long time.

v3: - Use distutils.version.StrictVersion instead of comparing strings

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

svga: simplify Mesa version string

Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

bin: always define MESA_GIT_SHA1 to make it directly usable in code

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

git_sha1: simplify logic

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

i965: drop unused assignment

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: drop cast-to-void of used variable

`device` is used 2 lines below, even visible in the diff context printed.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: use safer snprintf() to ensure NULL string-terminator

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: replace local ARRAY_LENGTH() macro with global ARRAY_SIZE()

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel: various python cleanups

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: check for buffer overflow *before* corrupting our memory

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl/wayland: remove sign from bitfield `formats`

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

mailmap: add various typos of Emil's address from the log

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: some spelling fixes

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>

radv: initialize the DCC predicate correctly when it's compressed

We have to do a fast-clear eliminate when clearing DCC
metadata with 0x20202020. I don't know if that fixes anything
but that seems correct to me.

CC: 18.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: fix missing initialization of the conditional rendering state

This was missing when VK_EXT_conditional_rendering has been
implemented. The predication type should be -1 to avoid
restoring previous state when performing a decompression pass
with DCC enabled.

Note that we don't have to handle secondary command buffers
because we don't support this feature currently.

CC: 18.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

bin: split `write_if_different()` out

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

bin: whitespace cleanup

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

radv: Revert divisor = 0 case for vertex attribute extension.

Seems like DXVK depends on that and it might get reverted
upstream. Since apps are not supposed to use 0 in v2 anyway,
we should be safe implementing the old behavior there.

Fixes: 66e12451ac4 "radv: Update to new VK_EXT_vertex_attribute_divisor to version 2."
CC: 18.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Possible on-demand compilation fix.

Seems that in a single case we use the renderpass before checking
the pipeline, so check the renderpass before we use it.

Fixes: fbcd1673144 "radv: Add on-demand compilation of built-in shaders."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa/st: fix array indices off-by-one error in remapping

When moving the array sizes from the old list to the new one it was
not taken into account that the array indices start with one, but the
array_size array started at index zero, which resulted in incorrect array
sizes when arrays were merged. Correct this by copying the array_size
values of the retained arrays with an offset of -1.

Also fix whitespaces for the replaced lines.

Fixes: d8c2119f9b0b257a23ceb398f6d0d78da916417e
  mesa/st/glsl_to_tgsi: Expose array live range tracking and merging
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

meson: fix build for egl platform_x11 without dri3 and gbm

Compiling EGL's platform_x11 without dri3 and gbm yields this compile
failure:

platform_x11 needs inc_loader:

../mesa-18.2.0-rc2/src/egl/drivers/dri2/platform_x11.c:48:10: fatal
error: loader.h: No such file or directory
 #include "loader.h"
          ^~~~~~~~~~

Fixes: 108d257a1685 ("meson: build libEGL")
Bugzilla: https://bugs.gentoo.org/663534
Reviewed-by: Matt Turner <mattst88@gmail.com>

Revert "intel/nir: Call nir_lower_io_to_scalar_early"

Commit 4434591bf56a6b0 caused substantially more URB messages in
geometry and tessellation shaders.  Before we can really enable this
sort of optimization,  We either need some way of combining them back
together into vectors or we need to do cross-stage vector element
elimination without splitting everything into scalars.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107510
Fixes: 4434591bf56a6 "intel/nir: Call nir_lower_io_to_scalar_early"
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Mark Janes <mark.a.janes@intel.com>

i965: do not emit empty surface state

If called with an empty size, brw_emit_buffer_surface_state asserts.
We already have a dedicated helper for uploading nothing, so let's use
that instead.

Avoids an assert in
dEQP-GLES31.functional.shaders.opaque_type_indexing.ssbo.const_literal_vertex
when running a debug build of i965.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/ppgtt: 4096 replaced by PAGE_SIZE

Usage of number 4096 replaced by PAGE_SIZE.

Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/ppgtt: memory address alignment

Kernel (for ppgtt) requires memory address to be
aligned to page size (4096).

-v2: added marking that also fixes initial commit 01058a552294.
-v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
instead of alignment of offsets (Chris Wilson).
-v4: changes related to PAGE_SIZE moved to separate commit
-v5: restored alignment to page-size for 0-size.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997
Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT systems.)
Fixes: 01058a552294 (i965: Add virtual memory allocator infrastructure to brw_bufmgr.)
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

radv: add Doom workaround

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

i965: Emitting 3DSTATE_SO_BUFFER of 0-size.

Avoided filling of whole structure and bo-allocation if
size of surface is 0.

Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>

virgl: report actual max-texture sizes

Instead of doing conservative guesses, we should report the max levels
based on the max sizes we get from GL on the host.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jakob Bornecrantz <jakob@collabora.com>

virgl: do not use SP_MAX_TEXTURE_*_LEVELS defines

These macro-names are also used for softpipe, so let's avoid confusion
by avoiding them. Besides, they are just used in one place in virgl, so
let's just inline them into the place they are used instead.

While we're at it, fixup an error in the comment for the 3D version.
Mesa subtracts computes max-size by doing by 2^(n-1), which means this
should be 256 cubed, not 512 cubed. The other comments are correct.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jakob Bornecrantz <jakob@collabora.com>

docs: Add news item for 18.1.6

radv: disable the auto-waitcnt-before-barrier LLVM option

This option allows us to remove additional s_waitcnt instructions
because s_barrier internally does s_waitcnt 0.

Though, apparently there is a problem with LDS accesses that
causes rendering issues with FFXV and DXVK. Disable this
optimization for now (RadeonSI still uses it).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107460
CC: 18.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: fix memory leaks in radv_load_meta_pipeline()

Reported by Coverity.

Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: drop wrong initialization of COMPUTE_RESOURCE_LIMITS

The last parameter of radeon_set_sh_reg_seq() is the number of
dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but
it was initialized to 0.

COMPUTE_RESOURCE_LIMITS is correctly set when generating
compute pipelines, so we don't need to initialize it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>