Merge pull request #740 from daveshah1/improve_dress

Improve ABC netname preservation

Hotfix for 4c82ddf

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #822 from litghost/expand_setundef

Add -params mode to force undef parameters in selected cells.

Add -params mode to force undef parameters in selected cells.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Merge pull request #818 from YosysHQ/clifford/dffsrfix

Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816

Merge pull request #786 from YosysHQ/pmgen

Pattern Matcher Generator and iCE40 DSP Mapper

Fix typo in passes/pmgen/README.md

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #821 from eddiehung/dff_init

Revert "Add -B option to autotest.sh to append to backend_opts"

Revert "Add -B option to autotest.sh to append to backend_opts"

This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b.

Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Bugfix in ice40_dsp

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #817 from eddiehung/dff_init

Cleanup #805

Remove simple_defparam tests

Add ice40 test_dsp_map test case generator

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "synth_ice40 -dsp"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add FF support to wreduce

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve iCE40 SB_MAC16 model

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Detect and reject cases that do not map well to iCE40 DSPs (yet)

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #805 from eddiehung/dff_init

write_verilog to write initial statement for initial flop state

Add first draft of functional SB_MAC16 model

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Instead of INIT param on cells, use initial statement with hier ref as
per @cliffordwolf

Revert "Add INIT parameter to all ff/latch cells"

This reverts commit 742b4e01b498ae2e735d40565f43607d69a015d8.

Merge https://github.com/YosysHQ/yosys into dff_init

Add actual DSP inference to ice40_dsp pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'master' of github.com:YosysHQ/yosys into pmgen

Merge pull request #811 from ucb-bar/firrtlfixes

Update cells supported for verilog to FIRRTL conversion.

Removed unused variables, functions.

Append (instead of over-writing) EXTRA_FLAGS

Update cells supported for verilog to FIRRTL conversion.
Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.

Fix sign handling of real constants

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #802 from whitequark/write_verilog_async_mem_ports

write_verilog: correctly emit asynchronous transparent ports

Merge pull request #806 from daveshah1/fsm_opt_no_reset

fsm_opt: Fix runtime error for FSMs without a reset state

fsm_opt: Fix runtime error for FSMs without a reset state

Signed-off-by: David Shah <dave@ds0.me>

Cope WIDTH of ff/latch cells is default of zero

Remove check for cell->name[0] == '$'

Refactor

write_verilog to cope with init attr on q when -noexpr

Add INIT parameter to all ff/latch cells

Add tests for simple cases using defparam

Add -B option to autotest.sh to append to backend_opts

Extend testcase

ecp5: Use abc -dress

Signed-off-by: David Shah <davey1576@gmail.com>

abc: Improved recovered netnames, also preserve src on nets with dress

Signed-off-by: David Shah <davey1576@gmail.com>

ice40: Use abc -dress in synth_ice40

Signed-off-by: David Shah <davey1576@gmail.com>

abc: Preserve naming through ABC using 'dress' command

Signed-off-by: David Shah <dave@ds0.me>

Add testcase

Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::get_id() behavior)

Signed-off-by: Clifford Wolf <clifford@clifford.at>

write_verilog: correctly emit asynchronous transparent ports.

This commit fixes two related issues:
  * For asynchronous ports, clock is no longer added to domain list.
    (This would lead to absurd constructs like `always @(posedge 0)`.
  * The logic to distinguish synchronous and asynchronous ports is
    changed to correctly use or avoid clock in all cases.

Before this commit, the following RTLIL snippet (after memory_collect)

    cell $memrd $2
      parameter \MEMID "\\mem"
      parameter \ABITS 2
      parameter \WIDTH 4
      parameter \CLK_ENABLE 0
      parameter \CLK_POLARITY 1
      parameter \TRANSPARENT 1
      connect \CLK 1'0
      connect \EN 1'1
      connect \ADDR \mem_r_addr
      connect \DATA \mem_r_data
    end

would lead to invalid Verilog:

    reg [1:0] _0_;
    always @(posedge 1'h0) begin
      _0_ <= mem_r_addr;
    end
    assign mem_r_data = mem[_0_];

Note that there are two potential pitfalls remaining after this
change:
  * For asynchronous ports, the \EN input and \TRANSPARENT parameter
    are silently ignored. (Per discussion in #760 this is the correct
    behavior.)
  * For synchronous transparent ports, the \EN input is ignored. This
    matches the behavior of the $mem simulation cell. Again, see #760.

Merge pull request #798 from mmicko/master

Fixed Anlogic simulation model

Merge pull request #800 from whitequark/write_verilog_tribuf

write_verilog: write $tribuf cell as ternary

Merge branch 'whitequark-write_verilog_keyword'

Remove asicworld tests for (unsupported) switch-level modelling

Signed-off-by: Clifford Wolf <clifford@clifford.at>

write_verilog: write $tribuf cell as ternary.

write_verilog: escape names that match SystemVerilog keywords.

Merge pull request #796 from whitequark/proc_clean_typo

proc_clean: fix critical typo

Fixed Anlogic simulation model

proc_clean: fix critical typo.

Merge pull request #793 from whitequark/proc_clean_fix_fully_def

proc_clean: fix fully def check to consider compare/signal length

proc_clean: fix fully def check to consider compare/signal length.

Fixes #790.

Cleanups in igloo2 example design

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add SF2 IO buffer insertion

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve Igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "synth_sf2 -vlog", fix "synth_sf2 -edif"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "write_edif -gndvccy"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Progress in pmgen

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Progress in pmgen, add pmgen README

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix pmgen "reject" statement

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Progress in pmgen

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Progress in pmgen

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Progress in pmgen

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add mockup .pmg (pattern matcher generator) file

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add optional nullstr argument to log_id()

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix handling of $shiftx in Verilog back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #788 from whitequark/master

Document $tribuf and some gates

Merge pull request #787 from whitequark/flowmap_relax

flowmap: implement depth relaxation

manual: document some gates.

manual: explain $tribuf cell.

Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>

flowmap: clean up terminology.

  * "map": group gates into LUTs;
  * "pack": replace gates with LUTs.

This is important because we have FlowMap and DF-Map, and currently
our messages are ambiguous.

Also clean up some other log messages while we're at it.

flowmap: implement depth relaxation.

Fix typo in manual

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Bugfix in $memrd sharing

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #782 from whitequark/flowmap_dfs

 flowmap: construct a max-volume max-flow min-cut, not just any one

Switch "bugpoint" from system() to run_command()

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #783 from whitequark/bugpoint

bugpoint: new pass

bugpoint: new pass.

A typical use of `bugpoint` would involve a script with a pass under
test, e.g.:

    flowmap -relax -optarea 100

and would be invoked as:

    bugpoint -yosys ./yosys -script flowmap.ys -clean -cells

This replaces the current design with the minimal design that still
crashes the `flowmap.ys` script.

`bugpoint` can also be used to perform generic design minimization
using `select`, e.g. the following script:

    select i:* %x t:$_MUX_ %i -assert-max 0

would remove all parts of the design except for an unbroken path from
an input to an output port that goes through exactly one $_MUX_ cell.
(The condition is inverted.)

flowmap: construct a max-volume max-flow min-cut, not just any one.

Merge pull request #780 from phire/rename_from_wire

Rename cells based on the wires they drive.

Rename cells based on the wires they drive.

Add skeleton Yosys-Libero igloo2 example project

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Bugfix in Verilog string handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>

flowmap: add -minlut option, to allow postprocessing with opt_lut.

Merge pull request #777 from mmicko/achronix_cell_sim_fix

Fix cells_sim.v for Achronix FPGA

Fix cells_sim.v for Achronix FPGA

Remove -m32 Verific eval lib build instructions

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #776 from mmicko/unify_noflatten

Unify usage of noflatten among architectures

Update Verific default path

Signed-off-by: Clifford Wolf <clifford@clifford.at>

flowmap: cleanup for clarity. NFCI.

Unify usage of noflatten among architectures

flowmap: improve debug graph output. NFC.