Eddie Hung [Thu, 26 Sep 2019 00:26:47 +0000 (17:26 -0700)]
Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit
Eddie Hung [Thu, 26 Sep 2019 00:25:44 +0000 (17:25 -0700)]
Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"
This reverts commit
234738b103d4f2b3d937ed928fd89bc4e31627f1.
Eddie Hung [Thu, 26 Sep 2019 00:24:11 +0000 (17:24 -0700)]
Revert "No need for $__mul anymore?"
This reverts commit
1d875ac76a354f654f28b9632d83f6b43542e827.
Eddie Hung [Thu, 26 Sep 2019 00:22:30 +0000 (17:22 -0700)]
Rework xilinx_dsp postAdd for new wreduce call
Eddie Hung [Thu, 26 Sep 2019 00:22:04 +0000 (17:22 -0700)]
Only wreduce on t:$add
Eddie Hung [Wed, 25 Sep 2019 23:51:31 +0000 (16:51 -0700)]
Remove _TECHMAP_CELLTYPE_ check since all $mul
Eddie Hung [Wed, 25 Sep 2019 23:45:51 +0000 (16:45 -0700)]
Fix memory issue since SigSpec& could be invalidated
Eddie Hung [Wed, 25 Sep 2019 21:06:21 +0000 (14:06 -0700)]
No need for $__mul anymore?
Eddie Hung [Wed, 25 Sep 2019 21:05:59 +0000 (14:05 -0700)]
unextend only used in init
Eddie Hung [Wed, 25 Sep 2019 21:04:36 +0000 (14:04 -0700)]
Call 'wreduce' after mul2dsp to avoid unextend()
Eddie Hung [Wed, 25 Sep 2019 17:33:16 +0000 (10:33 -0700)]
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
Eddie Hung [Tue, 24 Sep 2019 05:02:22 +0000 (22:02 -0700)]
Add (* techmap_autopurge *) to abc_unmap.v too
Eddie Hung [Tue, 24 Sep 2019 04:58:40 +0000 (21:58 -0700)]
"abc_padding" attr for blackbox outputs that were padded, remove them later
Eddie Hung [Tue, 24 Sep 2019 04:58:04 +0000 (21:58 -0700)]
Force $inout.out ports to begin with '$' to indicate internal
Eddie Hung [Tue, 24 Sep 2019 04:56:28 +0000 (21:56 -0700)]
Add techmap_autopurge to outputs in abc_map.v too
Eddie Hung [Tue, 24 Sep 2019 02:52:55 +0000 (19:52 -0700)]
Revert "Add a xilinx_finalise pass"
This reverts commit
23d90e0439ffef510632ce45a3d2aff1c129f405.
Eddie Hung [Tue, 24 Sep 2019 02:52:55 +0000 (19:52 -0700)]
Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"
This reverts commit
67c2db3486a7b2ff34f89dc861fb66d51ba6101b.
Eddie Hung [Tue, 24 Sep 2019 02:52:54 +0000 (19:52 -0700)]
Revert "Vivado does not like zero width port connections"
This reverts commit
895e2befa76bd326cc47fd40de112ea067fcaf98.
Eddie Hung [Tue, 24 Sep 2019 02:04:07 +0000 (19:04 -0700)]
Vivado does not like zero width port connections
Eddie Hung [Tue, 24 Sep 2019 01:56:18 +0000 (18:56 -0700)]
Remove (* techmap_autopurge *) from abc_unmap.v since no effect
Eddie Hung [Tue, 24 Sep 2019 01:56:02 +0000 (18:56 -0700)]
Add a xilinx_finalise pass
Eddie Hung [Mon, 23 Sep 2019 23:00:11 +0000 (16:00 -0700)]
Set [AB]CASCREG to legal values
Eddie Hung [Mon, 23 Sep 2019 20:58:10 +0000 (13:58 -0700)]
Comment to explain separating CREG packing
Eddie Hung [Mon, 23 Sep 2019 20:27:10 +0000 (13:27 -0700)]
Separate out CREG packing into new pattern, to avoid conflict with PREG
Eddie Hung [Mon, 23 Sep 2019 20:27:00 +0000 (13:27 -0700)]
Move log_debug("\n") later
Eddie Hung [Mon, 23 Sep 2019 20:26:34 +0000 (13:26 -0700)]
Move unextend initialisation later
Eddie Hung [Mon, 23 Sep 2019 20:00:44 +0000 (13:00 -0700)]
Use new port() overload once more
Eddie Hung [Mon, 23 Sep 2019 17:58:28 +0000 (10:58 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp
Clifford Wolf [Sat, 21 Sep 2019 09:25:36 +0000 (11:25 +0200)]
Merge pull request #1392 from YosysHQ/eddie/fix1391
(* techmap_autopurge *) fixes when ports aren't consistently-sized
Eddie Hung [Sat, 21 Sep 2019 00:58:51 +0000 (17:58 -0700)]
Hell let's add the original #1381 testcase too
Eddie Hung [Sat, 21 Sep 2019 00:52:23 +0000 (17:52 -0700)]
Revert abc9.cc
Eddie Hung [Sat, 21 Sep 2019 00:49:26 +0000 (17:49 -0700)]
Add testcase
Eddie Hung [Sat, 21 Sep 2019 00:48:37 +0000 (17:48 -0700)]
Trim mismatched connection to be same (smallest) size
Eddie Hung [Sat, 21 Sep 2019 00:42:36 +0000 (17:42 -0700)]
Fix first testcase in #1391
Eddie Hung [Fri, 20 Sep 2019 21:24:31 +0000 (14:24 -0700)]
Grammar
Eddie Hung [Fri, 20 Sep 2019 21:21:22 +0000 (14:21 -0700)]
Use new port/param overload in pmg
Eddie Hung [Fri, 20 Sep 2019 19:42:28 +0000 (12:42 -0700)]
Output pattern matcher items as log_debug()
Eddie Hung [Fri, 20 Sep 2019 19:37:29 +0000 (12:37 -0700)]
OPMODE is port not param
Eddie Hung [Fri, 20 Sep 2019 19:21:36 +0000 (12:21 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung [Fri, 20 Sep 2019 19:18:37 +0000 (12:18 -0700)]
Do not run xilinx_dsp_cascadeAB for now
Eddie Hung [Fri, 20 Sep 2019 19:07:14 +0000 (12:07 -0700)]
WIP for xiinx_dsp_cascadeAB
Eddie Hung [Fri, 20 Sep 2019 19:04:16 +0000 (12:04 -0700)]
Run until convergence
Eddie Hung [Fri, 20 Sep 2019 19:03:45 +0000 (12:03 -0700)]
Cleanup ice40_dsp.pmg
Eddie Hung [Fri, 20 Sep 2019 19:03:25 +0000 (12:03 -0700)]
Cleanup xilinx_dsp
Eddie Hung [Fri, 20 Sep 2019 19:03:10 +0000 (12:03 -0700)]
More exceptions
Eddie Hung [Fri, 20 Sep 2019 17:11:36 +0000 (10:11 -0700)]
Fix signedness bug
Eddie Hung [Fri, 20 Sep 2019 17:07:54 +0000 (10:07 -0700)]
Update doc
Eddie Hung [Fri, 20 Sep 2019 17:00:09 +0000 (10:00 -0700)]
Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
Eddie Hung [Fri, 20 Sep 2019 16:59:42 +0000 (09:59 -0700)]
Add an overload for port/param with default value
Eddie Hung [Fri, 20 Sep 2019 16:02:29 +0000 (09:02 -0700)]
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
Eddie Hung [Fri, 20 Sep 2019 15:56:16 +0000 (08:56 -0700)]
Revert "Move mul2dsp before wreduce"
This reverts commit
e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab.
Eddie Hung [Fri, 20 Sep 2019 15:41:40 +0000 (08:41 -0700)]
Move mul2dsp before wreduce
Eddie Hung [Fri, 20 Sep 2019 15:41:28 +0000 (08:41 -0700)]
Small cleanup
Clifford Wolf [Fri, 20 Sep 2019 11:30:28 +0000 (13:30 +0200)]
Merge pull request #1386 from YosysHQ/clifford/fix1360
Fix handling of read_verilog config in AstModule::reprocess_module()
Clifford Wolf [Fri, 20 Sep 2019 10:16:20 +0000 (12:16 +0200)]
Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 20 Sep 2019 08:28:20 +0000 (10:28 +0200)]
Update CHANGELOG
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 20 Sep 2019 08:27:17 +0000 (10:27 +0200)]
Add "add -mod"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 20 Sep 2019 07:58:42 +0000 (09:58 +0200)]
Merge pull request #1384 from YosysHQ/clifford/fix1381
Add techmap_autopurge attribute
Eddie Hung [Fri, 20 Sep 2019 05:48:57 +0000 (22:48 -0700)]
Disable support for SB_MAC16 reset since it is async
Eddie Hung [Fri, 20 Sep 2019 05:39:47 +0000 (22:39 -0700)]
SB_MAC16 ffCD to not pack same as ffO
Eddie Hung [Fri, 20 Sep 2019 05:39:15 +0000 (22:39 -0700)]
Add more complicated macc testcase
Eddie Hung [Fri, 20 Sep 2019 04:58:34 +0000 (21:58 -0700)]
Clarify
Eddie Hung [Fri, 20 Sep 2019 04:57:11 +0000 (21:57 -0700)]
Update doc for ice40_dsp
Eddie Hung [Fri, 20 Sep 2019 03:04:52 +0000 (20:04 -0700)]
Tidy up, fix undriven
Eddie Hung [Fri, 20 Sep 2019 03:04:44 +0000 (20:04 -0700)]
Add an index
Eddie Hung [Fri, 20 Sep 2019 02:37:45 +0000 (19:37 -0700)]
$__ABC_REG to have WIDTH parameter
Eddie Hung [Fri, 20 Sep 2019 01:59:28 +0000 (18:59 -0700)]
Fix DSP48E1 timing by breaking P path if MREG or PREG
Eddie Hung [Fri, 20 Sep 2019 01:33:38 +0000 (18:33 -0700)]
Revert "Different approach to timing"
This reverts commit
41256f48a5f3231e231cbdf9380a26128f272044.
Eddie Hung [Fri, 20 Sep 2019 01:33:29 +0000 (18:33 -0700)]
Different approach to timing
Eddie Hung [Fri, 20 Sep 2019 01:08:46 +0000 (18:08 -0700)]
Fix width of D
Eddie Hung [Fri, 20 Sep 2019 01:08:16 +0000 (18:08 -0700)]
Add mac.sh and macc_tb.v for testing
Eddie Hung [Thu, 19 Sep 2019 23:27:14 +0000 (16:27 -0700)]
Suppress $anyseq warnings
Eddie Hung [Thu, 19 Sep 2019 23:13:22 +0000 (16:13 -0700)]
Use ID() macro
Eddie Hung [Thu, 19 Sep 2019 22:58:01 +0000 (15:58 -0700)]
Use (* techmap_autopurge *) to suppress techmap warnings
Eddie Hung [Thu, 19 Sep 2019 22:55:49 +0000 (15:55 -0700)]
D is 25 bits not 24 bits wide
Eddie Hung [Thu, 19 Sep 2019 22:47:41 +0000 (15:47 -0700)]
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
Eddie Hung [Thu, 19 Sep 2019 22:40:28 +0000 (15:40 -0700)]
When two boxes connect to each other, need not be a (* keep *)
Eddie Hung [Thu, 19 Sep 2019 22:40:17 +0000 (15:40 -0700)]
Re-enable sign extension for C input
Eddie Hung [Thu, 19 Sep 2019 21:58:06 +0000 (14:58 -0700)]
synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2
Eddie Hung [Thu, 19 Sep 2019 21:57:38 +0000 (14:57 -0700)]
Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2
Eddie Hung [Thu, 19 Sep 2019 21:50:11 +0000 (14:50 -0700)]
Do not perform width-checks for DSP48E1 which is much more complicated
Eddie Hung [Thu, 19 Sep 2019 21:49:47 +0000 (14:49 -0700)]
Remove TODO as check should not be necessary
Eddie Hung [Thu, 19 Sep 2019 21:46:53 +0000 (14:46 -0700)]
Revert index to select
Eddie Hung [Thu, 19 Sep 2019 21:34:06 +0000 (14:34 -0700)]
Cleanup xilinx_dsp too
Eddie Hung [Thu, 19 Sep 2019 21:27:25 +0000 (14:27 -0700)]
Refactor ce{mux,pol} -> hold{mux,pol}
Eddie Hung [Thu, 19 Sep 2019 21:02:55 +0000 (14:02 -0700)]
Add HOLD/RST support for SB_MAC16
Eddie Hung [Thu, 19 Sep 2019 19:14:33 +0000 (12:14 -0700)]
Add support for SB_MAC16 CD and H registers
Eddie Hung [Thu, 19 Sep 2019 19:00:48 +0000 (12:00 -0700)]
Refactor ice40_dsp.pmg
Eddie Hung [Thu, 19 Sep 2019 19:00:39 +0000 (12:00 -0700)]
Add more entries
Eddie Hung [Thu, 19 Sep 2019 18:02:14 +0000 (11:02 -0700)]
Format macc.v
Clifford Wolf [Thu, 19 Sep 2019 17:26:09 +0000 (19:26 +0200)]
Add techmap_autopurge attribute, fixes #1381
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Thu, 19 Sep 2019 17:39:00 +0000 (10:39 -0700)]
Cleanup
Marcin Kościelnicki [Wed, 28 Aug 2019 15:28:01 +0000 (15:28 +0000)]
Use extractinv for synth_xilinx -ise
Marcin Kościelnicki [Wed, 28 Aug 2019 14:58:14 +0000 (14:58 +0000)]
Added extractinv pass
Eddie Hung [Wed, 18 Sep 2019 19:44:34 +0000 (12:44 -0700)]
Remove stat
Eddie Hung [Fri, 6 Sep 2019 20:28:15 +0000 (13:28 -0700)]
Document (* gentb_skip *) attr for test_autotb
Eddie Hung [Wed, 18 Sep 2019 19:40:21 +0000 (12:40 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung [Wed, 18 Sep 2019 19:40:08 +0000 (12:40 -0700)]
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
Eddie Hung [Wed, 18 Sep 2019 19:35:24 +0000 (12:35 -0700)]
Add doc on pattern detector for overflow
Eddie Hung [Wed, 18 Sep 2019 19:23:22 +0000 (12:23 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp