Dmitry Selyutin [Sat, 3 Jun 2023 16:58:02 +0000 (19:58 +0300)]
insndb/db: support pcode command
Dmitry Selyutin [Sat, 3 Jun 2023 15:43:29 +0000 (18:43 +0300)]
insndb/dis: rename into disasm for no good reason
Dmitry Selyutin [Sat, 3 Jun 2023 15:15:42 +0000 (18:15 +0300)]
insndb/db: support log option
Luke Kenneth Casson Leighton [Sat, 3 Jun 2023 15:14:15 +0000 (16:14 +0100)]
correct RS/RA/CR0 for rlwinm which is 2P-1S1D
Dmitry Selyutin [Sat, 3 Jun 2023 15:02:07 +0000 (18:02 +0300)]
insndb/db: support operands command
Dmitry Selyutin [Sat, 3 Jun 2023 10:41:42 +0000 (13:41 +0300)]
insndb/db: refactor classes hierarchy
Dmitry Selyutin [Sat, 3 Jun 2023 10:25:56 +0000 (13:25 +0300)]
insndb/db: deindent classes
Dmitry Selyutin [Sat, 3 Jun 2023 14:58:41 +0000 (17:58 +0300)]
insndb: rename types into core
Dmitry Selyutin [Sat, 3 Jun 2023 14:56:54 +0000 (17:56 +0300)]
insndb: revert recent renaming
Luke Kenneth Casson Leighton [Sat, 3 Jun 2023 14:10:35 +0000 (15:10 +0100)]
openpower.insndb.dis renamed to disasm in setup.py
Luke Kenneth Casson Leighton [Sat, 3 Jun 2023 11:47:30 +0000 (12:47 +0100)]
using names of modules that are identical to commonly-used python modules
(even at the leaf-node) is causing import problems
Luke Kenneth Casson Leighton [Sat, 3 Jun 2023 11:45:35 +0000 (12:45 +0100)]
import dis overloads naming of modules already in python3,
and stops functions from importing
Luke Kenneth Casson Leighton [Sat, 3 Jun 2023 11:32:30 +0000 (12:32 +0100)]
continuing the conversion of LDST_IDX to EXTRA332 type
https://bugs.libre-soc.org/show_bug.cgi?id=1083
Dmitry Selyutin [Sat, 3 Jun 2023 09:59:09 +0000 (12:59 +0300)]
insndb/db: support opcodes command
Dmitry Selyutin [Sat, 3 Jun 2023 09:48:39 +0000 (12:48 +0300)]
insndb/db: drop redundant method
Dmitry Selyutin [Sat, 3 Jun 2023 09:23:20 +0000 (12:23 +0300)]
insndb: provide pysvp64db script
Dmitry Selyutin [Fri, 2 Jun 2023 16:25:18 +0000 (19:25 +0300)]
pysvp64dis: integrate into insndb
Dmitry Selyutin [Fri, 2 Jun 2023 16:23:02 +0000 (19:23 +0300)]
pysvp64asm: integrate into insndb
Dmitry Selyutin [Fri, 2 Jun 2023 16:20:09 +0000 (19:20 +0300)]
power_insn: decouple into separate module
Dmitry Selyutin [Wed, 31 May 2023 21:05:08 +0000 (00:05 +0300)]
power_insn: disassemble RA0 and RT0 correctly
Dmitry Selyutin [Wed, 31 May 2023 21:04:13 +0000 (00:04 +0300)]
power_insn: forbid r0 for RA0 and RT0
Dmitry Selyutin [Wed, 31 May 2023 21:00:51 +0000 (00:00 +0300)]
power_enums: introduce Reg pair property
Dmitry Selyutin [Wed, 31 May 2023 21:00:37 +0000 (00:00 +0300)]
power_enums: introduce Reg or_zero property
Dmitry Selyutin [Wed, 31 May 2023 19:47:40 +0000 (22:47 +0300)]
power_insn: drop unused import
Dmitry Selyutin [Wed, 31 May 2023 19:47:05 +0000 (22:47 +0300)]
power_enums: deprecate SVExtraReg
Dmitry Selyutin [Wed, 31 May 2023 19:46:47 +0000 (22:46 +0300)]
power_insn: switch to Reg
Dmitry Selyutin [Wed, 31 May 2023 19:46:21 +0000 (22:46 +0300)]
power_enums: introduce Reg as alias of SVExtraReg
Dmitry Selyutin [Wed, 31 May 2023 19:41:27 +0000 (22:41 +0300)]
power_insn: guess extra from reg instead of sel
Dmitry Selyutin [Wed, 31 May 2023 19:25:32 +0000 (22:25 +0300)]
power_enums: provide selector type property
Dmitry Selyutin [Wed, 31 May 2023 19:06:54 +0000 (22:06 +0300)]
power_enums: deprecate SVExtraRegType
Dmitry Selyutin [Wed, 31 May 2023 19:06:14 +0000 (22:06 +0300)]
power_insn: switch to SelType
Dmitry Selyutin [Wed, 31 May 2023 18:48:42 +0000 (21:48 +0300)]
power_enums: introduce SelType as alias of SVExtraRegType
Dmitry Selyutin [Wed, 31 May 2023 18:37:47 +0000 (21:37 +0300)]
power_insn: completely refactor extras
Dmitry Selyutin [Wed, 31 May 2023 20:40:39 +0000 (23:40 +0300)]
power_enums: introduce register aliases
Dmitry Selyutin [Tue, 30 May 2023 19:45:48 +0000 (22:45 +0300)]
power_insn: introduce extras property
Dmitry Selyutin [Tue, 30 May 2023 16:31:11 +0000 (19:31 +0300)]
power_enums: change SVExtra representation
Luke Kenneth Casson Leighton [Thu, 1 Jun 2023 16:02:56 +0000 (17:02 +0100)]
far too much memory (58 GB) being used by these unit tests,
they have to be done as far smaller batches
Luke Kenneth Casson Leighton [Thu, 1 Jun 2023 15:54:02 +0000 (16:54 +0100)]
disable fmv-fcvt tests entirely
Luke Kenneth Casson Leighton [Thu, 1 Jun 2023 14:18:56 +0000 (15:18 +0100)]
disable fmv / fcvt unit tests as there are such a vast number
it causes machines with 64 GB of RAM to run out of memory
tests *have* to be kept short
Jacob Lifshay [Thu, 1 Jun 2023 06:54:48 +0000 (23:54 -0700)]
add expected values to source
Jacob Lifshay [Thu, 1 Jun 2023 06:46:23 +0000 (23:46 -0700)]
add worked-out svp64 16-bit maddsubrs test case
Jacob Lifshay [Thu, 1 Jun 2023 06:30:48 +0000 (23:30 -0700)]
make maddsubrs show up in SVP64 generated CSVs
Jacob Lifshay [Thu, 1 Jun 2023 06:29:59 +0000 (23:29 -0700)]
raise error on unhandled instruction kind
Jacob Lifshay [Thu, 1 Jun 2023 04:39:58 +0000 (21:39 -0700)]
log no longer raises internal exceptions and has more caching, so is likely faster
Jacob Lifshay [Thu, 1 Jun 2023 04:12:30 +0000 (21:12 -0700)]
format code
Jacob Lifshay [Thu, 1 Jun 2023 02:57:55 +0000 (19:57 -0700)]
increase ci maxfail to 10
Dmitry Selyutin [Wed, 31 May 2023 18:20:28 +0000 (21:20 +0300)]
test_pysvp64dis.py: add tests for broken extras
Jacob Lifshay [Wed, 31 May 2023 06:08:05 +0000 (23:08 -0700)]
fcvtfg works!
Jacob Lifshay [Wed, 31 May 2023 06:07:08 +0000 (23:07 -0700)]
add rest of bfp* functions needed for fcvtfg
Jacob Lifshay [Wed, 31 May 2023 05:08:02 +0000 (22:08 -0700)]
use raise_syntax_error for `IndentationError`s as well
Jacob Lifshay [Tue, 30 May 2023 08:00:01 +0000 (01:00 -0700)]
add support for checking sprs and msr in unit tests
Jacob Lifshay [Tue, 30 May 2023 07:50:42 +0000 (00:50 -0700)]
use a different default MSR value for unit tests since 0 isn't a very useful default
Andrey Miroshnikov [Mon, 29 May 2023 09:51:14 +0000 (09:51 +0000)]
inorder.py: Typo fixes.
Andrey Miroshnikov [Sun, 28 May 2023 20:40:58 +0000 (20:40 +0000)]
inorder.py: Added draft get_input/output_regs functions.
Passing trace (insn and Hazards()) to the fetch phase.
Decoder not yet using Hazard info.
Dmitry Selyutin [Sun, 14 May 2023 12:25:37 +0000 (12:25 +0000)]
power_insn: fix broken extra_idx
Dmitry Selyutin [Sun, 14 May 2023 12:09:22 +0000 (12:09 +0000)]
power_enums: fix incorrect naming
Luke Kenneth Casson Leighton [Sat, 27 May 2023 11:56:31 +0000 (12:56 +0100)]
add P2M type - 1P 2P 2PM needed for new LD/ST-Indexed format
Luke Kenneth Casson Leighton [Sat, 27 May 2023 11:35:37 +0000 (12:35 +0100)]
https://bugs.libre-soc.org/show_bug.cgi?id=1091
* rename shadd to sadd
* rename sm to SH
* update CSV files with instruction definition
* move shadd unit tests to separate class
Luke Kenneth Casson Leighton [Sat, 27 May 2023 11:33:36 +0000 (12:33 +0100)]
add .py? gitignore
Luke Kenneth Casson Leighton [Sat, 27 May 2023 10:54:57 +0000 (11:54 +0100)]
rename sm to SH for shift-and-add instructions
https://bugs.libre-soc.org/show_bug.cgi?id=1091
in fields.text machine-readable spec
Luke Kenneth Casson Leighton [Wed, 24 May 2023 12:01:51 +0000 (13:01 +0100)]
note on FP Exception about DDFF VLi=0/1
Jacob Lifshay [Wed, 24 May 2023 03:10:58 +0000 (20:10 -0700)]
test fcvttgo. with traps enabled
Jacob Lifshay [Wed, 24 May 2023 03:10:18 +0000 (20:10 -0700)]
ISACaller: generate FP trap
Jacob Lifshay [Wed, 24 May 2023 02:34:15 +0000 (19:34 -0700)]
test fcvttgo. with VE=1 too
Jacob Lifshay [Wed, 24 May 2023 02:33:01 +0000 (19:33 -0700)]
fcvttg[s][o][.] needs EXTRA_UNINIT_REGS: RT
Jacob Lifshay [Wed, 24 May 2023 02:24:34 +0000 (19:24 -0700)]
add support for adding extra uninit_regs from html comment
I chose an html comment since it's not part of the proposed pseudocode
like so:
* blah RT,RA
Pseudo-code:
<!-- EXTRA_UNINIT_REGS: RT -->
if rand() then
RT <- 42 + (RA)
Luke Kenneth Casson Leighton [Mon, 22 May 2023 11:39:08 +0000 (12:39 +0100)]
add getopt for test and help to inorder.py
Luke Kenneth Casson Leighton [Mon, 22 May 2023 11:27:47 +0000 (12:27 +0100)]
comment read_file explaining usage contract
convert read_file to yield
explain unit tests
Luke Kenneth Casson Leighton [Mon, 22 May 2023 11:11:11 +0000 (12:11 +0100)]
yet another namespace hack now that @inject is on
ISACallerFnHelper_double2single
Luke Kenneth Casson Leighton [Mon, 22 May 2023 11:09:31 +0000 (12:09 +0100)]
make style of consts.py consistent with standard python
practices (and those of this project) - remove underscores in front of
imports. the classes named _Const* however are *NOT* so altered because
Luke Kenneth Casson Leighton [Mon, 22 May 2023 11:07:46 +0000 (12:07 +0100)]
make style of pysvp64dis.py consistent with standard python
practices (and those of this project) - remove underscores in front of
imports
Luke Kenneth Casson Leighton [Mon, 22 May 2023 11:04:39 +0000 (12:04 +0100)]
make style of power_fields.py consistent with standard python
practices (and those of this project) - remove underscores in front of
imports
Luke Kenneth Casson Leighton [Sun, 21 May 2023 20:35:20 +0000 (21:35 +0100)]
eurrrgh, hack in a namespace dict now that @inject() is
done on ISACallerFnHelper_{pyfnwriterpage}
Luke Kenneth Casson Leighton [Sun, 21 May 2023 20:06:39 +0000 (21:06 +0100)]
add /pi to LD/ST, temporarily. lose dz/sz replace with zz to compensate
this is related to bug #1047 and #1083
Luke Kenneth Casson Leighton [Sun, 21 May 2023 14:23:19 +0000 (15:23 +0100)]
big set of updates to LD/ST in line with new spec changes
https://bugs.libre-soc.org/show_bug.cgi?id=1083
LD/ST-imm and LD/ST-idx are now pretty similar
Luke Kenneth Casson Leighton [Sun, 21 May 2023 14:02:44 +0000 (15:02 +0100)]
hack-add @inject() into pyfnwriter, also take the
opportunity to stop doing "import ISACallerFnHelper as something"
by doing a hack-substitute on the class name
Luke Kenneth Casson Leighton [Sun, 21 May 2023 11:17:39 +0000 (12:17 +0100)]
explicitly update FPSCR from list of return results
Luke Kenneth Casson Leighton [Sun, 21 May 2023 11:17:20 +0000 (12:17 +0100)]
whitespace - bug in autopep8 which is dreadful
Luke Kenneth Casson Leighton [Sun, 21 May 2023 11:01:55 +0000 (12:01 +0100)]
code-comment spelling
Luke Kenneth Casson Leighton [Sun, 21 May 2023 11:01:45 +0000 (12:01 +0100)]
FPSCR should never have been added to "bypass" the incoming
local parameter or its return result
Jacob Lifshay [Sat, 20 May 2023 02:53:36 +0000 (19:53 -0700)]
must test fcvtfgs not fcvtfg for f32 test case
Jacob Lifshay [Sat, 20 May 2023 02:52:43 +0000 (19:52 -0700)]
format code
Jacob Lifshay [Sat, 20 May 2023 02:51:39 +0000 (19:51 -0700)]
add more bfp_* functions
Jacob Lifshay [Sat, 20 May 2023 02:50:38 +0000 (19:50 -0700)]
fix bfp compare
Jacob Lifshay [Sat, 20 May 2023 02:50:17 +0000 (19:50 -0700)]
fix typo
Jacob Lifshay [Sat, 20 May 2023 02:49:12 +0000 (19:49 -0700)]
fix using python int instead of SelectableInt
Jacob Lifshay [Fri, 19 May 2023 06:51:21 +0000 (23:51 -0700)]
fix fptrans unit tests' CR1 expected values since we calculate them from FPSCR now
Jacob Lifshay [Fri, 19 May 2023 06:40:45 +0000 (23:40 -0700)]
add WIP fcvtfg unit tests
Jacob Lifshay [Fri, 19 May 2023 06:39:29 +0000 (23:39 -0700)]
add WIP bfp_* function
Jacob Lifshay [Fri, 19 May 2023 06:36:15 +0000 (23:36 -0700)]
fix: bfp_ROUND_TO_BFP64 takes 3 arguments
Jacob Lifshay [Fri, 19 May 2023 06:35:50 +0000 (23:35 -0700)]
add more bfp_* functions
Jacob Lifshay [Fri, 19 May 2023 06:32:58 +0000 (23:32 -0700)]
fix bfp_COMPARE_* when given denormal inputs
Jacob Lifshay [Fri, 19 May 2023 06:28:06 +0000 (23:28 -0700)]
compute CR1 for non-compare fp Rc=1 instructions
Jacob Lifshay [Fri, 19 May 2023 06:26:51 +0000 (23:26 -0700)]
support binary literals with embedded _ (e.g. 0b10_01)
Jacob Lifshay [Fri, 19 May 2023 03:53:23 +0000 (20:53 -0700)]
fix fcvttg FPSCR.FR computation
the unit test previously assumed the rounding mode is truncate,
but when I switched it to allow dynamic rounding modes,
I forgot to no longer hard-code FPSCR.FR = 0
Jacob Lifshay [Fri, 19 May 2023 01:46:57 +0000 (18:46 -0700)]
only retrieve stack frames we need -- ~2x speed up of test_caller_fmv_fcvt
Jacob Lifshay [Fri, 19 May 2023 01:01:08 +0000 (18:01 -0700)]
parallelize fmv/fcvt unit tests
Jacob Lifshay [Thu, 18 May 2023 04:26:23 +0000 (21:26 -0700)]
test fcvttgo. instead of fcvttg
Jacob Lifshay [Thu, 18 May 2023 04:25:16 +0000 (21:25 -0700)]
fix CR0 output for fmvtg*/fcvttg*
Jacob Lifshay [Thu, 18 May 2023 04:24:35 +0000 (21:24 -0700)]
add fmv*/fcvt* to sv_analysis.py