util,arch-arm: Added python script to generate ARM FS binaries

This python script builds the bootloaders, kernels and DTBs for the
VExpress_GEM5_V1 (aarch32/aarch64), VExpress_EMM and VExpress_EMM64
platforms (it checkouts some linux kernel repositories when needed).

This is the result of this e-mail thread in gem5-dev mailing list:
http://www.mail-archive.com/gem5-dev@gem5.org/msg22406.html

Change-Id: Ida8f9b974f7188f48be8f84f14828a1973d6d256
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/3945
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu, sim: Add param to force CPUs to wait for GDB

By setting the BaseCPU parameter wait_for_dbg_connection, the GDB
server blocks during initialisation waiting for the remote debugger to
connect before starting the simulated CPU.

Change-Id: I4d62c68ce9adf69344bccbb44f66e30b33715a1c
[ Update info message to include remote GDB port, rename param. ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3963
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch-riscv,tests: Add insttests for RV64C

This patch adds instruction tests for the RV64C extension
implementation.  It also updates existing executables for the latest
riscv-tools now that they are compatible.

[Update for changes to parents.]

Change-Id: Id4cfd966a8cae39b0d728b02849622fd00ee7e0e
Reviewed-on: https://gem5-review.googlesource.com/3862
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch-riscv: Add support for compressed extension RV64C

This patch adds compatibility with the 64-bit compressed extension to
the RISC-V ISA, RV64C.  Current versions of the toolchain may use
compressed instructions in glibc by default, which can only be
overridden by recompiling the entire toolchain (simply adding
"-march=rv64g" or "-march=rv64imafd" when compiling a binary is not
sufficient to use uncompressed instructions in glibc functions in the
binary).

[Update diassembly generation for new RegId type.]
[Rebase onto master.]

Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4
Reviewed-on: https://gem5-review.googlesource.com/3860
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

arch-riscv: Restructure ISA description

This patch restructures the RISC-V ISA description to use fewer classes
and improve its ability to be extended with nonstandard extensions in
the future. It also cleans up the disassembly for some of the CSR and
system instructions by removing source and destination registers for
instructions that don't have any.

[Fix class UImmOp to have an "imm" member rather than "uimm".]
[Update disassembly generation for new RegId class.]

Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9
Reviewed-on: https://gem5-review.googlesource.com/3800
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

dev-arm: Add ID registers to the GIC model

Implement GICD_IIDR, GICC_IIDR, GICD_PIDR0, GICD_PIDR1, GICD_PIDR2,
and GICD_PIDR3.

Change-Id: I4f6b5a6303907226e7d8e2f677543b3868c02e7b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3961

arch-arm: Support PMU evens in the 0x4000-0x4040 range

ARMv8.1 added a second architected event range, 0x4000-0x4040. Events
in this range are discovered using the high word of PMCEID{0,1}_EL0

Change-Id: I4cd01264230e5da4c841268a7cf3e6bd307c7180
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3960

dev-arm: Don't unconditionally overwrite bootloader params

The bootloader arguments were previously defaulting to a predetermined
value even if initialized elsewhere in the platform config script.
This commit fixes this issue by not calling the default initialization
routine if the bootloader is already defined.

Change-Id: Id80af4762b52dc036da29430b2795bb30970a349
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3967

dev: Fix OnIdle test in DmaReadFifo

OnIdle() is never called since DMA active check is completely
opposite to what it should be. old active status should be 'true'
and new active status should be false for OnIdle to be called

Change-Id: I94eca50edbe96113190837c7f6e50a0d061158a6
Reported-by: Rohit Kurup <rohit.kurup@arm.com>
Signed-off-by: Rohit Kurup <rohit.kurup@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3966
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>

dev: Fix address type promotion issues in VirtIO devices

With the change we explicitly update the types for the VirtIO bit
masks to be Addr (uint64_t). By changing this, we ensure type
promotion where it is needed. Therefore, this fixes issues where, in
certain situations, address calculations were performed in 32-bits,
resulting in overflows.

Change-Id: I5c5c3f9a3f94e806812282da01268e18ae0d2d39
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3968

sim: Fix clashing stat names in TickedObject and Ticked

Change tickCycles numCycles stat name to totalTickCycles os as not to
clash with the name of the tickCycles stat of the same class.
Declared the params passed to the TickedObject constructer as const.
Call ClockedObject::regStats() from the TickedObject::regStats to
ensure the correct initialization of the base class (ClockedObject)
stats

Change-Id: I6cf5bbe10fa27f2ad0e31d9f70ec3be47fe41455
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3964
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

kvm, arm: don't create interrupt events while saving GIC state

If an interrupt was pending according to Kvm state during a drain,
the Pl390 model would create an interrupt event that could not be
serviced, preventing the system from draining.  The proper behavior
is for the Pl390 not actively being used for simulation to just skip
the GIC state machine that delivers interrupts.

Change-Id: Icb37e7e992f1fb441a9b3a26daa1bb5a6fe19228
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3661
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

kvm, arm: Don't forward IRQ/FIQ when using the kernel's GIC

The BaseArmKvmCPU is responsible for forwarding the IRQ and FIQ
signals from gem5's simulated GIC to KVM. However, these signals
shouldn't be used when the in-kernel GIC emulator is used.

Instead of delivering the interrupts to the guest, we should just
ignore them since any such pending interrupts are likely to be an
artifact of CPU switching or incorrect draining.

Change-Id: I083b72639384272157f92f44a6606bdf0be7413c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3660

arch: ISA parser additions of vector registers

Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.

Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.

Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Added interface for vector reg file

This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.

This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.

This requires implementing the vector register file for the different
models using the VecRegContainer class.

This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.

The changes also affect how the remote_gdb connection works.

There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.

Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.

Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705

arch: added generic vector register

This commit adds a new generic vector register to have a cleaner
implementation of SIMD ISAs.

Nathanael's idea, Rekai's implementation.

Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2704
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Result refactoring

The Result union used to collect the result of an instruction is now a
class of its own, with its constructor, and explicit casting methods for
cleanliness.

This is also a stepping stone to have vector registers, and instructions
that produce a vector register as output.

Change-Id: I6f40c11cb5e835d8b11f7804a4e967aff18025b9
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2703
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Simplify the rename interface and use RegId

With the hierarchical RegId there are a lot of functions that are
redundant now.

The idea behind the simplification is that instead of having the regId,
telling which kind of register read/write/rename/lookup/etc. and then
the function panic_if'ing if the regId is not of the appropriate type,
we provide an interface that decides what kind of register to read
depending on the register type of the given regId.

Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2702

cpu: Physical register structural + flat indexing

Mimic the changes done on the architectural register indexes on the
physical register indexes. This is specific to the O3 model. The
structure, called PhysRegId, contains a register class, a register
index and a flat register index. The flat register index is kept
because it is useful in some cases where the type of register is not
important (dependency graph and scoreboard for example). Instead
of directly using the structure, most of the code is working with
a const PhysRegId* (typedef to PhysRegIdPtr). The actual PhysRegId
objects are stored in the regFile.

Change-Id: Ic879a3cc608aa2f34e2168280faac1846de77667
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2701
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

arm,kvm: update CP15 timer model when exiting Kvm

The ARM MiscRegs implementation has two interfaces: 'normal'
and 'no effect'.  The latter acts as a way to access the
backing store without architectural 'effects'.  For instance,
a normal write to a timer compare value would call into the
timer model to emulate the device.  The 'no effect' interface,
however, would just write the value into the register backing
store and do nothing else.

For Kvm execution, a delicate balance must be struck for the
timer device specifically.  We need the code in the model
to be run, because it contains state other than the register
backing store that must stay in sync.  On the other hand, we
don't necessarily want the timer model to schedule gem5
events when this happens.

In this commit, we ensure that we use the 'effectful'
MiscReg interface when copying the CP15 timer registers
from Kvm back into gem5.  The prior commit makes sure
that this doesn't generate unnecessary timer events
or interrupts.

Change-Id: Id414c2965bd07fc21ac95e3d581ccc9f55cef9f9
Reviewed-on: https://gem5-review.googlesource.com/3543
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev,arm: add Kvm mode of operation for CP15 timer

The timer device exposed via the ARM ISA, also known as the
"CP15 timer" due to its legacy coprocessor encodings, is
implemented by the GenericTimerISA class.  During Kvm
execution, however, this functionality is directly emulated
by the hardware.

This commit subclasses the GenericTimer, which is (solely)
used by GenericTimerISA, to facilitate Kvm in much the same
way as the prior GIC changes: the gem5 model is used as the
backing store for state, so checkpointing and CPU switching
work correctly, but isn't used during Kvm execution.

The added indirection prevents the timer device from creating
events when we're just updating its state, but not actually
using it for simulation.

Change-Id: I427540d11ccf049c334afe318f575146aa888672
Reviewed-on: https://gem5-review.googlesource.com/3542
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev,arm: remove and recreate timer events around drains

Having timer events stored in checkpoints complicates Kvm
execution.  We change the timer behavior so that it always
deschedules any pending events on a drain() and recreates
them on a drainResume(), thus they will never appear in
checkpoints henceforth.  This pattern of behavior makes
it simpler to handle Kvm execution, where the hardware
performs the timer function directly.

Change-Id: Ia218868c69350d96e923c640634d492b5c19cd3f
Reviewed-on: https://gem5-review.googlesource.com/3541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

kvm: move Kvm check from ARM Kvm GIC to System

The check was nearly completely generic anyway,
with the exception of the Kvm CPU type.

This will make it easier for other parts of the
codebase to do similar checks.

Change-Id: Ibfdd3d65e9e6cc3041b53b73adfabee1999283da
Reviewed-on: https://gem5-review.googlesource.com/3540
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config, arm: Don't import timing models for missing CPUs

When importing the cores.arm package, we currently throw an exception
if a timing model can't be imported due to a missing dependency (e.g.,
the required CPU model wasn't included in the build). This is
undesirable since it prevents other, working, timing models from being
added to the package. Wrap the import_module call in a try-except
block and skip timing models that have missing dependencies.

Change-Id: I92bab62c989f433a8a4a7bf59207d9d81b3d19e1
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3946
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Clean up core timing model discovery

Instead of hard-coding timing models in CpuConfig.py, use
introspection to find them in the cores.arm model package.

Change-Id: I6642dc9cbc3f5beeeec748e716c9426c233d51ea
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3944
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Move core timing models to config/common/cores

Change-Id: I189b6462cc64f7cc6c1b7a6c2af1abb60e1854de
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3943
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Make ex5_*.py independent of old configs

The ex5_LITTLE and ex5_big configs currently depend on Caches.py and
O3_ARM_v7a.py. These aren't actual dependencies since all of the
params from the caches and the old O3 model are overridden. This
changeset updates the ex5 models to derive from the base SimObjects
instead.

Change-Id: I999e73bb9cc21ad96865c1bc0dd5973faa48ab61
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3942
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Add missing import of 'fatal' in CpuConfig

Change-Id: I7762d344cb964c3e010135ff928c6ea12538912c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3941
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Make some MemConfig options optional

MemConfig currently assumes that all callers include the its full set
of options in the command line parser. This is unnecessary and
sometimes confusing. Make most of the options optional to avoid having
to add all of them to example scripts.

Change-Id: I2d73be2454427b00db16716edcfd96a47133c888
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3940
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm: Fix memleak in Pl390 by adding destructor

Change-Id: I3395e64311f6aa7bbfb6eee9bfec82e832bcbd4d
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3901
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Fix memleak in VGic by adding destructor

Change-Id: I864b5d9ed655cc52e440e2eb54987e8ff9a73296
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3900
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Add missing overrides to BaseCache

Change-Id: I6a3a57e3067c247bd6ce6f01ac9459883f4aae2c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3880
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arm,sim: fix context switch stats dumps for ARM64/Linux

32bit and 64bit Linux have different arguments passed to the
__switch_to() function that gem5 hooks into in order to collect context
switch statistics. 64bit Linux provides the task_struct pointer to the
next task that will be switched to, which means we don't have to look
up the task_struct from thread_info as we do in 32bit ARM Linux.

This patch adds a second set of accessors to ThreadInfo to extract
details such as the pid, tgid, task name, etc., directly from a
task_struct. The existing accessors maintain their existing behavior by
first looking up the task_struct and then calling these new accessors.

A 64-bit variant of the DumpStatsPCEvent class is added that uses these
new accessors to get the task details for the context switch dumps
directly from the task_struct passed to __switch_to().

Change-Id: I63c4b3e1ad64446751a91f6340901d5180d7382d
Reviewed-on: https://gem5-review.googlesource.com/2640
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim: Updated ClockedObject power state warning

To prevent this warning from printing for *every* simulation, this patch
adds a check to only print the warning if we are not at the beginning of
simulation.

Change-Id: I7f6154f0ca26bef6280f909f799aa1c7936b624a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/3840
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim, x86: Replace EventWrapper use with EventFunctionWrapper

Change-Id: Ie1df07b70776208fc3631a73d403024636fc05a9
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3749
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

dev: Replace EventWrapper use with EventFunctionWrapper

Change-Id: I6b03cc6f67e76dffb79940431711ae6171901c6a
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3748
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Replace EventWrapper use with EventFunctionWrapper

Change-Id: I08de5f72513645d1fe92bde99fa205dde897e951
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3747
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapper

Change-Id: Idd5992463bcf9154f823b82461070d1f1842cea3
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3746
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem: Replace EventWrapper use with EventFunctionWrapper

NOTE: With this change there is a possibility for `DRAMCtrl::Rank`s
event names to not properly match the rank they were generated by. This
could occur if the public rank member is modified after the Rank's
construction. A patch would mean refactoring Rank and `DRAMCtrl`b to
privatize many of the members of Rank behind getters.

Change-Id: I7b8bd15086f4ffdfd3f40be4aeddac5e786fd78e
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3745
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Replace EventWrapper in PacketQueue with EventFunctionWrapper

In order to replicate the same `name()` output with `PacketQueue`, subclasses
using EventFunctionWrapper must initialize PacketQueue with their own name so
the sendEvent holds the name of the subclass.

Change-Id: Ib091e118bab8858192e1d1370d61def42958ec29
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3744
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

sim: Add generic EventFunctionWrapper

Add EventFunctionWrapper, an event wrapper which takes any callable
object to use as its callback. (This includes c++ lambdas, function
pointers, bound functions, and std::functions.)

Change-Id: Iab140df47bd0f7e4b3fe3b568f9dd122a43cee1c
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3743
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

mem: Move the Rank construction logic to the Rank constructor

This change was made so Rank objects have their name assigned
when they are instantiated. Therefore, they can initialize their
member objects with their name and it is less likely to change during
runtime.

(NOTE: I would recommend hiding the fields which would cause the name to
change behind getters. Since modification of `Rank.rank` during runtime
will cause the `name()` to change.)

Change-Id: Id51c3553b40e489792c57950e18b8ce927e43173
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3742
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

sim: Remove DelayFunction

`DelayFunction` is unused.

Change-Id: I28aa756054c9b121fe4cfa65c393366f26ccb128
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3741
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

configs, arm: add option to enable security extensions

Change-Id: I0c839bb649a5d2d73080b7e718da3c9b5839cf8c
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3264
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm: ignore writes to the reset_ctl register

Change-Id: I953521572e6ace475b656369c9f07ddfa50d731a
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3263
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev, arm: add a9mpcore global timer device

Change-Id: I6d8a5e3795291b2a4cce022f555cf4b04f997538
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3262
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev, virtio: Use of Unix socket for virtIO 9P device

This commit adds support for diod to use a unix socket, rather
than a TCP port.  We don't rely on the IP-based connection as we
directly use pipes to interact with diod.  This allows it to work
on any system, even if the specific port is taken by another diod
instance (or similar).  Secondly, the Unix socket could in theory
be used to debug.  However, this functionality has not been
tested.

Change-Id: I616e0ad8768da1dfc867de3af98cdfbb22a72d63
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2820
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

tests: Fix a typo for the default MI_example protocol

Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3795
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

x86: Add consistent overrides to process.hh

Change-Id: I912601b6f781a0bbedd06583c059589374f6d5c6
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3720
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Joe Gross <joe.gross@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

x86: Fixed remote debugging of simulated code

GDB breaks if more bytes are sent than the transmitted registers
actually need. Therefore the GdbRegCache struct needs to be packed to
prevent padding at the end.

Change-Id: Ib2c14eb70becdac609eb4f475d5dddbd5bcc60da
Signed-off-by: Matthias Hille <matthiashille8@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/3020
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

configs: fixed SimpleOpts missing error by adding library path

Change-Id: I0de761c8a322a506e436d5c7f12ee509535f52fd
Reviewed-on: https://gem5-review.googlesource.com/2801
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-garnet: Fix garnet stats

This patch fix some statistics that in presence of a resetStats
instruction were not  reseted. This bug makes impossible to obtain
reliable network statistics when the simulation doesn't start from tick
zero.

Change-Id: Ibec45f08d95bf0a533d94b70ec960719206ae945
Maintainer: Tushar Krishna <tushar@ece.gatech.edu>
Reviewed-on: https://gem5-review.googlesource.com/3700
Reviewed-by: Jieming Yin <bjm419@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests: Add ARM MOESI_CMP_directory regressions

Change-Id: I3d9c1249a2d39f20fb60c4d4e8af7d1d5731dbef
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2908
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Refactor the VExpress_EMM system creation

Change-Id: Iac3d15719b2bbc426020a27d6b47a4baaab078c7
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2907
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Make MOESI_CMP_directory the default ARM ruby protocol

Previously ARM binaries were by default compiled with the MI_example
protocol. The MI_example protocol cannot properly support load/store
exclusive instructions and therefore it cannot be used to simulate
multicore ARM systems. This change changes to MOESI_CMP_directory as
the default ruby protocol for ARM systems.

Change-Id: I942d950ba466aea9a75f3d8764f9f3eddd0c3baa
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2906
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

config: Warn not fail for ARM systems configured with ruby

Ruby for ARM systems is not fully supported but certain configurations
are expected to work. This change removes the more general fail
statement and warns or fails depending on the particular
configuration.

Change-Id: Ic24799aff966ba15858b93482e0f24a8672d9483
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2905
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

ruby, arm: Forward invalidations to the local exclusive monitor

ARM systems require local exclusive monitors for the implementation of
synchronization primitives between processors. A ruby memory system
needs to forward invalidations to the local exclusive monitors to
to correctly determine their state.

Change-Id: I7bc4d0f2a5be0f4e36a25c87aa4a81a3f086fb3c
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2904
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

ruby: Add support for address ranges in the directory

Previously the directory covered a flat address range that always
started from address 0. This change adds a vector of address ranges
with interleaving and hashing that each directory keeps track of and
the necessary flexibility to support systems with non continuous
memory ranges.

Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2903
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev: Avoid arbitrarily deep stack depth in the i8254xGBe model.

When it comes time to send a packet with the i8254xGBe model hooked up to
EtherTap and while running in KVM mode, the packet will first go to the
EtherTap over the network style port between them. EtherTap, because it's
not actually a model of anything in the simulation, will immediately pass
the packet off to the real network and report that the transmission was
successful to the i8254xGBe. The i8254xGBe will notice that it still has
stuff it can send (the KVM mode CPU has no trouble keeping it full) and
will, without returning and collapsing the stack, immediately call back
into EtherTap with the next packet. This loop repeats, continually
deepening the stack, until gem5 crashes with a segfault.

To break this loop, a few small changes have been made. First, txFifoTick
has been repurposed slightly so that it continuously keeps track of
whether there's still work to do to flush out the fifo during the current
tick. The code in txWire has been adjusted slightly so that it clears that
variable at the start (also removing some redundancy), so that other code
can set it again if more work needs to be done. Specifically, the
ethTxDone function will set that flag.

If there's more work to be done flushing the Fifo while in tick(), it
will loop until txFifoTick stays cleared, meaning either the Fifo is
empty, or the object on the other end hasn't said it's done yet.

Finally, a new bool member called inTick has been added which keeps track
of whether the tick() function is still active somewhere in the callstack.
If it is, then the tick event shouldn't be rescheduled in ethTxDone, since
tick will take care of that before it returns. It won't check to see if it
needs to, and so without this check there's a panic from scheduling the
same event twice.

It's not completely clear that the Fifo should send packets over and over
as fast as the other side accepts them within the same tick, although it's
not clear that it shouldn't either. If not, then probably all that would
need to change would be to remove the "while" loop so that the tick event
would be rescheduled, and the Fifo would be further emptied the next time
around.

Change-Id: I653379b43389d0539ecfadb3fc6c40e38a8864c2
Reviewed-on: https://gem5-review.googlesource.com/3642
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

scons: Try to handle problems with gcc, lto and partial linking.

gcc has had a lot of problems with incremental linking and partial linking
at the same time. Basically, the partial link assumes that it's the only
link that's going to happen, and it converts weak external symbols into
regular external symbols. Then when the real final link happens, those
symbols are duplicated and the link fails.

Versions of gcc 6 and greater add an option called -flinker-output which
lets you tell the linker to do an incremental link. Unfortunately, other
bugs make that fail, and so gcc 6 doesn't work either. Hopefully version
7 works better.

A --force-lto option was added so that, when only one of lto and partial
linking is available, you can switch from having partial linking to having
lto.

Change-Id: I5e293f5cfb07a14343dc74030d99cb161fb8bbbe
Reviewed-on: https://gem5-review.googlesource.com/3680
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests: Update RISC-V hello test and stats

Update the "Hello, world!" executable for RISC-V to use the latest GNU
Linux toolchain and fix the stats accordingly.

Change-Id: I5ff3d7f4bb41b10170038b8c07492f15bb54a022
Reviewed-on: https://gem5-review.googlesource.com/3560
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

scons: Add use_tuntap to export list

Fixes broken build after c58537c.

Change-Id: I686ffaaad4fe558b6e51c89c9b26121318c2b721
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/3647
Reviewed-by: Gabe Black <gabeblack@google.com>

base: misc: Include cstdlib in base/misc.hh.

Some of the macros, notably panic, uses exit(). Callers shouldn't have to
know that or have coincidentally included cstdlib, the provider of exit,
themselves.

Change-Id: I634602ed1795dcc8897b4bddb1167c96763acc18
Reviewed-on: https://gem5-review.googlesource.com/3601
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config: Adjust load_addr_mask in VExpress_GEM5_V1

Fix load_addr_mask in VExpress_GEM5_V1 in order to boot with the 64-bit
kernel.

Change-Id: I13a0a752c60e53262a245cb24b16606071041397
Reviewed-on: https://gem5-review.googlesource.com/3643
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Ignore build products in src/util/term.

Change-Id: I8027a282c261d29cd276742411eb0ed3ce078247
Reviewed-on: https://gem5-review.googlesource.com/3641
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

misc: Add git ignore patterns for build products in src/util/tap

Change-Id: I498058255a05585e8142bdaa852549e20c27e347
Reviewed-on: https://gem5-review.googlesource.com/3640
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev: Add a version of EtherTap which uses the tap driver.

The object is called EtherTap (as opposed to EtherTapStub, what the former
EtherTap was renamed to), and its existance is gated on the linux/if_tun.h
header file existing. That's probably overly strict, but it will hopefully
be minimally likely to break the build for other systems.

Change-Id: Ie03507fadf0d843a4d4d52f283c44a416c6f2a74
Reviewed-on: https://gem5-review.googlesource.com/3646
Reviewed-by: Nathan Binkert <nate@binkert.org>
Maintainer: Nathan Binkert <nate@binkert.org>

dev: Refactor the EtherTapStub to make room for using tap.

A lot of the implementation of EtherTapStub can be shared with a version
which uses a tap device directly. This change factors out those parts to
accommodate that.

Change-Id: I9c2e31f1be139ca73859a83f05457cef90101006
Reviewed-on: https://gem5-review.googlesource.com/3645
Reviewed-by: Nathan Binkert <nate@binkert.org>
Maintainer: Nathan Binkert <nate@binkert.org>

dev: Rename EtherTap to be EtherTapStub.

The EtherTap object is going to be reworked so that it connects to a tap
device directly, but it's worthwhile to still be able to use the m5tap
utility (util/tap) to send/receive packets on systems which don't support
tap but do support the pcap API. It can also be used to replay ethernet
frames, to capture the ethernet frames coming from gem5 for analysis, to
programmatically consume and/or generate the frames, or even to forward
them to/from a remote system.

Change-Id: Ic7bd763d86cd913ac373dd10a8d6d1fc6b35f95a
Reviewed-on: https://gem5-review.googlesource.com/3644
Reviewed-by: Nathan Binkert <nate@binkert.org>
Maintainer: Nathan Binkert <nate@binkert.org>

misc: Fix building the m5tap utility.

Use printf instead of cprintf to avoid having to have .o files from gem5.
Stop disabling optimization. Placate the style checker by rearranging the
header include order. Include some missing standard headers. Switch from
the deprecated -I- gcc option to using -iquote. Make the "program"
variable a const char *. When checking the return value of getopt, don't
check against the char c which may mask the -1 return value. Instead,
store the return value in an int, and then later cast it to a char when
it's actually consumed.

Change-Id: Ibec51927d0cdbd98db8e53081be2c4931e20333c
Reviewed-on: https://gem5-review.googlesource.com/3600
Reviewed-by: Nathan Binkert <nate@binkert.org>
Maintainer: Nathan Binkert <nate@binkert.org>

dev: Add a missing parameter to the EtherTap device.

There needs to be a SlavePort called "tap" for the ethertap device to be
able to connect to the gem5 network successfully.

Change-Id: I1ad81219f612fd1ec278c6148af728d20bc916da
Reviewed-on: https://gem5-review.googlesource.com/3580
Reviewed-by: Nathan Binkert <nate@binkert.org>
Maintainer: Nathan Binkert <nate@binkert.org>

ruby: Don't set the block data when a store conditional fails

Previously the Sequencer upon a Store Conditional would
unconditionally set the data of the memory location. This change
checks and prevents a failed Store Conditional from modifying any
data.

Change-Id: Id63c9579d8f054f0e95c6d338a7e31aa48762755
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2902
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

python: Fix unproxing of VectorParams

Previously proxy vector parameters would resolve correctly only for
Parent.all. Any other proxy such as Parent.any, or exact ones such as
Parent.addr_range would resolve to a *vector* of the right value
resulting into a vector of a vector. For example if we set:

DirectoryController0.addr_range = [0x100000-0x1fffff, 0x200000-0x2fffff]
DirectoryMemory0.addr_range = Parent.addr_range

where DirectoryController0 is the parent SimObject of DirectoryMemory0
after unproxying the Parent.addr_range VectorParam we would get

DirectoryMemory0.addr_range = [[0x100000-0x1fffff, 0x200000-0x2fffff]]

This change unifies handling of all three proxies to the same correct
unproxy mechanism.

Change-Id: Ie5107f69f58eb700b3e1b92c55210e0d53e6788d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2901
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

dev, arm: ignore writes to the SCU

Change-Id: I31808b6d7ca2bc2af41deaec747e3a13bd4f77d2
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3261
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: check address range in the SystemC example

Using a wrong offset or memory size may lead to segmentation faults.
This patch adds an address range check and produces an error message.

Change-Id: I79a72c05879266daf61a83367fe4ae386d1958a4
Reviewed-on: https://gem5-review.googlesource.com/3482
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>

misc: Reorder sources in util/tlm and rewrite build scripts

* Use one SConstruct to build everything instead of one SConstruct for
  each example.
* Introduce SConscripts for sub-directories.
* Build in 'build' instead of the source tree.
* Build and link to SystemC from the ext/systemc directory. This
  ensures that SystemC does not need to be installed on the host and
  avoids possible issues caused by an incompatible SystemC build.
* Update the README and add some minor fixes

Change-Id: I641ed94f542626864fb7af499ad1be8fd4ad929f
Reviewed-on: https://gem5-review.googlesource.com/3480
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

ext: Revamp the systemc SConscripts.

The existing scripts were including pthread code and QT code at the same
time, and also insisting on an having a set of architecture specific
source files for whatever the current architecture is.

This change selects using either QT or pthreads based on the host
architecture, distributes accumulating source files, list source files
explicitly (to avoid including redundant coroutine libraries) and makes
scons insist on an architecture specific QT implementation only if QT is
being used. It also defines a preprocessor symbol which tells some headers
whether or not pthreads are being used, and also clones the scons
environment to avoid leaking flags into the main environment used to
compile gem5 itself.

If the host architecture isn't supported by systemc, a warning will be
printed, and the various build products and SConscript files will be
skipped over.

Change-Id: I1a40123a11e49e02922a054f093246cf197087bf
Reviewed-on: https://gem5-review.googlesource.com/3461
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Christian Menard <christian.menard@tu-dresden.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

x86: Rework how VEX prefixes are decoded.

Remove redundant information from the ExtMachInst, hash the vex
information to ensure the decode cache works properly, print the vex info
when printing an ExtMachInst, consider the vex info when comparing two
ExtMachInsts, fold the info from the vex prefixes into existing settings,
remove redundant decode code, handle vex prefixes one byte at a time and
don't bother building up the entire prefix, and let instructions that care
about vex use it in their implementation, instead of developing an entire
parallel decode tree.

This also eliminates the error prone vex immediate decode table which was
incomplete and would result in an out of bounds access for incorrectly
encoded instructions or when the CPU was mispeculating, as it was (as far
as I can tell) redundant with the tables that already existed for two and
three byte opcodes. There were differences, but I think those may have
been mistakes based on the documentation I found.

Also, in 32 bit mode, the VEX prefixes might actually be LDS or LES
instructions which are still legal in that mode. A valid VEX prefix would
look like an LDS/LES with an otherwise invalid modrm encoding, so use that
as a signal to abort processing the VEX and turn the instruction into an
LES/LDS as appropriate.

Change-Id: Icb367eaaa35590692df1c98862f315da4c139f5c
Reviewed-on: https://gem5-review.googlesource.com/3501
Reviewed-by: Joe Gross <joe.gross@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

x86: sim: Make 32 bit x86 processes work again.

When the LiveProcess class was renamed to be just Process, the CL author
also changed the syscall function from a virtual function into a regular
one. Unfortunately, the I386Process class overrode the syscall function
to adjust the return address so that control would return to the right
place. Without that adjustment, 32 bit x86 process would segfault and die
immediately after their first system call.

This change reinstates the virtual specifier on the base syscall function,
and adds an override keyword on the I386Process's version so that it won't
be orphaned again in the future. It also fixes some small style issues the
style checker script complained about.

Change-Id: I0d1178ea0eda6676050c8fc043820a2bb4d99c0d
Reviewed-on: https://gem5-review.googlesource.com/3500
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

util: generate fully qualified paths for cscope

Change-Id: I318c185b117b9608110544526fbaaa3fdcdeb8bc
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3260
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMU

The PMU model currently doesn't calculate the PMU event counter index
correctly for writes to the PMEVTYPER[0-5]_EL0 registers. Fix this
obvious mistake.

Change-Id: I2913eedddeb98480660e2d63948f6d727adf5ab8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3121
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>

python: Fix PyEvent reference counting bug

The current implementation of reference counting for PyEvents only
partially works. The native object is currently kept alive while it is
in the event queue. However, if the Python object goes out of scope,
the Python side of this object is garbage collected which leaves a
"dangling" native object. This results in confusing error messages
where PyBind is unable to find the Python implementation of an event
when it is triggered.

Implement reference counting using the generalized reference counting
API instead.

Change-Id: I4e8e04abc4f61dff238d718065f5371e73b38ab3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3222
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

sim: Add hooks to implement event reference counting

We currently only support deleting an event if it is triggered and not
re-scheduled. This is fine for most native code. However, there are
cases where Python needs to count references to make sure that the
Python object stays live while the native object is live.

Generalise the mechanism used to implement by adding reference
counting hooks to the event base class:

  * Event::acquire() / Event::acquireImpl()
  * Event::release() / Event::releaseImpl()

These calls can be used to implement both reference counting and the
existing AutoDelete functionality. The default implementation in Event
maintains backwards compatibility with the existing AutoDelete feature
by ignoring acquireImpl() and deleting the event on releaseImpl() if
it isn't scheduled anymore.

Since AutoDelete functionality is no longer the only way events can be
managed, this change introduces the new Managed flag. This flag
activates automatic memory management. The acquireImpl()/releaseImpl()
methods are only called from acquire()/release() it is set. To
maintain backwards compatibility, AutoDelete is used as an alias for
Managed.

Change-Id: I5637984c906a9d44c22780712cf1c521b8297149
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch-riscv: Fix bad stack initialization

This patch fixes a problem with RISC-V initial stack setup in SE mode
where the AT_RANDOM aux vector value contains an address that is too
close to the top of the stack and doesn't fit the required 16 bytes. To
fix this, the program header table was added to the top of the stack
just like the RISC-V proxy kernel does.

Change-Id: I814562e060ff041cd0d7a7c54c3685645bd325a3
Reviewed-on: https://gem5-review.googlesource.com/3401
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

arch-arm: Fix some poorly done type max and min in NEON

The ISA code for ARM calculates min and max elements for types using
bit manipulation. That triggers some warnings, treated as errors, as
the compiler can tell that there is an overflow and the sign
flips. Fixed using standard lib definitions instead.

Change-Id: Ie2331b410c7f76d4bd87da5afe9edf20c8ac91b3
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3481
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

ext: Upgrade PyBind11 to version 2.1.1

Change-Id: I16870dec402d661295f9d013dc23e362b2b2c169
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3225
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

python: Prevent Python wrappers from deleting SimObjects

The PyBind wrappers could potentially delete SimObjects if they don't
have any references. This is not desirable since there could be
pointers to such objects within the C++ world. This problem doesn't
normally occur since Python typically holds a pointer to the root node
as long as the simulator is running.

Prevent SimObject and Param deletion by using a PyBind-prescribed
unique_ptr with a dummy deleter as the pointer wrapper for the Python
world.

Change-Id: Ied14602c9ee69a083a69c5dae1b5fcf8efb4548a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3224
Reviewed-by: Gabe Black <gabeblack@google.com>

python: Fix weird memory issue in wrapped AddrRange vectors

There is a weird issue with the PyBind wrapper of
vector<AddrRange>. Assigning new values to a param that is a vector of
AddrRange sometimes results in an out-of-bounds memory access.

We work around this issue by treating AddrRange vectors as opaque
types. This slightly changes the semantics of the wrapper since Python
now manipulates the real object rather than a copy that has been
converted to a list.

Change-Id: Ie027c06e7a7262214b43b19a76b24fe4b20426c5
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Timothy Hayes <timothy.hayes@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3223
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

scons: Enable explicitly building something with no variant.

The SConstruct currently expects all explicit targets to be under a
variant directory like ARM or X86 which tells it what settings to use,
etc. There are things which scons knows how to build however, which do not
live under a variant directory, specifically everything under ext.

This change makes scons not look for a variant directory when it
encounters a target which is built by something in ext. This enables
things like explicitly building the systemc libraries, for example.

Change-Id: I8982a96fe49e3cb970ec78e11cea08703990c686
Reviewed-on: https://gem5-review.googlesource.com/3460
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Christian Menard <christian.menard@tu-dresden.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

python: Remove unused readline import

The readline module is imported by main.py but doesn't seem to be
used.

Change-Id: I7888e3b6ad0a0fedc14b0feec2adf0a39883bbf8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3421
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

base, sim, arch: Fix clang 5.0 warnings

Compiling gem5 with recent version of clang (4 and 5) triggers
warnings that are treated as errors:

  * Global templatized static functions result in a warning if they
    are not used. These should either be declared as static inline or
    without the static identifier to avoid the warning.

  * Some templatized classes contain static variables. The
    instantiated versions of these variables / templates need to be
    explicitly declared to avoid a compiler warning.

Change-Id: Ie8261144836e94ebab7ea04ccccb90927672c257
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3420
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

base: Refactor the GDB code.

The new version modularizes the implementation of the various commands,
gets rid of dynamic allocation of the register cache, fixes some small
style problems, and uses exceptions to simplify error handling internal to
the GDB stub.

Change-Id: Iff3548373ce4adfb99106a810f5713b769df89b2
Reviewed-on: https://gem5-review.googlesource.com/3280
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

syscall_emul, riscv: add override keyword to RISCV Process class

Change-Id: I2a146ae57aac3787389997961208474a97e7c155
Reviewed-on: https://gem5-review.googlesource.com/3360
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

configs: fix cpu names in big.LITTLE example

CPU aliases have been dropped, this change fixes the big.LITTLE example.

Change-Id: Idd59a6eca93448ef0e23087365fb5452bcef9247
Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-on: https://gem5-review.googlesource.com/3300
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm, config: added support for ex5 model of big.LITTLE

This patch enables using calibrated big and LITTLE cores, ex5_big and
ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5
model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory
hierarchy latencies have been calibrated using the lmbench micro-benchmark
suite. The preliminary validation results have been published as: 'Full-System
Simulation of big.LITTLE Multicore Architecture for Performance and Energy
Exploration', in International Symposium on Embedded Multicore/Many-core
Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016).

From http://reviews.gem5.org/r/3666

Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7
Signed-off-by: Anastasiia Butko <abutko@lbl.gov>
Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-on: https://gem5-review.googlesource.com/2464
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

ext: Include SystemC 2.3.1 into gem5

In the past it happened several times that some changes in gem5 broke the
SystemC coupling. Recently Accelera has changed the licence for SystemC
from their own licence to Apache2.0, which is compatible with gem5.
However, SystemC usually relies on the Boost library, but I was able to
exchange the boost calls by c++11 alternatives. The recent SystemC version
is placed into /ext and is integrated into gem5's build system. The goal is
to integrate some SystemC tests for the CI in some following patches.

Change-Id: I4b66ec806b5e3cffc1d7c85d3735ff4fa5b31fd0
Reviewed-on: https://gem5-review.googlesource.com/2240
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config: Changes to boot Android N

necessary kernel command line options in FSConfig.py

Change-Id: Id66f640b6beb4efa9c23080c3d2516eda688c72d
Reviewed-on: https://gem5-review.googlesource.com/3320
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

x86: Fix the multiplication microops.

If the operands were 64 bit, an intermediate calculation could lose a
carry bit. This change rearranges that intermediate calculation if the
operand width is large, and reworks the microop implementation in general
in an attempt to make it easier to understand.

Change-Id: Ib36333f3f2695a33cd9623e43682de22ebd2e7ea
Reviewed-on: https://gem5-review.googlesource.com/3381
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

python: Add a helper function to create Python events

Add a helper function, m5.event.create(), to create events from
Python. This function takes a callable Python object (e.g., a
function) as an argument and optionally a priority as a keyword
argument. This function was accidentally dropped from the public API
when switching to PyBind.

Change-Id: Icbd0e392d9506934ec2c9f541199aa35c1c2df8c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3220
Reviewed-by: Gabe Black <gabeblack@google.com>