Nilay Vaish [Fri, 17 Jan 2014 17:02:15 +0000 (11:02 -0600)]
ruby: remove unused label no_vector
Nilay Vaish [Fri, 10 Jan 2014 22:19:58 +0000 (16:19 -0600)]
stats: updates due to changes to ruby
Nilay Vaish [Fri, 10 Jan 2014 22:19:47 +0000 (16:19 -0600)]
ruby: move all statistics to stats.txt, eliminate ruby.stats
Nilay Vaish [Fri, 10 Jan 2014 22:19:40 +0000 (16:19 -0600)]
stats: add function for adding two histograms
This patch adds a function to the HistStor class for adding two histograms.
This functionality is required for Ruby. It also adds support for printing
histograms in a single line.
Nilay Vaish [Thu, 9 Jan 2014 16:45:50 +0000 (10:45 -0600)]
ruby: fix bug introduced to revision
8523754f8885
Nilay Vaish [Wed, 8 Jan 2014 10:26:25 +0000 (04:26 -0600)]
ruby: slicc: remove variable 'addr' used in calls to doTransition
This variable causes trouble if a variable of same name is declared in a
protocol file. Hence it is being eliminated.
Nilay Vaish [Sat, 4 Jan 2014 06:03:34 +0000 (00:03 -0600)]
ruby: add a three level MESI protocol.
The first two levels (L0, L1) are private to the core, the third level (L2)is
possibly shared. The protocol supports clustered designs. For example, one
can have two sets of two cores. Each core has an L0 and L1 cache. There are
two L2 controllers where each set accesses only one of the L2 controllers.
Nilay Vaish [Sat, 4 Jan 2014 06:03:33 +0000 (00:03 -0600)]
ruby: rename MESI_CMP_directory to MESI_Two_Level
This is because the next patch introduces a three level hierarchy.
--HG--
rename : build_opts/ALPHA_MESI_CMP_directory => build_opts/ALPHA_MESI_Two_Level
rename : build_opts/X86_MESI_CMP_directory => build_opts/X86_MESI_Two_Level
rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/MESI_Two_Level.py
rename : src/mem/protocol/MESI_CMP_directory-L1cache.sm => src/mem/protocol/MESI_Two_Level-L1cache.sm
rename : src/mem/protocol/MESI_CMP_directory-L2cache.sm => src/mem/protocol/MESI_Two_Level-L2cache.sm
rename : src/mem/protocol/MESI_CMP_directory-dir.sm => src/mem/protocol/MESI_Two_Level-dir.sm
rename : src/mem/protocol/MESI_CMP_directory-dma.sm => src/mem/protocol/MESI_Two_Level-dma.sm
rename : src/mem/protocol/MESI_CMP_directory-msg.sm => src/mem/protocol/MESI_Two_Level-msg.sm
rename : src/mem/protocol/MESI_CMP_directory.slicc => src/mem/protocol/MESI_Two_Level.slicc
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
Nilay Vaish [Sat, 4 Jan 2014 06:03:32 +0000 (00:03 -0600)]
ruby: remove cntrl_id from python config scripts.
Nilay Vaish [Sat, 4 Jan 2014 06:03:31 +0000 (00:03 -0600)]
ruby: add support for clusters
A cluster over here means a set of controllers that can be accessed only by a
certain set of cores. For example, consider a two level hierarchy. Assume
there are 4 L1 controllers (private) and 2 L2 controllers. We can have two
different hierarchies here:
a. the address space is partitioned between the two L2 controllers. Each L1
controller accesses both the L2 controllers. In this case, each L1 controller
is a cluster initself.
b. both the L2 controllers can cache any address. An L1 controller has access
to only one of the L2 controllers. In this case, each L2 controller
along with the L1 controllers that access it, form a cluster.
This patch allows for each controller to have a cluster ID, which is 0 by
default. By setting the cluster ID properly, one can instantiate hierarchies
with clusters. Note that the coherence protocol might have to be changed as
well.
Nilay Vaish [Sat, 4 Jan 2014 06:03:30 +0000 (00:03 -0600)]
ruby: some small changes
Steve Reinhardt [Sat, 4 Jan 2014 01:08:44 +0000 (17:08 -0800)]
config, x86: move kernel specification from tests to FSConfig.py
For some reason, the default x86 kernel is specified in
tests/configs/x86_generic.py and not in configs/common/FSConfig.py,
where the kernels for all the other ISAs are. This means that
running configs/example/fs.py for x86 fails because no kernel
is specified. Moving the specification over fixes this problem.
There is another problem that this uncovers, which is that going
past the init stage (i.e., past where the regression test stops)
fails because the fsck test on the disk device fails, but that's
a separate issue.
Steve Reinhardt [Sat, 4 Jan 2014 01:08:43 +0000 (17:08 -0800)]
python: provide better error message for wrapped C++ methods
If you successfully export a C++ SimObject method, but try to
invoke it from Python before the C++ object is created, you
get a confusing error that says the attribute does not exist,
making you question whether you successfully exported the
method at all. In reality, your only problem is that you're
calling the method too soon. This patch enhances the error
message to give you a better clue.
Steve Reinhardt [Sat, 4 Jan 2014 01:08:42 +0000 (17:08 -0800)]
python: don't die on assignment to cloned object
Updating the SimObject topology of a cloned hierarchy is a little
dangerous, in that cloning is a "deep copy" and the clone does not
inherit SimObject updates the same way it would inherit scalar
variable assignments.
However, because of various SimObject-valued proxy parameters,
like 'memories', 'clk_domain', and 'system', it turns out that
there are a number of implicit topology changes that happen at
instantiation, which means that these changes are impossible to
avoid. So in order to make cloning systems useful, this error
has to go. Changing it to a warning produces a lot of noise,
so it seems best just to delete it.
Christopher Torng [Mon, 30 Dec 2013 01:29:45 +0000 (19:29 -0600)]
sim: Add support for dynamic frequency scaling
This patch provides support for DFS by having ClockedObjects register
themselves with their clock domain at construction time in a member list.
Using this list, a clock domain can update each member's tick to the
curTick() before modifying the clock period.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Christopher Torng [Mon, 30 Dec 2013 01:29:45 +0000 (19:29 -0600)]
mips: Floating point convert bug fix
In mips architecture, floating point convert instructions use the
FloatConvertOp format defined in src/arch/mips/isa/formats/fp.isa. The type
of the operands in the ISA description file (_sw for signed word, or _sf for
signed float, etc.) is used to create a type for the operand in C++. Then the
operand is converted using the fpConvert() function in src/arch/mips/utility.cc.
If we are converting from a word to a float, and we want to convert 0xffffffff,
we expect -1 to be passed into fpConvert(). Instead, we see MAX_INT passed in.
Then fpConvert() converts _val_ to MAX_INT in single-precision floating point,
and we get the wrong value.
To fix it, the signs of the convert operands are being changed from unsigned to
signed in the MIPS ISA description.
Then, the FloatConvertOp format is being changed to insert a int32_t into the
C++ code instead of a uint32_t.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Thu, 26 Dec 2013 21:18:58 +0000 (15:18 -0600)]
stats: updates due to bug fixed in mesi coherence protocol
Nilay Vaish [Thu, 26 Dec 2013 21:18:55 +0000 (15:18 -0600)]
ruby: fix bugs in mesi cmp directory protocol
This patch fixes couple of bugs in the L2 controller of the mesi cmp
directory protocol.
1. The state MT_I was transitioning to NP on receiving a clean writeback
from the L1 controller. This patch makes it inform the directory controller
about the writeback.
2. The L2 controller was sending the dirty bit to the L1 controller and the
L2 controller used writeback from the L1 controller to update the dirty bit
unconditionally. Now, the L1 controller always assumes that the incoming
data is clean. The L2 controller updates the dirty bit only when the L1
controller writes to the block.
3. Certain unused functions and events are being removed.
Nilay Vaish [Sat, 21 Dec 2013 02:34:04 +0000 (20:34 -0600)]
ruby: slicc: replace max_in_port_rank with number of inports
This patch replaces max_in_port_rank with the number of inports. The use of
max_in_port_rank was causing spurious re-builds and incorrect initialization
of variables in ruby related regression tests. This was due to the variable
value being used across threads while compiling when it was not meant to be.
Since the number of inports is state machine specific value, this problem
should get solved.
Nilay Vaish [Sat, 21 Dec 2013 02:34:03 +0000 (20:34 -0600)]
ruby: declare variables to be unsigned in Address.hh
Nilay Vaish [Sat, 21 Dec 2013 02:34:03 +0000 (20:34 -0600)]
ruby: mesi: remove owner and sharer fields from directory tags
The directory controller should not have the sharer field since there is
only one level 2 cache. Anyway the field was not in use. The owner field
was being used to track the l2 cache version (in case of distributed l2) that
has the cache block under consideration. The information is not required
since the version of the level 2 cache can be obtained from a subset of the
address bits.
Nilay Vaish [Tue, 3 Dec 2013 16:51:40 +0000 (10:51 -0600)]
sim: reset stats after startup
Currently statistics are reset after the initial / checkpoint state
has been loaded. But ruby does some checkpoint processing in its
startup() function. So the stats need to be reset after the startup()
function has been called. This patch moves the class to stats.reset()
to achieve this change in functionality.
Nilay Vaish [Tue, 3 Dec 2013 16:36:04 +0000 (10:36 -0600)]
cpu: call BaseCPU startup() function in o3 cpu
Nilay Vaish [Tue, 3 Dec 2013 16:36:03 +0000 (10:36 -0600)]
util: update checkpoint aggregation script
The checkpoint aggregation script had become outdated due to numerous changes
to checkpoints over the past couple of years. This updates the script. It
now supports aggregation for x86 architecture instead of alpha. Also a couple
of new options have been added that specify the size of the memory file to be
created and whether or not the memory file should be compressed.
Andreas Sandberg [Fri, 29 Nov 2013 13:36:10 +0000 (14:36 +0100)]
base: Fix race in PollQueue and remove SIGALRM workaround
There is a race between enabling asynchronous IO for a file descriptor
and IO events happening on that descriptor. A SIGIO won't normally be
delivered if an event is pending when asynchronous IO is
enabled. Instead, the signal will be raised the next time there is an
event on the FD. This changeset simulates a SIGIO by setting the
async_io flag when setting up asynchronous IO for an FD. This causes
the main event loop to poll all file descriptors to check for pending
IO. As a consequence of this, the old SIGALRM hack should no longer be
needed and is therefore removed.
Andreas Sandberg [Fri, 29 Nov 2013 13:35:36 +0000 (14:35 +0100)]
base: Clean up signal handling
The PollEvent class dynamically installs a SIGIO and SIGALRM handler
when a file handler is registered. Most signal handlers currently get
registered in the initSignals() function. This changeset moves the
SIGIO/SIGALRM handlers to initSignals() to live with the other signal
handlers. The original code installs SIGIO and SIGALRM with the
SA_RESTART option to prevent syscalls from returning EINTR. This
changeset consistently uses this flag for all signal handlers to
ensure that other signals that trigger asynchronous behavior (e.g.,
statistics dumping) do not cause undesirable EINTR returns.
Nilay Vaish [Tue, 26 Nov 2013 23:05:25 +0000 (17:05 -0600)]
stats: updates due to changes to ticksToCycles()
Nilay Vaish [Tue, 26 Nov 2013 23:05:22 +0000 (17:05 -0600)]
sim: correct ticksToCycles() function.
Andreas Sandberg [Tue, 15 Oct 2013 08:09:23 +0000 (10:09 +0200)]
kvm: Set the perf exclude_host attribute if available
The performance counting framework in Linux 3.2 and onwards supports
an attribute to exclude events generated by the host when running
KVM. Setting this attribute allows us to get more reliable
measurements of the guest machine. For example, on a highly loaded
system, the instruction counts from the guest can be severely
distorted by the host kernel (e.g., by page fault handlers).
This changeset introduces a check for the attribute and enables it in
the KVM CPU if present.
Christian Menard [Tue, 26 Nov 2013 16:51:07 +0000 (17:51 +0100)]
x86: Implementation of Int3 and Int_Ib in long mode
This is an implementation of the x86 int3 and int immediate
instructions for long mode according to 'AMD64 Programmers Manual
Volume 3'.
Andreas Sandberg [Tue, 26 Nov 2013 16:40:58 +0000 (17:40 +0100)]
kvm: Remove the unused hostFreq member from BaseKvmCPU
sim: simulate with multiple threads and event queues
This patch adds support for simulating with multiple threads, each of
which operates on an event queue. Each sim object specifies which eventq
is would like to be on. A custom barrier implementation is being added
using which eventqs synchronize.
The patch was tested in two different configurations:
1. ruby_network_test.py: in this simulation L1 cache controllers receive
requests from the cpu. The requests are replied to immediately without
any communication taking place with any other level.
2. twosys-tsunami-simple-atomic: this configuration simulates a client-server
system which are connected by an ethernet link.
We still lack the ability to communicate using message buffers or ports. But
other things like simulation start and end, synchronizing after every quantum
are working.
Committed by: Nilay Vaish
Anthony Gutierrez [Fri, 15 Nov 2013 18:21:15 +0000 (13:21 -0500)]
cpu: allow the fetch buffer to be smaller than a cache line
the current implementation of the fetch buffer in the o3 cpu
is only allowed to be the size of a cache line. some
architectures, e.g., ARM, have fetch buffers smaller than a cache
line, see slide 22 at:
http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf
this patch allows the fetch buffer to be set to values smaller
than a cache line.
Andreas Hansson [Fri, 15 Nov 2013 08:47:10 +0000 (03:47 -0500)]
cpu: Fix Checker register index use
This patch fixes an issue in the checker CPU register indexing. The
code will not even compile using LTO as deep inlining causes the used
index to be outside the array bounds.
Steve Reinhardt [Thu, 14 Nov 2013 23:03:42 +0000 (15:03 -0800)]
tests: suppress output on switcheroo tests
The output from the switcheroo tests is voluminous and
(because it includes timestamps) highly sensitive to
minor changes, leading to extremely large updates to the
reference outputs. This patch addresses this problem
by suppressing output from the tests. An internal
parameter can be set to enable the output. Wiring that
up to a command-line flag (perhaps even the rudimantary
-v/-q options in m5/main.py) is left for future work.
Anthony Gutierrez [Tue, 12 Nov 2013 16:46:48 +0000 (11:46 -0500)]
sim: fix event priority name for debug-start option
Andreas Hansson [Fri, 1 Nov 2013 15:56:34 +0000 (11:56 -0400)]
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
Andreas Hansson [Fri, 1 Nov 2013 15:56:31 +0000 (11:56 -0400)]
mem: Fixes for DRAM stats accounting
This patch fixes a number of stats accounting issues in the DRAM
controller. Most importantly, it separates the system interface and
DRAM interface so that it is clearer what the actual DRAM bandwidth
(and consequently utilisation) is.
Andreas Hansson [Fri, 1 Nov 2013 15:56:30 +0000 (11:56 -0400)]
mem: Fix the LPDDR3 page size
This patch corrects the LPDDR3 page size, which was set too low.
Neha Agarwal [Fri, 1 Nov 2013 15:56:28 +0000 (11:56 -0400)]
mem: Adding stats for DRAM power calculation
This patch adds stats which are used for offline power calculation
from the 'Micron Power Calculator' spreadsheet.
Neha Agarwal [Fri, 1 Nov 2013 15:56:27 +0000 (11:56 -0400)]
mem: Unify request selection for read and write queues
This patch unifies the request selection across read and write queues
for FR-FCFS scheduling policy. It also fixes the request selection
code to prioritize the row hits present in the request queues over the
selection based on earliest bank availability.
Andreas Hansson [Fri, 1 Nov 2013 15:56:26 +0000 (11:56 -0400)]
mem: Add a simple adaptive version of the open-page policy
This patch adds a basic adaptive version of the open-page policy that
guides the decision to keep open or close by looking at the contents
of the controller queues. If no row hits are found, and bank conflicts
are present, then the row is closed by means of an auto
precharge. This is a well-known technique that should improve
performance in most use-cases.
Neha Agarwal [Fri, 1 Nov 2013 15:56:25 +0000 (11:56 -0400)]
mem: Just-in-time write scheduling in DRAM controller
This patch removes the untimed while loop in the write scheduling
mechanism and now schedule commands taking into account the minimum
timing constraint. It also introduces an optimization to track write
queue size and switch from writes to reads if the number of write
requests fall below write low threshold.
Andreas Hansson [Fri, 1 Nov 2013 15:56:24 +0000 (11:56 -0400)]
mem: Add tRRD as a timing parameter for the DRAM controller
This patch adds the tRRD parameter to the DRAM controller. With the
recent addition of the actAllowedAt member for each bank, this
addition is trivial.
Andreas Hansson [Fri, 1 Nov 2013 15:56:23 +0000 (11:56 -0400)]
mem: Less conservative tRAS in DRAM configurations
This patch changes the default values of the tRAS timing parameter to
be less conservative, and closer in line with existing parts.
Ani Udipi [Fri, 1 Nov 2013 15:56:22 +0000 (11:56 -0400)]
mem: Make tXAW enforcement less conservative and per rank
This patch changes the tXAW constraint so that it is enforced per rank
rather than globally for all ranks in the channel. It also avoids
using the bank freeAt to enforce the activation limit, as doing so
also precludes performing any column or row command to the
DRAM. Instead the patch introduces a new variable actAllowedAt for the
banks and use this to track when a potential activation can occur.
Neha Agarwal [Fri, 1 Nov 2013 15:56:21 +0000 (11:56 -0400)]
mem: Fix for 100% write threshold in DRAM controller
This patch fixes the controller when a write threshold of 100% is
used. Earlier for 100% write threshold no data is written to memory
as writes never get triggered since this corner case is not
considered.
Andreas Hansson [Fri, 1 Nov 2013 15:56:20 +0000 (11:56 -0400)]
mem: Pick the next DRAM request based on bank availability
This patch changes the FCFS bit of FR-FCFS such that requests that
target the earliest available bank are picked first (as suggested in
the original work on FR-FCFS by Rixner et al). To accommodate this we
add functionality to identify a bank through a one-dimensional
identifier (bank id). The member names of the DRAMPacket are also
update to match the style guide.
Ani Udipi [Fri, 1 Nov 2013 15:56:19 +0000 (11:56 -0400)]
mem: Use the same timing calculation for DRAM read and write
This patch simplifies the DRAM model by re-using the function that
computes the busy and access time for both reads and writes.
Ani Udipi [Fri, 1 Nov 2013 15:56:18 +0000 (11:56 -0400)]
mem: Fix DRAM bank occupancy for streaming access
This patch fixes an issue that allowed more than 100% bus utilisation
in certain cases.
Ani Udipi [Fri, 1 Nov 2013 15:56:17 +0000 (11:56 -0400)]
mem: Schedule time for DRAM event taking tRAS into account
This patch changes the time the controller is woken up to take the
next scheduling decisions. tRAS is now handled in estimateLatency and
doDRAMAccess and we do not need to worry about it at scheduling
time. The earliest we need to wake up is to do a pre-charge, row
access and column access before the bus becomes free for use.
Ani Udipi [Fri, 1 Nov 2013 15:56:16 +0000 (11:56 -0400)]
mem: Add tRAS parameter to the DRAM controller model
This patch adds an explicit tRAS parameter to the DRAM controller
model. Previously tRAS was, rather conservatively, assumed to be tRCD
+ tCL + tRP. The default values for tRAS are chosen to match the
previous behaviour and will be updated later.
Andreas Hansson [Fri, 1 Nov 2013 15:56:15 +0000 (11:56 -0400)]
stats: Bump stats after shifting to SimpleMemory
Match stats with new regression configs.
Andreas Hansson [Fri, 1 Nov 2013 15:56:14 +0000 (11:56 -0400)]
test: Use SimpleMemory for atomic full-system tests
Keep it simple and use the SimpleMemory rather than the DRAM
controller model for atomic full-system tests.
Andreas Hansson [Fri, 1 Nov 2013 15:56:13 +0000 (11:56 -0400)]
sim: Clarify the difference between tracing and debugging
This patch changes the name the command-line options related to debug
output to all start with "debug" rather than being a mix of that and
"trace". It also makes it clear that the breakpoint time is specified
in ticks and not in cycles.
Chander Sudanthi [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
ARM: add support for TEEHBR access
Thumb2 ARM kernels may access the TEEHBR via thumbee_notifier
in arch/arm/kernel/thumbee.c. The Linux kernel code just seems
to be saving and restoring the register. This patch adds support
for the TEEHBR cp14 register. Note, this may be a special case
when restoring from an image that was run on a system that
supports ThumbEE.
Matt Evans [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
dev: Add 'OSC' oscillator sys control reg support to VersatileExpress
The VE motherboard provides a set of system control registers through which
various motherboard and coretile registers are accessed. Voltage regulators and
oscillator (DLL/PLL) config are examples. These registers must be impleted to
boot Linux 3.9+ kernels.
Geoffrey Blake [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
dev: Add support for MSI-X and Capability Lists for ARM and PCI devices
This patch adds the registers and fields to the PCI device to support
Capability lists and to support MSI-X in the GIC.
Geoffrey Blake [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
dev: Fix race conditions in IDE device on newer kernels
Newer linux kernels and distros exercise more functionality in the IDE device
than previously, exposing 2 races. The first race is the handling of aborted
DMA commands would immediately report the device is ready back to the kernel
and cause already in flight commands to assert the simulator when they returned
and discovered an inconsitent device state. The second race was due to the
Status register not being handled correctly, the interrupt status bit would get
stuck at 1 and the driver eventually views this as a bad state and logs the
condition to the terminal. This patch fixes these two conditions by making the
device handle aborted commands gracefully and properly handles clearing the
interrupt status bit in the Status register.
Geoffrey Blake [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
base: Add support for ipv6 into inet.hh/inet.cc
Faissal Sleiman [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
cpu: Construct ROB with cpu params struct instead of each variable
Most other structures/stages get passed the cpu params struct.
Geoffrey Blake [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
config: Fix handling of parents for simobject vectors
SimObjectVector objects did not provide the same interface to
the _parent attribute through get_parent() like a normal
SimObject. It also handled assigning a _parent incorrectly
if objects in a SimObjectVector were changed post-creation,
leading to errors later when the simulator tried to execute.
This patch fixes these two omissions.
Dam Sunwoo [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
sim: added option to serialize SimLoopExitEvent
SimLoopExitEvents weren't serialized by default. Some benchmarks
utilize a delayed m5 exit pseudo op call to terminate the simulation
and this event was lost when resuming from a checkpoint generated
after the pseudo op call. This patch adds the capability to serialize
the SimLoopExitEvents and enable serialization for m5_exit and m5_fail
pseudo ops by default. Does not affect other generic
SimLoopExitEvents.
Stephan Diestelhorst [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
mem: Add "const" attribute to Packet getters
Add a "const" keywords to the getters in the Packet class so these can be
invoked on const Packet objects.
Prakash Ramrakhyani [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
mem: Add privilege info to request class
This patch adds a flag in the request class that indicates if the request
was made in privileged mode.
Ali Saidi [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
arm: fix m5ops binary for ARM and add m5fail.
Changes to make m5ops work under virtualization seemed to break them working
with non-virtualized systems and the recently added m5 fail command makes
the m5op binary not compile. For now remove the code for virtualization.
Ali Saidi [Thu, 31 Oct 2013 18:41:13 +0000 (13:41 -0500)]
cpu: Fix O3 issuse with load+barrier instructions.
Fix a problem in the O3 CPU for instructions that are both
memory loads and memory barriers (e.g. load acquire) and
to uncacheable memory. This combination can confuse the
commit stage into commitng an instruction that hasn't
executed and got it's value yet. At the same time refactor
the code slightly to remove duplication between two of
the cases.
Lluc Alvarez [Wed, 30 Oct 2013 15:35:06 +0000 (10:35 -0500)]
ruby: set SenderMachine in messages of MOESI_CMP_directory
This patch adds missing initializations of the SenderMachine field of
out_msg's when thery are created in the L2 cache controller of the
MOESI_CMP_directory coherence protocol. When an out_msg is created and this
field is left uninitialized, it is set to the default value MachineType_NUM.
This causes a panic in the MachineType_to_string function when gem5 is
executed with the Ruby debug flag on and it tries to print the message.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Emilio Castillo [Wed, 30 Oct 2013 15:35:05 +0000 (10:35 -0500)]
ruby: Fixed a deadlock when restoring a checkpoint with garnet
This patch fixes a problem where in Garnet, the enqueue time in the
VCallocator and the SWallocator which is of type Cycles was being stored
inside a variable with int type.
This lead to a known problem restoring checkpoints with garnet & the fixed
pipeline enabled. That value was really big and didn't fit in the variable
overflowing it, therefore some conditions on the VC allocation stage & the
SW allocation stage were not met and the packets didn't advance through the
network, leading to a deadlock panic right after the checkpoint was restored.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Stephan Diestelhorst [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
mem: De-virtualise interfaces in the CoherentBus
The CoherentBus eventually got virtual methods for its interface. The
"virtuality" of the CoherentBus, however, comes already from the virtual
interface of the bus' ports. There is no need to add another layer of virtual
functions, here.
Matt Horsnell [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
cpu: add consistent guarding to *_impl.hh files.
Sascha Bischoff [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
mem: Add PortID to QueuedMasterPort constructor
This patch adds the PortID to the QueuedMasterPort. This allows a PortID to be
specified as it previously was set to the detault value of -1.
Matt Evans [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
arm: Add a 'clear PPI' method to gic_pl390
The underlying assumption that all PPIs must be edge-triggered is
strained when the architected timers and VGIC interfaces make
level-behaviour observable. For example, a virtual timer interrupt
'goes away' when the hypervisor is entered and the vtimer is disabled;
this requires a PPI to be de-activated.
The new method simply clears the interrupt pending state.
Geoffrey Blake [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
config: Fix ommission of number base in ethernet address param
The ethernet address param tries to convert a hexadecimal
string using int() in python, which defaults to base 10,
need to specify base 16 in this case.
Geoffrey Blake [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
config: Fix for port references generated multiple times
SimObjects are expected to only generate one port reference per
port belonging to them. There is a subtle bug with using "not"
here as a VectorPort is seen as not having a reference if it is
either None or empty as per Python docs sec 9.9 for Standard operators.
Intended behavior is to only check if we have not created the reference.
Dam Sunwoo [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
dev: Add option to disable framebuffer .bmp dump in run folder
There is an option to enable/disable all framebuffer dumps, but the
last frame always gets dumped in the run folder with no other way to
disable it. These files can add up very quickly running many experiments.
This patch adds an option to disable them. The default behavior
remains unchanged.
Faissal Sleiman [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
cpu: Removing an unused variable in rename
Faissal Sleiman [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
cpu: Change IEW DPRINTF to use IEW debug flag
IEW DPRINTF uses Decode debug flag, which appears to be a copying error. This
patch changes this to the IEW Debug flag.
Faissal Sleiman [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
cpu: Put in assertions to check for maximum supported LQ/SQ size
LSQSenderState represents the LQ/SQ index using uint8_t, which supports up to
256 entries (including the sentinel entry). Sending packets to memory with a
higher index than 255 truncates the index, such that the response matches the
wrong entry. For instance, this can result in a deadlock if a store completion
does not clear the head entry.
Dam Sunwoo [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
util: Streamline .apc project convertsion script
This Python script generates an ARM DS-5 Streamline .apc project based
on gem5 run. To successfully convert, the gem5 runs needs to be run
with the context-switch-based stats dump option enabled (The guest
kernel also needs to be patched to allow gem5 interrogate its task
information.) See help for more information.
Eric Van Hensbergen [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
arm: Accomodate function name changes in newer linux kernels
Ali Saidi [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
arm: Fix a GIC mask register bug
This resulted in a kernel printk that said,
"GIC CPU mask not found - kernel will fail to boot."
Ali Saidi [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
cpu: Fix O3 uncacheable load that is replayed but misses the TLB
This change fixes an issue in the O3 CPU where an uncachable instruction
is attempted to be executed before it reaches the head of the ROB. It is
determined to be uncacheable, and is replayed, but a PanicFault is attached
to the instruction to make sure that it is properly executed before
committing. If the TLB entry it was using is replaced in the interveaning
time, the TLB returns a delayed translation when the load is replayed at
the head of the ROB, however the LSQ code can't differntiate between the
old fault and the new one. If the translation isn't complete it can't
be faulting, so clear the fault.
Ali Saidi [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
mem: Make MemoryAccess flag more verbose
This patch extends the MemoryAccess debug flag to report who sent the
requests and the cacheability.
Andreas Hansson [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
build: Place proto output in the same directory, also for EXTRAS
This patch changes the ProtoBuf builder such that the generated source
and header is placed in the build directory of the proto file. This
was previously not the case for the directories included as EXTRAS. To
make this work, we also ensure that the build directory for the EXTRAS
are added to the include path (which does not seem to automatically be
the case).
Ali Saidi [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
arm, config: Fix a small issue with the dtb file being specified
Ali Saidi [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
config: Fix memtest example script
Ali Saidi [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
dev: Allow additional UART interrupts to be set
This patch allows setting a few additional interrupts for status
changes that should never occur.
Stan Czerniawski [Thu, 17 Oct 2013 15:20:45 +0000 (10:20 -0500)]
build: Enable color diagnostics in clang by preserving TERM.
Andreas Sandberg [Wed, 16 Oct 2013 16:12:15 +0000 (18:12 +0200)]
kvm: Fix latency calculation of IPR accesses
When handling IPR accesses in doMMIOAccess, the KVM CPU used
clockEdge() to convert between cycles and ticks. This is incorrect
since doMMIOAccess is supposed to return a latency in ticks rather
than when the access is done. This changeset fixes this issue by
returning clockPeriod() * ipr_delay instead.
Steve Reinhardt [Wed, 16 Oct 2013 14:44:12 +0000 (10:44 -0400)]
test: update stats
Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
Steve Reinhardt [Tue, 15 Oct 2013 22:22:49 +0000 (18:22 -0400)]
ruby: eliminate non-determinism from ruby.stats output
Get rid of non-deterministic "stats" in ruby.stats output
such as time & date of run, elapsed & CPU time used,
and memory usage. These values cause spurious
miscomparisons when looking at output diffs (though
they don't affect regressions, since the regressions
pass/fail status currently ignores ruby.stats entirely).
Most of this information is already captured in other
places (time & date in stdout, elapsed time & mem usage
in stats.txt), where the regression script is smart
enough to filter it out. It seems easier to get rid of
the redundant output rather than teaching the
regression tester to ignore the same information in
two different places.
Steve Reinhardt [Tue, 15 Oct 2013 22:22:41 +0000 (18:22 -0400)]
scons: fix minor update-ref bug in regressions
In the unusual case that regressions are run with --update-ref
when there is no existing regression output, scons gets
confused because it depends on stats.txt to trigger the
update, but it has no indication that running the test will
generate the stats.txt file. (In the typical case where
stats.txt already exists, scons doesn't care about where
it came from.)
It's easy to fix this just by adding the stats.txt file
to the target list for the test action.
Yasuko Eckert [Tue, 15 Oct 2013 18:22:44 +0000 (14:22 -0400)]
arch/x86: add support for explicit CC register file
Convert condition code registers from being specialized
("pseudo") integer registers to using the recently
added CC register class.
Nilay Vaish also contributed to this patch.
Yasuko Eckert [Tue, 15 Oct 2013 18:22:44 +0000 (14:22 -0400)]
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Steve Reinhardt [Tue, 15 Oct 2013 18:22:44 +0000 (14:22 -0400)]
cpu/o3: clean up rename map and free list
Restructured rename map and free list to clean up some
extraneous code and separate out common code that can
be reused across different register classes (int and fp
at this point). Both components now consist of a set
of Simple* objects that are stand-alone rename map &
free list for each class, plus a Unified* object that
presents a unified interface across all register
classes and then redirects accesses to the appropriate
Simple* object as needed.
Moved free list initialization to PhysRegFile to better
isolate knowledge of physical register index mappings
to that class (and remove the need to pass a number
of parameters to the free list constructor).
Causes a small change to these stats:
cpu.rename.int_rename_lookups
cpu.rename.fp_rename_lookups
because they are now categorized on a per-operand basis
rather than a per-instruction basis.
That is, an instruction with mixed fp/int/misc operand
types will have each operand categorized independently,
where previously the lookup was categorized based on
the instruction type.
Steve Reinhardt [Tue, 15 Oct 2013 18:22:43 +0000 (14:22 -0400)]
cpu: rename *_DepTag constants to *_Reg_Base
Make these names more meaningful.
Specifically, made these substitutions:
s/FP_Base_DepTag/FP_Reg_Base/g;
s/Ctrl_Base_DepTag/Misc_Reg_Base/g;
s/Max_DepTag/Max_Reg_Index/g;
Steve Reinhardt [Tue, 15 Oct 2013 18:22:43 +0000 (14:22 -0400)]
isa: clean up register constants
Clean up and add some consistency to the *_Base_DepTag
constants as well as some related register constants:
- Get rid of NumMiscArchRegs, TotalArchRegs, and TotalDataRegs
since they're never used and not always defined
- Set FP_Base_DepTag = NumIntRegs when possible (i.e.,
every case except x86)
- Set Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs
(this was true before, but wasn't always expressed
that way)
- Drastically reduce the number of arbitrary constants
appearing in these calculations
Steve Reinhardt [Tue, 15 Oct 2013 18:22:43 +0000 (14:22 -0400)]
cpu/o3: clean up scoreboard object
It had a bunch of fields (and associated constructor
parameters) thet it didn't really use, and the array
initialization was needlessly verbose.
Also just hardwired the getReg() method to aleays
return true for misc regs, rather than having an array
of bits that we always kept marked as ready.
Steve Reinhardt [Tue, 15 Oct 2013 18:22:43 +0000 (14:22 -0400)]
cpu/o3: clean up physical register file
No need for PhysRegFile to be a template class, or
have a pointer back to the CPU. Also made some methods
for checking the physical register type (int vs. float)
based on the phys reg index, which will come in handy later.