nmigen.git
5 years agoback.rtlil: allow record slices on LHS.
whitequark [Sat, 20 Apr 2019 08:12:29 +0000 (08:12 +0000)]
back.rtlil: allow record slices on LHS.

5 years agohdl.rec: fix slicing of records.
whitequark [Fri, 19 Apr 2019 19:55:39 +0000 (19:55 +0000)]
hdl.rec: fix slicing of records.

5 years agohdl.xfrm: handle classes that inherit from Record.
whitequark [Thu, 18 Apr 2019 17:06:33 +0000 (17:06 +0000)]
hdl.xfrm: handle classes that inherit from Record.

5 years agolib.io: rework TSTriple/Tristate interface to use pin_layout/Pin.
whitequark [Mon, 15 Apr 2019 16:27:23 +0000 (16:27 +0000)]
lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin.

5 years agohdl.ast: fix some type checks.
whitequark [Wed, 10 Apr 2019 04:33:44 +0000 (04:33 +0000)]
hdl.ast: fix some type checks.

5 years agohdl.xfrm: allow using FragmentTransformer on any elaboratable.
whitequark [Wed, 10 Apr 2019 00:23:11 +0000 (00:23 +0000)]
hdl.xfrm: allow using FragmentTransformer on any elaboratable.

Fixes #29.

5 years agohdl: remove deprecated get_fragment() and lower() methods.
whitequark [Tue, 9 Apr 2019 23:53:43 +0000 (23:53 +0000)]
hdl: remove deprecated get_fragment() and lower() methods.

5 years agohdl.ast: handle a common typo, such as Signal(1, True).
whitequark [Wed, 3 Apr 2019 14:59:01 +0000 (14:59 +0000)]
hdl.ast: handle a common typo, such as Signal(1, True).

5 years agotest_sim: add missing add_process().
whitequark [Thu, 28 Mar 2019 17:50:14 +0000 (17:50 +0000)]
test_sim: add missing add_process().

Fixes #43.

5 years agolib.cdc: add optional reset to MultiReg, and document its use cases.
Luke Wren [Tue, 19 Mar 2019 03:36:55 +0000 (03:36 +0000)]
lib.cdc: add optional reset to MultiReg, and document its use cases.

5 years agoback.rtlil: fix off-by-one in Part legalization.
whitequark [Thu, 28 Mar 2019 05:12:02 +0000 (05:12 +0000)]
back.rtlil: fix off-by-one in Part legalization.

Fixes #52.

5 years agohdl.rec: separate record and signal name with __, not _.
anuejn [Mon, 25 Mar 2019 14:26:00 +0000 (15:26 +0100)]
hdl.rec: separate record and signal name with __, not _.

This makes names of signals within records less ambiguous, in case
they themselves have underscores within them.

5 years agohdl.ast: fix typo.
whitequark [Mon, 25 Mar 2019 10:49:29 +0000 (10:49 +0000)]
hdl.ast: fix typo.

Fixes #49.

5 years agoexamples.por: fix typo
Alain Péteut [Mon, 11 Mar 2019 17:11:51 +0000 (18:11 +0100)]
examples.por: fix typo

5 years agolib.fifo: register GrayEncoder output before CDC.
whitequark [Sun, 3 Mar 2019 18:23:51 +0000 (18:23 +0000)]
lib.fifo: register GrayEncoder output before CDC.

Without this register, static hazards in the encoder could cause
multiple encoder output bits to toggle, which would be incorrectly
sampled by the 2FF synchronizer.

Reported by @Wren6991.

5 years agotracer: factor out get_var_name(default=).
whitequark [Fri, 15 Feb 2019 14:15:02 +0000 (14:15 +0000)]
tracer: factor out get_var_name(default=).

5 years agohdl.rec: remove __slots__.
whitequark [Fri, 15 Feb 2019 14:00:42 +0000 (14:00 +0000)]
hdl.rec: remove __slots__.

Left in by mistake.

5 years agosetup.py: constrain Python version
Alain Péteut [Fri, 22 Feb 2019 08:45:28 +0000 (09:45 +0100)]
setup.py: constrain Python version

Installation should be constraint to supported Python versions, using `python_requires`,
refer to [1] for details.

[1] https://packaging.python.org/guides/distributing-packages-using-setuptools/#python-requires

5 years agohdl.ir: raise a more descriptive error on non-elaboratable object.
whitequark [Thu, 14 Feb 2019 20:52:42 +0000 (20:52 +0000)]
hdl.ir: raise a more descriptive error on non-elaboratable object.

5 years agoback.rtlil: accept ast.Const as cell parameter.
whitequark [Sat, 26 Jan 2019 23:25:54 +0000 (23:25 +0000)]
back.rtlil: accept ast.Const as cell parameter.

5 years agohdl.ast: fix ValueKey for Cat.
whitequark [Sat, 26 Jan 2019 23:25:34 +0000 (23:25 +0000)]
hdl.ast: fix ValueKey for Cat.

5 years agocompat.fhdl.module: fix typo.
whitequark [Sat, 26 Jan 2019 23:08:55 +0000 (23:08 +0000)]
compat.fhdl.module: fix typo.

5 years agocompat.fhdl.specials: fix __all__ list.
whitequark [Sat, 26 Jan 2019 22:59:33 +0000 (22:59 +0000)]
compat.fhdl.specials: fix __all__ list.

5 years agocompat.genlib.resetsync: add shim for AsyncResetSynchronizer.
whitequark [Sat, 26 Jan 2019 18:24:12 +0000 (18:24 +0000)]
compat.genlib.resetsync: add shim for AsyncResetSynchronizer.

5 years agocompat.fifo: fix _FIFOInterface deprecation wrapper.
whitequark [Sat, 26 Jan 2019 18:23:58 +0000 (18:23 +0000)]
compat.fifo: fix _FIFOInterface deprecation wrapper.

5 years agolib.cdc: add ResetSynchronizer.
whitequark [Sat, 26 Jan 2019 18:07:59 +0000 (18:07 +0000)]
lib.cdc: add ResetSynchronizer.

5 years agoback.pysim: support async reset.
whitequark [Sat, 26 Jan 2019 18:07:43 +0000 (18:07 +0000)]
back.pysim: support async reset.

5 years agoback.pysim: give better names to unnamed fragments and their signals.
whitequark [Sat, 26 Jan 2019 18:07:16 +0000 (18:07 +0000)]
back.pysim: give better names to unnamed fragments and their signals.

Was: top.#0, top.None_clk
Now: top.U0, top.U0_clk

(U for Unnamed, or similarly, an unit refdes.)

5 years agoexamples: update for newer API.
whitequark [Sat, 26 Jan 2019 16:25:05 +0000 (16:25 +0000)]
examples: update for newer API.

5 years agoback.rtlil: accept any elaboratable, not just fragments.
whitequark [Sat, 26 Jan 2019 16:11:29 +0000 (16:11 +0000)]
back.rtlil: accept any elaboratable, not just fragments.

5 years agocompat: suppress deprecation warnings that are internal or during test.
whitequark [Sat, 26 Jan 2019 15:43:00 +0000 (15:43 +0000)]
compat: suppress deprecation warnings that are internal or during test.

5 years agotest.compat: reenable tests converting to Verilog.
whitequark [Sat, 26 Jan 2019 15:29:09 +0000 (15:29 +0000)]
test.compat: reenable tests converting to Verilog.

5 years agocompat.sim: fix deprecated stdlib import.
whitequark [Sat, 26 Jan 2019 15:26:54 +0000 (15:26 +0000)]
compat.sim: fix deprecated stdlib import.

5 years agohdl.ir: rename .get_fragment() to .elaborate().
whitequark [Sat, 26 Jan 2019 02:31:12 +0000 (02:31 +0000)]
hdl.ir: rename .get_fragment() to .elaborate().

Closes #9.

5 years agotest.compat: import tests from Migen as appropriate.
whitequark [Tue, 18 Dec 2018 18:05:37 +0000 (18:05 +0000)]
test.compat: import tests from Migen as appropriate.

test_signed and test_coding are adjusted slightly to account for
differences in comb propagation between the simulators; we might want
to revert that eventually.

5 years agohdl.ast: fix shape calculation for *.
whitequark [Sat, 26 Jan 2019 00:54:02 +0000 (00:54 +0000)]
hdl.ast: fix shape calculation for *.

This was carried over from Migen, and is wrong there too.
Counterexample: 1'sd-1 * 4'sd-4 = 4'sd-4 (but should be 5'sd4).

5 years agoback.pysim: fix behavior of initial cycle for sync processes.
whitequark [Tue, 22 Jan 2019 17:51:44 +0000 (17:51 +0000)]
back.pysim: fix behavior of initial cycle for sync processes.

The current behavior was introduced in 65702719, which was a wrong
fix for an issue that was actually fixed in 12e04e4e. This commit
effectively reverts 65702719 and 1782b841.

5 years agolib.fifo: in FIFOInterface.read(), check readable on the right cycle.
whitequark [Tue, 22 Jan 2019 07:03:46 +0000 (07:03 +0000)]
lib.fifo: in FIFOInterface.read(), check readable on the right cycle.

5 years agocompat.genlib.fifo: adjust _FIFOInterface shim to not require fwft=.
whitequark [Tue, 22 Jan 2019 06:56:46 +0000 (06:56 +0000)]
compat.genlib.fifo: adjust _FIFOInterface shim to not require fwft=.

5 years agolib.fifo: fix typo in AsyncFIFO documentation.
whitequark [Tue, 22 Jan 2019 05:47:50 +0000 (05:47 +0000)]
lib.fifo: fix typo in AsyncFIFO documentation.

5 years agolib.fifo: add AsyncFIFO and AsyncFIFOBuffered.
whitequark [Mon, 21 Jan 2019 16:02:46 +0000 (16:02 +0000)]
lib.fifo: add AsyncFIFO and AsyncFIFOBuffered.

5 years agoback.pysim: wake up processes before ever committing any values.
whitequark [Mon, 21 Jan 2019 16:00:25 +0000 (16:00 +0000)]
back.pysim: wake up processes before ever committing any values.

Otherwise, the contract of the simulator to sync processes is not
always fulfilled.

5 years agocompat.genlib.cdc: add missing import.
whitequark [Sun, 20 Jan 2019 03:03:48 +0000 (03:03 +0000)]
compat.genlib.cdc: add missing import.

5 years agocompat.genlib.cdc: add GrayCounter and GrayDecoder shims.
whitequark [Sun, 20 Jan 2019 02:29:08 +0000 (02:29 +0000)]
compat.genlib.cdc: add GrayCounter and GrayDecoder shims.

5 years agolib.coding: add GrayEncoder and GrayDecoder.
whitequark [Sun, 20 Jan 2019 02:20:34 +0000 (02:20 +0000)]
lib.coding: add GrayEncoder and GrayDecoder.

Unlike the Migen ones, these are purely combinatorial.

5 years agolib.coding: add width as attribute to all coders.
whitequark [Sun, 20 Jan 2019 01:59:09 +0000 (01:59 +0000)]
lib.coding: add width as attribute to all coders.

5 years agolib.fifo: use memory in the FIFO model.
whitequark [Sat, 19 Jan 2019 09:27:13 +0000 (09:27 +0000)]
lib.fifo: use memory in the FIFO model.

This is unfortunately more complicated, but results in a much faster
proof.

5 years agolib.fifo: use model equivalence to simplify formal specification.
whitequark [Sat, 19 Jan 2019 08:57:18 +0000 (08:57 +0000)]
lib.fifo: use model equivalence to simplify formal specification.

This is unfortunately slow, and should probably be using theory
of arrays.

5 years agohdl.ast: implement shape for modulo operator.
whitequark [Sat, 19 Jan 2019 09:26:26 +0000 (09:26 +0000)]
hdl.ast: implement shape for modulo operator.

5 years agohdl.ast: add Value.implies.
whitequark [Sat, 19 Jan 2019 08:56:44 +0000 (08:56 +0000)]
hdl.ast: add Value.implies.

5 years agohdl.xfrm: mark internal registers used in lowering Sample().
whitequark [Sat, 19 Jan 2019 06:02:04 +0000 (06:02 +0000)]
hdl.xfrm: mark internal registers used in lowering Sample().

5 years agodoc: update COMPAT_SUMMARY.
whitequark [Sat, 19 Jan 2019 01:01:32 +0000 (01:01 +0000)]
doc: update COMPAT_SUMMARY.

5 years agofhdl.specials: add compatibility shim for Tristate.
whitequark [Sat, 19 Jan 2019 02:19:06 +0000 (02:19 +0000)]
fhdl.specials: add compatibility shim for Tristate.

5 years agolib.fifo: fix simulation read/write methods to take only one cycle.
whitequark [Sat, 19 Jan 2019 01:37:58 +0000 (01:37 +0000)]
lib.fifo: fix simulation read/write methods to take only one cycle.

5 years agocompat.genlib.fifo: add aliases for SyncFIFO, SyncFIFOBuffered.
whitequark [Sat, 19 Jan 2019 01:06:27 +0000 (01:06 +0000)]
compat.genlib.fifo: add aliases for SyncFIFO, SyncFIFOBuffered.

5 years agolib.fifo: formally verify FIFO contract.
whitequark [Sat, 19 Jan 2019 00:52:56 +0000 (00:52 +0000)]
lib.fifo: formally verify FIFO contract.

5 years agohdl.ast: give Assert and Assume their own src_loc.
whitequark [Sat, 19 Jan 2019 00:08:51 +0000 (00:08 +0000)]
hdl.ast: give Assert and Assume their own src_loc.

This helps with patterns like `Assert(fsm.ongoing("IDLE"))`, which
would otherwise point into nMigen internals.

5 years agoback.rtlil: only emit each AnyConst/AnySeq cell once.
whitequark [Fri, 18 Jan 2019 01:27:17 +0000 (01:27 +0000)]
back.rtlil: only emit each AnyConst/AnySeq cell once.

These are semantically like signals, not like constants.

5 years agocli: add missing default for `generate`
Alain Péteut [Thu, 17 Jan 2019 20:32:47 +0000 (21:32 +0100)]
cli: add missing default for `generate`

5 years agolib.fifo: add basic formal specification.
whitequark [Thu, 17 Jan 2019 05:26:54 +0000 (05:26 +0000)]
lib.fifo: add basic formal specification.

5 years agohdl.ast: allow sampling ClockSignal, ResetSignal.
whitequark [Thu, 17 Jan 2019 05:23:06 +0000 (05:23 +0000)]
hdl.ast: allow sampling ClockSignal, ResetSignal.

5 years agohdl.ast: add Past, Stable, Rose, Fell.
whitequark [Thu, 17 Jan 2019 04:31:27 +0000 (04:31 +0000)]
hdl.ast: add Past, Stable, Rose, Fell.

5 years agoformal: extract from toplevel module.
whitequark [Thu, 17 Jan 2019 01:43:07 +0000 (01:43 +0000)]
formal: extract from toplevel module.

The nMigen formal language is about to get *much* larger and will
keep growing faster than the rest of nMigen language, so it makes
good sense to extract it. Further, this makes it easier to qualify
formal keywords like `formal.AnyConst()` without directly importing
hdl.ast.

5 years agohdl.xfrm: add SampleLowerer.
whitequark [Thu, 17 Jan 2019 01:41:02 +0000 (01:41 +0000)]
hdl.xfrm: add SampleLowerer.

5 years agohdl.ast: add Sample.
whitequark [Thu, 17 Jan 2019 01:36:27 +0000 (01:36 +0000)]
hdl.ast: add Sample.

5 years agolib.fifo: port sync FIFO queues from Migen.
whitequark [Wed, 16 Jan 2019 17:19:46 +0000 (17:19 +0000)]
lib.fifo: port sync FIFO queues from Migen.

5 years agohdl.ast: fix naming of Signal.like() signals when tracer fails.
whitequark [Wed, 16 Jan 2019 15:55:28 +0000 (15:55 +0000)]
hdl.ast: fix naming of Signal.like() signals when tracer fails.

5 years agoback.rtlil: slightly nicer naming for $next signals. NFC.
whitequark [Wed, 16 Jan 2019 17:20:30 +0000 (17:20 +0000)]
back.rtlil: slightly nicer naming for $next signals. NFC.

5 years agoback.rtlil: rename \sig$next to $next$sig.
whitequark [Wed, 16 Jan 2019 14:51:20 +0000 (14:51 +0000)]
back.rtlil: rename \sig$next to $next$sig.

These used to serve a useful purpose being public, back when the RTLIL
backend was immature. Not anymore; now they merely clutter up views
in gtkwave and so on.

5 years agoTravis: install SymbiYosys and Yices2.
whitequark [Wed, 16 Jan 2019 00:57:09 +0000 (00:57 +0000)]
Travis: install SymbiYosys and Yices2.

In preparation for adding formal tests.

5 years agoUnbreak 655d02d5.
whitequark [Tue, 15 Jan 2019 23:09:10 +0000 (23:09 +0000)]
Unbreak 655d02d5.

5 years agoback.rtlil: Generate $anyconst and $anyseq cells.
William D. Jones [Tue, 15 Jan 2019 21:06:19 +0000 (16:06 -0500)]
back.rtlil: Generate $anyconst and $anyseq cells.

5 years agohdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children.
William D. Jones [Tue, 15 Jan 2019 21:05:25 +0000 (16:05 -0500)]
hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children.

5 years agohdl.ast: Add AnyConst and AnySeq value types.
William D. Jones [Tue, 15 Jan 2019 20:13:47 +0000 (15:13 -0500)]
hdl.ast: Add AnyConst and AnySeq value types.

5 years agoREADME: add LambdaConcept sponsorship
Sebastien Bourdeauducq [Tue, 15 Jan 2019 07:58:38 +0000 (15:58 +0800)]
README: add LambdaConcept sponsorship

5 years agolib.io: pass pin to platform.get_tristate().
whitequark [Mon, 14 Jan 2019 21:39:19 +0000 (21:39 +0000)]
lib.io: pass pin to platform.get_tristate().

5 years agohdl.ir: allow explicitly requesting flattening.
whitequark [Mon, 14 Jan 2019 17:04:23 +0000 (17:04 +0000)]
hdl.ir: allow explicitly requesting flattening.

5 years agolib.io: lower to platform-independent tristate buffer.
whitequark [Mon, 14 Jan 2019 16:50:04 +0000 (16:50 +0000)]
lib.io: lower to platform-independent tristate buffer.

5 years agohdl: make ClockSignal and ResetSignal usable on LHS.
whitequark [Mon, 14 Jan 2019 15:38:16 +0000 (15:38 +0000)]
hdl: make ClockSignal and ResetSignal usable on LHS.

Fixes #8.

5 years agohdl.dsl: cases wider than switch test value are unreachable.
whitequark [Sun, 13 Jan 2019 08:51:49 +0000 (08:51 +0000)]
hdl.dsl: cases wider than switch test value are unreachable.

In 3083c1d6 they were erroneously fixed via truncation.

5 years agohdl.dsl: accept (but warn on) cases wider than switch test value.
whitequark [Sun, 13 Jan 2019 08:46:28 +0000 (08:46 +0000)]
hdl.dsl: accept (but warn on) cases wider than switch test value.

Fixes #13.

5 years agoback.pysim: handle non-driven, non-port signals.
whitequark [Sun, 13 Jan 2019 08:31:38 +0000 (08:31 +0000)]
back.pysim: handle non-driven, non-port signals.

Fixes #20.

5 years agoback.verilog: better error message if Yosys is not found.
whitequark [Sun, 13 Jan 2019 08:10:23 +0000 (08:10 +0000)]
back.verilog: better error message if Yosys is not found.

Fixes #17.

5 years agoback.verilog: remove undriven check.
whitequark [Tue, 8 Jan 2019 20:42:56 +0000 (20:42 +0000)]
back.verilog: remove undriven check.

This check no longer finds bugs and is prone to false positives.
Instead, we should do integration tests on the entire stack, from
fragments to Verilog.

Fixes #23.

5 years agoGive the top level scope a name to fix VCD hierarchy.
Adam Greig [Sun, 6 Jan 2019 00:10:37 +0000 (00:10 +0000)]
Give the top level scope a name to fix VCD hierarchy.

5 years agohdl.ast: allow slicing [n:n] into n-bit value.
whitequark [Wed, 2 Jan 2019 18:14:57 +0000 (18:14 +0000)]
hdl.ast: allow slicing [n:n] into n-bit value.

5 years agoback.rtlil: translate empty slices correctly.
whitequark [Wed, 2 Jan 2019 18:14:29 +0000 (18:14 +0000)]
back.rtlil: translate empty slices correctly.

5 years agoback.rtlil: Generate RTLIL for Assert/Assume statements.
William D. Jones [Tue, 1 Jan 2019 06:31:54 +0000 (01:31 -0500)]
back.rtlil: Generate RTLIL for Assert/Assume statements.

5 years agohdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement...
William D. Jones [Sun, 30 Dec 2018 10:17:39 +0000 (05:17 -0500)]
hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children.

5 years agohdl.dsl: Support Assert and Assume where an Assign can occur.
William D. Jones [Fri, 28 Dec 2018 07:10:15 +0000 (02:10 -0500)]
hdl.dsl: Support Assert and Assume where an Assign can occur.

5 years agohdl.ast: Add Assert and Assign statements.
William D. Jones [Fri, 28 Dec 2018 06:33:19 +0000 (01:33 -0500)]
hdl.ast: Add Assert and Assign statements.

5 years agohdl.ast: experimentally add Value._as_const.
whitequark [Tue, 1 Jan 2019 09:50:39 +0000 (09:50 +0000)]
hdl.ast: experimentally add Value._as_const.

Useful for writing e.g. decoders that accept Cat, etc as argument.

5 years agoback.rtlil: fix typo.
whitequark [Tue, 1 Jan 2019 08:50:28 +0000 (08:50 +0000)]
back.rtlil: fix typo.

5 years agohdl.rec: include record name in error message.
whitequark [Tue, 1 Jan 2019 03:39:12 +0000 (03:39 +0000)]
hdl.rec: include record name in error message.

5 years agohdl.rec: use a helpful error on unknown field reference.
whitequark [Tue, 1 Jan 2019 03:35:34 +0000 (03:35 +0000)]
hdl.rec: use a helpful error on unknown field reference.

5 years agohdl.mem: add DummyPort, for testing and verification.
whitequark [Tue, 1 Jan 2019 03:08:10 +0000 (03:08 +0000)]
hdl.mem: add DummyPort, for testing and verification.

5 years agoback.rtlil: match shape of Array elements to ArrayProxy shape.
whitequark [Mon, 31 Dec 2018 03:43:34 +0000 (03:43 +0000)]
back.rtlil: match shape of Array elements to ArrayProxy shape.

Fixes #15.

5 years agoback.rtlil: fix typo.
whitequark [Mon, 31 Dec 2018 03:37:38 +0000 (03:37 +0000)]
back.rtlil: fix typo.

5 years agolib.cdc: fix tests to actually run.
whitequark [Sat, 29 Dec 2018 15:02:44 +0000 (15:02 +0000)]
lib.cdc: fix tests to actually run.

5 years agoback.pysim: warn if simulation is not run.
whitequark [Sat, 29 Dec 2018 15:02:04 +0000 (15:02 +0000)]
back.pysim: warn if simulation is not run.

This would have prevented 3ea35b85.