cpu-o3,tests: add page boundary access test

The O3 model supports unaligned accesses across page boundaries.
This changeset provides a stress test for the feature.

Other benchmarks exercise it, but their coverage is spotty. This
test does nothing else except poke bytes which straddle page
boundaries.

Change-Id: Ic20c2862bcb7af7be091030c12916ba499db10c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22303
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix missing header in associative set

Add missing intmath header to AssociativeSet, so that isPowerOf2 can
be used.

error: there are no arguments to 'isPowerOf2' that depend on a template
parameter, so a declaration of 'isPowerOf2' must be available

Change-Id: Ib2b194f9e71284ee439786bdb76d99858e57e2f5
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22444
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Fixed pipeline squashes caused by aliased requests

This patch was created by Bihn Pham during his internship at AMD.

This patch fixes a very significant performance bug when using the O3
CPU model and Ruby. The issue was Ruby returned false when it received
a request to the same address that already has an outstanding request or
when the memory is blocked. As a result, O3 unnecessary squashed the
pipeline and re-executed instructions. This fix merges readRequestTable
and writeRequestTable in Sequencer into a single request table that
keeps track of all requests and allows multiple outstanding requests to
the same address. This prevents O3 from squashing the pipeline.

Change-Id: If934d57b4736861e342de0ab18be4feec464273d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21219
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add baremetal.py example script

Change-Id: I7a4818836decbf743f6c9b1f2e5361a43fca2d10
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21799
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: bugfix for partial faults in x86

The c58cb8c9 changeset broke some code related to checking
consistency model guarantees (found in X86 benchmarks).

This changeset adds some documentation to the code and obviates
the problem.

Change-Id: Ied9c6b0b1d237538efe4beb2f97ef76248ce2746
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22283
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

ext: Fix undefined-behavior bug in bitshift

If a small number or zero is passed in, fp64_exp could be very
negative (-1000 for example). The intent of the line is to evaluate to
zero in these cases, but what it actually did was bitshift right by
1000, which is undefined behavior (according to ubsan) that so happens
to result in 0 on GCC/most architectures. This commit changes the code
to check for cases where the bitshift is larger than the width of the
integer.

Change-Id: I8de4bd8ad170f0321d54689460de449b7f8fb60a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21859
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

alpha: Convert htog and gtoh to htole and letoh.

When within the Alpha arch, we know the guest endianness already.

Change-Id: Iee22a33451a06c6e6a5c7d1e8c71f0b00e98ae3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22367
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,sim: Make copyStringArray take an explicit endianness.

Change-Id: I5cf4291b19dd2d2bdbbf145ad8e00994fabf5547
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22366
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

kern: When dumping dmesg, detect the byte order dynamically.

The dmesg dumper has access to the system object and so has access to
the getGuestByteOrder accessor. Use that instead of TheISA to determine
the byte order.

Change-Id: I4df7b1bcd807aaced1d7dc8d2030123e2d4d1d2b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22365
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Use the system and OS to get endianness.

This converts the syscall implementations to either use the
OS::byteOrder constant or, if that's not available, the system's
getGuestByteOrder() accessor, to determine the byte order, instead of
relying on TheISA to provide the correct accessor.

Change-Id: Idf7b02ee8d73990224ceac9a5efaec91a5ebf79f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22364
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Make endianness a property of the OS class syscalls can consume.

That way the syscall implementations won't have to find the right
endianness to use on their own, typically by referring to TheISA.

Change-Id: I186b2f419d5dbee72cc9b5abce7356f3143f0c83
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22363
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Make the virtio devices track endianness explicitly.

These classes now track what endianness they're supposed to use
explicitly, initially set by the getGuestByteOrder accessor on the
system object. In the future, if the endianness depends on the
version of the VirtIO spec as the comment suggest, it will be easier
to dynamically set the endianness in the various structures based on
the version being used,

Since there isn't anything special about the virt IO versions of these
converters other than their types, and since the endianness conversion
infrastructure can be taught how to convert new types, the code was
switched over to using the standard htog and gtoh but with the
explicit byte order provided.

This also gets rid of the final use of TheISA in the dev directory.

Change-Id: I9345e3295eb27fc5eb87e8ce0d8d424ad1e75d2d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22273
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a getGuestByteOrder accessor to the system class.

This goes along with the existing getPageBytes, etc., accessors, and
paves the way for this to be a parameter of the System class.

Change-Id: Ibfe2d591185d23beccdd5bbff1092dc07b1278ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22272
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Update MAINTAINERS file

Add systemc tag and add Bobby as a tests maintainer.

Change-Id: Idc890365387f7e99543067d2e02ce0caadf785df
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22304
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Refactor the CortexA76x1 model for MP support.

This change inverts the relationship between the fast model and gem5
CPUs, and factors out the parts of the CortexA76x1 which are per core
vs. per cluster.

Change-Id: I33eacc2461f08c7fd1784936b230e96c768c0e79
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21501
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Adding support for large BAR

During PCI setup, this patch checks if a Base Address Register (BAR) is
used as a large BAR (64 bits rather than 32), and return proper address
range. The order which updates are done is decided by kernel, so this
patch implements both cases (writing lower or upper bits first).

Bit 2 in a BAR indicates a 64-bit decoder (10X to be more exact, 11X is
reserved).

The addresses in BARAddrs are full addresses and are set to zero for BAR
providing upper 32 bits to avoid conflicts in addr ranges reported.

Change-Id: I93303d36ac83dab9ed6837c81e77c9dfb778f409
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22082
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Name segments after their index

Current loader is performing a linear scan of the section table for
every segment in the elf since it is naming every segment after the
sections it contains. With this patch we are just naming segments
after their index.
This is in any case how they are referenced when a readelf --segments
command is issued on the elf file.

Change-Id: I599400fcdfc0b80ac64632aba36781bd876777f0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21999
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: Fix handling of some mem. order violations

This patch fixes the handling of memory order violations due to snoops
targeting out-of-order loads: the re-execution triggered in these cases
is achieved by raising a ReExec fault, but such a fault was not handled
correctly after the code changes introduced in changeset 46da8fb.

Change-Id: I2abe161a90468412f56cb28dcc92729326cba1cd
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21819
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Timothy Hayes <timothy.hayes@arm.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev: Remove TheISA from ns_gige.cc.

It was not being used there.

Change-Id: Ib39cfb52553e0556f7a6ad616e1029c74fa90e1f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22271
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev: Stop including config/the_isa.hh unnecessarily.

This file was included in a few files which didn't use TheISA.

Change-Id: Ib296b88dc6cfe9d487ee31cf385bb872d2cffaf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22270
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev: Get PageBytes from the system in the ARM generic timer.

These will ultimately by ArmISA::PageBytes, but this is more consistent
with other devices which don't know what ISA they're part of.

Change-Id: Iac13d5010564512207ed009377a771ee5949eff3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22269
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev: Get PageBytes from the system in the ide_disk model.

This avoids having to use TheISA::.

Change-Id: I020860ab343f9b6fafbcb0e23479d0b64f094512
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22268
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev: Remove using namespace std and TheISA from ide_disk.cc.

Neither was necessary since either that namespace wasn't used, or was
used explicitly when referenced.

Change-Id: I96d2791c09250255e7e65d47cbb6f65eb4fcb3ba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22267
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

fastmodel: Helper function to setup FastModels for simulation

This function sets up ARM license, simulation name, and minimum
synchronize latency in FastModels. This function should be called once
per simulation.

Change-Id: Ic3408955aaff9f8b4e2b72d2f2b0da97b41bfc3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22183
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Get rid of using namespace std and TheISA in realview.cc.

Neither was actually used by the nearly empty file.

Change-Id: Ief1b77b18c8c616511bf9870e1667439a42dfcbd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22266
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Remove SINIC_VTOPHYS and related code.

The code in this #ifdef isn't turned on by anything, and either has or
likely will bitrot, especially since there are no tests to even
determine manually if the code they guard works. They are also
preceeded by panics which say that the code they guard is known not to
work now anyway.

This change also gets rid of TheISA in that file since the only reason
it was around was for vtophys in the guarded code.

Change-Id: I59fd8974d0dd3d7ab0d5a8ccfa6a446d2da41eb0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22265
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

alpha: Remove TheISA from the Alpha devices.

These are the from the various bits of the tsunami platform. They
primarily consisted of "using TheISA" which could be replaced with
using AlphaISA or removed altogether (I went with the later), and use
of TheISA:: which I replaced with AlphaISA::.

Change-Id: Ic52577c65241a92a3f1ae318a19431f8faa50a66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22264
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Remove TheISA from x86 devices.

This was really only in the PC platform class.

Change-Id: I5365d965ea335a7c45be9f80706a875b19ed0417
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22263
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Create a helper functions to install firmware images.

The first function handles the repetitive process of creating an
ObjectFile for a particular purpose and checking if that was
successful.
The second conditionally offsets the images in case they were, for
instance, loaded from an ELF file which already had them in the right
place. It offsets them so that their entry point (which will be zero
for raw images) lines up with the appropriate entry address (which will
be at the start of raw images).

This is more correct in more cases, and also removes a lot of
redundancy. There's still a lot of redundancy in the code which sets
up the symbol tables, but there are some irregularities which make that
harder to wrap in a helper function.

Change-Id: I2fee8b2175faff284ff9e007307f7769043497a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21469
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add a repeated value pattern to compressors

The repeated value pattern checks if values are composed of multiple
instances of the same value. If successful, the bits of the repeated
value are included only once in the compressed data.

Change-Id: Ia7045b4e33a91fd8d712fe1ca689f7f8cb4e5feb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21153
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Inform unused bits instead of bytes in compressor pattern

Increase pattern precision by giving the number of unmatched bits
instead of bytes.

Change-Id: I5efbe9c31672cc973b4c89c741cdc8cc28d26285
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21152
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add a masked const value pattern to compressors

The masked pattern compares values to masked const non-dictionary values
to determine whether these match. If successful, the bits that do not
match must be added to the compressed data.

Change-Id: I4c53568694dab916136fe384cb2ee10e554f7136
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21151
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add a masked pattern to compressors

The masked pattern compares masked values to masked dictionary entries
to determine whether these values match. If successful, the bits that
do not match must be added to the compressed data.

Change-Id: I4b1c8feb0faa99576382b54a73a20c353f965d2a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21150
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add an uncompressed pattern to compressors

The uncompressed pattern always stores the original data, and therefore
it is always successful. All of the derived classes of the dictionary
compressor must have this pattern as the last pattern of the pattern
factory.

Change-Id: I2a38fd56630d88ef8b918220dc4c2824a196a8a2
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21149
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Templatize DictionaryCompressor

Templatize DictionaryCompressor so that the dictionary entries' sizes
can be changed.

Change-Id: I3d89e3c692a721cefcd7e3c55d2ccdefa425f614
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21148
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Factor out CPack's dictionary functionality

Factor out dictionary functionality of CPack, so that it can be
used easily for other compressors.

As a side effect, create an addToDictionary function to allow
subclasses to chose how to handle insertion.

Change-Id: I02fae4e98b02db5a40467ec470b71020d5e867cb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21147
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

mem-cache: Use shouldAllocate() instead of CPack's decompress()

Split decompression functionality using the proper function to
determine if a dictionary entry should be allocated after
decompression or not.

Change-Id: I4995304f4c4508c03c9fc1685f04511622969556
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21146
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Limit compression size

Add a threshold so that if the compressed size is greater than it,
the compression is abandoned, and the data is considered uncompressible.

Change-Id: Ic416195b06ec440a40263b75bd0f0383cde2ea6a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21144
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Do not try to compress dataless packets

Fix filling blocks so that packets that do not contain data do not
generate a compression attempt. This can happen, for example, with
invalidation responses, which will trigger a packet data access
assertion.

Change-Id: I2a1e7983657f6e5e770b148ab62c9de9ac3986ac
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22164
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Remove non-source files from fputils

Remove the autoconf-based build system and GNU-style information files
from fputils. After this change, we only keep the files we will need
to integrate into gem5's main source tree.

Change-Id: I2ddf1d07d9cb51bcd91fc63f1ae43c7f46129933
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22163
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem: Fix DRAM controller to operate on its own address space

Typically, a memory controller is assigned an address range of the
form [start, end). This address range might be interleaved and
therefore only a non-continuous subset of the addresses in the address
range is handed by this controller.

Prior to this patch, the DRAM controller was unaware of the
interleaving and as a result the address range could affect the
mapping of addresses to DRAM ranks, rows and columns. This patch
changes the DRAM controller, to transform the input address to a
continuous range of the form [0, size). As a result the DRAM
controller always operates on a dense and continuous address range
regardlesss of the system configuration.

Change-Id: I7d273a630928421d1854658c9bb0ab34e9360851
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19328
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Avoid promotion of incompatible deferred targets

Often a request that hits on an MSHR has to be deferred as it can't be
serviced by the current response.

For example, a request that requires writable has to be deferred when
the response is expected to bring in a read-only copy of the
block. However, there are cases where the response, although not
expected to do so, brings a writable copy and as a result we also
service deferred targets. In such cases, we promote deferred targets
up until the first that can't be serviced by the current response
(e.g., cache maintainance operation). If the first deferred target is
incompatible we don't promote any targets at all.

Change-Id: Ib3e13be51120b7c0f0053b83b76bde03e1b7dd4e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22127
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix MSHR whole line write tracking

The MSHR keeps track of outstanding writes and services them as a
whole line write whenever possible. To do this the outstanding writes
have to be compatible (e.g., not strictly ordered). Prior to this
change, due to this tracking mechanism, the MSHR would not service a
WriteLineReq with flags that do not allow merging as a full line write
even if it was the first target triggering an assertion. This
changeset fixes this bug.

Change-Id: I2cbf5ece0c108c1fcfe6855e8f194408d5ab8ce2
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22126
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Update HPI to use ArmDTB and ArmITB.

Change-Id: I67693e9d79e89f151e30c585ad565deac53c77c1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22203
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Fix undefined BaseCPU

When using NULL ISA BaseCPU is undefined, and therefore the
isinstance call generates a NameError.

Change-Id: Ia4582606b775cdb20829966f8e312a333a55b6f3
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21959
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests, base: Fixed incorrect implementation of StrTest.ToLower test.

Change-Id: I96672052f8c9da9d4f61ff0e8eed324032b1afac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22123
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Update fputils to rev 0721843

This patch updates fputils to the latest revision (0721843) from the
upstream repository (github.com/andysan/fputils). This effectively
only updates the license of the library to match gem5's 3-clause BSD
license.

Change-Id: I46d8a5dfac2f4a95e66ee82a15288ac424d7df90
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22125
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips,riscv: Get rid of some Alpha cruft in these System classes.

The consolePanicEvent pointer and addConsoleFuncEvent template were
inherited from Alpha and were not used (and probably make no sense) for
MIPS or RISCV which (to my knowledge) don't have the idea of a
"console" binary.

Change-Id: I109b866a65f69c7334062f7304c7b18acc51d99d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21782
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Get rid of the nextInstEventCount method.

This was only used by the KVM CPU, and it has access to all it needs to
figure out that value locally without requiring all the ThreadContexts
to implement an equivalent function.

Change-Id: I17a14ce669db2519edf129db761ebd8dc3bd4129
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22114
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Get rid of the serviceInstCountEvents method.

This was useful when transitioning away from the CPU based
comInstEventQueue, but now that objects backing the ThreadContexts have
access to the underlying comInstEventQueue and can manipulate it
directly, they don't need to do so through a generic interface.

Getting rid of this function narrows and simplifies the interface.

Change-Id: I202d466d266551675ef6792d38c658d8a8f1cb8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22113
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Use getCurrentInstCount for totalInsts().

This had been using a custom totalInsts method on the iris
ThreadContext, but since that's equivalent to what the totalInsts
method does only through a different mechanism, we can
drop that and use getCurrentInstCount instead.

Change-Id: I058fec13e81f28285281e136635d53a2e849cb47
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22112
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Implement getCurrentInstCount.

This uses the step counter the iris API provides.

Change-Id: Ic916888fa256d0aa65042d3e6695d9bf4ba32c86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22111
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Switch off of the CPU's comInstEventQueue.

This switches to letting the ThreadContexts use a thread based/local
comInstEventQueue instead of falling back to the CPU's array. Because
the implementation is no longer shared and it's not given where the
comInstEventQueue (or other implementation) should be accessed, the
default implementation has been removed.

Also, because nobody is using the CPU's array of event queues, those
have been removed.

Change-Id: I515e6e00a2174067a928c33ef832bc5c840bdf7f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22110
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Access inst events through ThreadContext instead of the CPU.

Also delete the CPU interface.

Change-Id: I62a6b0a9a303d672f4083bdedf393f9f6d07331f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22109
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Delegate comInstEventQueue methods to the ThreadContexts.

These then just use the comInstEventQueue array from the CPU, but soon
they will actually be self contained and allow the thread context to
use whatever mechanism it wants.

Also, now that the thread contexts need to exist before instruction
count based events can be scheduled, setting up max instruction based
events needs to happen in init after the CPU subclasses have had a
chance to set up the threadContexts vector.

Change-Id: I34bb401633d277a60be74e30d5a478a149b972ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22108
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Make accesses to comInstEventQueue indirect through methods.

This lets us move the event queue itself around, or change how those
services are provided.

Change-Id: Ie36665b353cf9788968f253cf281a854a6eff4f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22107
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,sim: Delegate PCEvent scheduling from Systems to ThreadContexts.

The System keeps track of what events are live so new ThreadContexts
can have the same set of events as the other ThreadContexts.

Change-Id: Id22bfa0af7592a43d97be1564ca067b08ac1de7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22106
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Make the ThreadContext a PCEventScope.

Both the thread and system's PCEventQueue are checked when appropriate.

Change-Id: I16c371339c91a37b5641860d974e546a30e23e13
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22105
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,sim: Get rid of a bunch of conditional compilation for PCEvents.

These can now be built without referring to anything in ThreadContext
and so can be built even with the NULL ISA. This means the pcEventQueue
can be unconditionally built into the System class. Even though the
pcEventQueue is going away, this still makes it possible for System to
be a PCEventScope unconditionally.

Change-Id: Ia342bb7972b1b5ce95033176d72af4bfa343560f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22104
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Don't print the CPU name when a (Break|Panic)PCEvent happens.

This requires reaching into the threadcontext to access the CPU
pointer, and also isn't all that useful since it's more important what
event happened, not what CPU happened to be running the code at that
time.

Change-Id: I368707c804dff9bd349f3261bdcd08be55c5d04a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22103
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Pass the address to check into the PCEventQueue service method.

This prevents having to access it from within the ThreadContext.

Change-Id: I34f5815a11201b8fc41871c18bdbbcd0f40305cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22102
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Make the System object a PCEventScope.

This abstracts away the raw PCEventQueue managed by the System.

Change-Id: I04d773e6be90a891884a76841f15c3eecd5796ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Stop checking for PC changes when servicing a PCEventQueue.

First of all, this would arbitrarily skip events based on when they
were encountered in the queue. Second, this is one of the three places
where the ThreadContext is actually accessed in pc_event.cc. By
removing this and the other uses, this file can be included even when
using the NULL ISA, and a lot of #ifdefs can be removed.

Change-Id: If81f5e9ff9d3f9833145fec0b6062b4bda8d2e47
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22100
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Create a PCEventScope class to abstract the scope of PCEvents.

This abstraction will allow scheduling PCEvents for a particular
ThreadContext, all contexts on a CPU, all contexts in a system, etc.,
and delegates scheduling and removing events to each particular scope.

Right now the PCEventQueue is the only implementor of the PCEventSCope
interface.

Change-Id: I8fb62931511136229915c2e19d36aae7ffdec9df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22099
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Added GTests for base/str.cc

Adding these tests supercedes the unittest/strnumtest.cc
and unittest/tokentest.cc tests. They have thereby been removed.

Function "to_number" in base/str.hh previously failed to cast negative
float/double numbers. This was due to the use of
std::numeric_limits<T>::min() instead of std::numeric_limits<T>::lowest()
to determine whether a string-to-float/double conversion was
"Out of range". Tests "StrTest.ToNumberFloatNegative" and
"StrTest.ToNumberDoubleNegative" exposed this bug. It has been fixed.

Methods "split_first" and "split_last" in base/str.hh have had their
documentation updated to remove abiguity in their functionality.

Change-Id: I16e0fe40d884e22dd010db4045857eb6e7f33d4a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22084
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu, sim-se: don't wake up threads that are awake in futex

FutexMap::wakeup is called when the futex(TGT_FUTEX_WAKE syscall is done.

FutexMap maintains a list of sleeping threads for each futex address
added on FutexMap::suspend, and entries are removed from the list
at FutexMap::wakeup.

The problem is that this system was not taking into account that threads
can be woken up by memory accesses to locked addresses via the path:

SimpleThread::activate
BaseSimpleCPU::wakeup
AbstractMemory::checkLockedAddrList
AbstractMemory::access
DRAMCtrl::recvAtomic
CoherentXBar::recvAtomicBackdoor
SimpleExecContext::writeMem

which happens on trivial pthread examples on ARM at least. The instruction
that locked memory in those test cases was LDAXR.

This could lead futex(TGT_FUTEX_WAKE to awake a thread that is already
awake but is first on the sleeping thread list, instead of a sleeping one,
which can lead all threads to incorrectly sleep and in turn to
"simulate() limit reached".

To implement this, ThreadContext::activate return now returns a boolean
that indicates if the state changed. suspend and halt are also modified
to also return a boolean in the same case for symmetry, although this is
not strictly necessary for the current patch.

Change-Id: Ia6b4d3e6148c64721d810b8f1fffaa208a394b06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21606
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: fix futexFunc TGT_FUTEX_WAIT always selects bitset

Change-Id: I3e2bd1dd34d7cc00b2685547ab74b56bd8126128
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21605
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Add string constructors which delegate to const char * ones.

Change-Id: I22d88111409fc477c135b15c8f898adad4f6d4ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21502
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

cpu: Apply the ARM TLB rework to the O3 checker CPU.

The TLBs now create the stage 2 MMUs as children, and since those are
specialized for instruction and data, the CPU needs to use ArmITB or
ArmDTB instead of ArmTLB which is the base class without an MMU. This
was changed for the BaseCPU and SimpleCPU checker already, but the TLBs
are added in the O3 checker CPU as well.

Change-Id: I498f247f376c8721fb70ce26c0f1b0815b12fe2d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22039
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Drop sysctl support if built against glibc

Since glibc 2.30 the sysctl() function has been declared deprecated and
it will be deleted in future versions. This patch removes the support
for the sysctl system call in SE mode (which is currently serviced
calling the sysctl() function) if gem5 is built against glibc, keeping
it with other libc implementations, as a temporary measure to prevent
the generation of a compilation error. Note that this system call in
gem5 is only supported for the arm/freebsd architecture.

Change-Id: Ie5fcb983d15c0a27c7820d24250d7ae5dbe12355
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21519
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Clean setupBootLoader signature

This is because the bus parameter is not used anymore

Change-Id: I27aa8cc064904a6e3e0376f61eb7db74ea1a4d6c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22002
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

configs: Do not assume bootmem is a System child

As far as I can see bootmem is used in Arm systems only.

With

https://gem5-review.googlesource.com/c/public/gem5/+/21604

bootmem has been moved from system to system.realview.
This patch fix things by removing the assumption that the bootmem
SimObject lives under the system.
It is now trying to getattr a reference of the bootmem.
It is the ISA specific system builder's duty to bind the bootmem
reference (_bootmem) to the real bootmem object

Change-Id: I1e7405b5cb186de13c44bfd93fb4c8a1a5447f24
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22001
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm, configs: Using _on_chip_memory for on chip memory

This patch is pulling the on-chip memory outside of the on_chip_devices
list.
The external interface will be more or less the same: configuration
scripts will still use the attachOnChipIO method; a new kw argument has
been added in order to store mem_ports.

We want to provide to on-chip memory the same mechanism used when
collecting on-chip dma ports. This is needed when using Ruby, since
we need to pass a non None mem_ports to prevent the bootmem to be
wired to the bus.

Change-Id: Ifc519c3072dc5de1530772c70c80dc2094e2c54c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22000
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Apply the ARM TLB rework to the checker CPU.

The TLBs now create the stage 2 MMUs as children, and since those are
specialized for instruction and data, the CPU needs to use ArmITB or
ArmDTB instead of ArmTLB which is the base class without an MMU. This
was changed for the BaseCPU already, but the TLBs are added in the
checker CPU as well.

Change-Id: Ide8ce950622b40f69c37bbe2ea0d22295b76d7a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21979
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Add Giacomo Travaglini as an Arm maintainer

I have been delegating a lot of changes to Giacomo T for a long time,
making him a de facto Arm co-maintainer. Make this official by adding
him to the list of maintainers.

Change-Id: I69c53316e2fc6ca162d07ac2d167ac2ae2b6bbee
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21899
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs.

This regularizes the TLB setup in the CPU so that ARM is no longer a
special case with extra objects.

Change-Id: I739b82578ff74f8f9777cd7e34cd5227b47b186c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21842
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch: Remove the "interrupts.hh" switching header file.

That switching header is no longer necessary since everything outside
of the ISA can use the BaseInterrupts class.

Change-Id: Ie3ed45c38fec24234ff51fb05ba94f6f3cd02afd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20832
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch: Make a base class for Interrupts.

That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.

Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Check for gem5 extensions in GicV2

Using GicV2 without setting the gem5_extensions parameter in a
config  with more than 8 is not allowed to prevent overflow of
the 8-bit mask.

Change-Id: I780c6985e8f44ed780b4f74f9a27805124e23a7b
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19288
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Added GTests for base/bitfield.hh

In addition to the tests, a more detailed explanation of how
"insertBits(..)" functions has been included in its doxygen
documentation. The previous explanation was ambigious and led to
confusion.

Change-Id: I2ae8608733ebaa8f8f726cbb3a2cd8639b69c6b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21700
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch: Get rid of the unused GenericTLB.

Nothing is using it, and it's actually not use*able* at the moment
because it doesn't have implementations for all the pure virtual
methods that exist in the BaseTLB class.

Change-Id: I03d47c2e116f354c7247a2fa19a9f33dfe4c5eec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21841
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Turn the stage 2 ARM MMUs from params to children.

These aren't referred to in the C++, so there's no reason for them to
be parameters. By making them children, they can still be modified,
replaced wholesale, or even replaced by an entirely different object
to, for instance, mask them when they're not needed.

Change-Id: Ic7f144a3cd3d1fca12fec220918aa72af885f61c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21839
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Turn the local APIC Interrupts class into a SimObject.

It will no longer be a PioDevice or a ClockedObject, but will carry
forward the little bits and pieces of those classes that it was using.
Those are a PIO port for memory mapped register accesses, and a clock
domain parameter for setting the apic tick frequency.

This brings the x86 Interrupts class in line with the Interrupts of the
other ISAs so that they can inherit from a standard base class.

Change-Id: I6b25fa21911b39a756e0cf9408c5489a81d6ca56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20829
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Added GTests for base/atomicio.cc

Change-Id: I586a06c70f4e7331b4a31208ef7831e8473509c5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21699
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add classes that encapsulate a channel address

There are cases where the memory system needs to reason about
channel-local addresses. These are currently represented using the
Addr and AddrRange classes. This is not ideal since it doesn't provide
any type safety when working with global addresses and channel-local
addresses. This is particularly problematic when porting existing
components to work in multi-channel configurations.

This changeset introduces the new ChannelAddr and ChannelAddrRange
classes. These classes encapsulate channel-local addresses in a
contiguous address space. These can, for example, be used in a memory
controller to represent a flat address space when calculating timings
or in a sectored cache.

Change-Id: I45d4061ebc8507a10d0a4577b28796dc5ec7a469
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21600
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Delete the MessageReq and MessageResp memory commands.

Now that Message*Port is gone, there are no users of these two memory
commands. They can now be deleted, simplifying the memory system
slightly.

Change-Id: If157dade4a3fb2610756c2ee81dc0c3fac670a26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20824
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Don't force the ArmISA::TLB in vtophys.cc.

The only reason the TLB pointer is being cast to an ArmISA::TLB is so
that it can call a version of translateFunctional which takes more
arguments, when the standard version of translateFunctional just calls
that underlying function with the same arguments.

Change-Id: I3ffd3a8ecc2dda91ddca77f516e2b2ac7313a227
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21840
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

cpu: Clean up some style issues in pc_event.(hh|cc).

The record_t typedef isn't all that helpful, and is also not consistent
with gem5 style. The map_t style is more useful but is also not
compliant. This change eliminates the first typedef and replaces the
second with a type called Map.

There are some other small style fixups added in as well, like making
the member variable pc_map pcMap.

Change-Id: I8ffea529004fd6d5b42fdc60250804e2e4987e88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21781
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Get rid of load count based events.

This was initially added in 2003 and only supported in the simple CPUs.
It's oddly specific since there are no other similar event queues for,
for instance, stores, branches, system calls, etc.

Given that this seems like a historical oddity which is only partially
supported and would be very hard to support on more diverse CPU types
like KVM or fast model which don't generally have hooks for counts of
specific instruction types.

Change-Id: I29209b7ffcf896cf424b71545c9c7546f439e2b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21780
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add addIntlvBits to AddrRange

This method performs the opposite operation of removeIntlvBits and can
be used to transform a channel-local address to a global PA.

Change-Id: I2fab587d7c094597e52422305775ac7f31efba34
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21599
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Using scoped string in DPRINTFNR

We would otherwise need to add a using namespace std wherever we
use DPRINTFNR.

Change-Id: I30bf9ba474408133abded66141f6dc96dfdba8d6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21821
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Fix gem5.fast compilation

Change-Id: I86c83e8622ae5a88ff802ccb1cb919194c1251ef
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21820
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,base,sim: Move Process loader hooks into the Process class.

This code was originally in the ObjectFile class, but not all object
files will become Processes. All Processes will ultimately come from
ObjectFiles though, so it makes more sense to put that class there.

Change-Id: Ie73e4cdecbb51ce53d24cf68911a6cfc0685d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21468
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Use a std::function to handle MSI completion.

This removes the recvResponse callback from the IntMasterPort, and
makes it easier to handle the default case where we just need to clean
up the Packet.

Change-Id: I8bcbfee0aaf68b12310d773f925c399fc87ea65d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20828
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

arch,base: Restructure the object file loaders.

This change creates a distinction between object files which hold
executable code, and flat files which don't. The first type of files
have entry points, symbols, etc., while the others are just blobs which
can be shoved into memory. Rather than have those aspects but stub
them out, this change creates a new base class which simply doesn't
have them.

This change also restructures the ELF loader since it's main function
was quite long and doing multiple jobs.

It stops passing the architecture and operating system to the
ObjectFile constructor, since those might not be known at the very top
of the constructor. Instead, those default to Uknown*, and then are
filled in in the constructor body if appropriate. This removes a lot
of plumbing that was hard to actually use in practice.

It also introduces a mechanism to collect generic object file formats
so that they can be tried one by one by the general createObjectFile
function, rather than listing them all there one by one. It's unlikely
that new types of object files will need to be added in a modular way
without being able to modify the core loader code, but it's cleaner to
have that abstraction and modularization like is already there for
process loaders.

Finally, to make it possible to share the code which handles zipped
files for both true object files and also files which will be loaded
into memory but are just blobs, that mechanism is pulled out into a
new class called ImageFileData. It holds a collection of segments
which are set up by the object file and may refer to regions of the
original file, buffers maintained elsewhere, or even nothing to support
bss-es. shared_ptr is used to make it easier to keep track of that
information without having to do so explicitly or worry about deleting
a buffer before everyone was done using it.

Change-Id: I92890266f2ba0a703803cccad675a3ab41f2c4af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21467
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Delete the unused sched_break_pc(_sys) functions.

Change-Id: I2adae2858897e665fd28cfe9de3fdcf95ffc2a2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21779
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Make LFENCE a serializing instruction

According to the Intel SDM, no instruction following an LFENCE can begin
execution until after the LFENCE has executed. (This is
less strict than an actual serializing instruction, such as CPUID.)

Serializing instructions (per intel SDM Volume 3A Chapter 8.3) ensure
that no future instruction is fetched until after the serializing
instruction is completed.

By contrast, LFENCE (and other memory-ordering instructions) allows
future instructions to have been fetched; it just prohibits them from
being executed.

Change-Id: If89fcb552192326ab69a581f57d71c95cf5d90e7
Signed-off-by: Isaac Richter <isaac.richter@rochester.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10321
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Carve out a portion of VExpress_GEM5 for the bootloader

This patch is carving out a portion of VExpress_GEM5 memory for the
bootloader. Prior to this patch this was only happening
conditionally/dynamically via the setupBootLoader call.  With this patch
the region is always present and the setupBootLoader doesn't instantiate
memory, it is only setting up some bootloader parameters.

Change-Id: Iaa5cdf471b14e8faa37353a25631bf7c6fc64afc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21604
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add simpleSystem helper to generate devices.SimpleSystem

This patch will make it possible to generate a SimpleSystem inheriting
from a configurable base class. More practically it will be possible to
inherit from a baremetal System (ArmSystem) rather than from a
LinuxArmSystem

Change-Id: I11553ae8045519059e159c555c6c9141bb4519b7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21603
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim,cpu: Get rid of the unused instEventQueue.

This queue was set up to allow triggering events based on the total
number of instructions executed at the system level, and was added in
a change which added a number of things to support McPAT. No code
checked into gem5 actually schedules an event on that queue, and no
code in McPAT (which seems to have gone dormant) either downloadable
from github or found in ext modify gem5 in a way that makes it use
the instEventQueue.

Also, the KVM CPU does not interact with the instEventQueue correctly.
While it does check the per-thread instruction event queue when
deciding how long to run, it does not check the instEventQueue. It will
poke it to run events when it stops for other reasons, but it may (and
likely will) have run beyond the point where it was supposed to stop.

Since this queue doesn't seem to actually be used for anything, isn't
being used properly in all cases anyway, and adds overhead to all the
CPU models, this change eliminates it.

Change-Id: I0e126df14788c37a6d58ca9e1bb2686b70e60d88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21783
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>