i965/fs: Fix gl_SampleID for 2x MSAA and SIMD16 mode.

We might be able to do this without an extra program key field, but this
is non-invasive and fixes the bug, for now.

This fixes the following Piglit tests on Broadwell:
- ARB_sample_shading/builtin-gl-sample-id 2
- ARB_sample_shading/builtin-gl-sample-position 2
- EXT_framebuffer_multisample/multisample-blit 2 color
- EXT_framebuffer_multisample/multisample-blit 2 color linear
- EXT_framebuffer_multisample/multisample-blit 2 depth
- EXT_framebuffer_multisample/no-color 2 depth combined
- EXT_framebuffer_multisample/no-color 2 depth separate
- EXT_framebuffer_multisample/no-color 2 depth single
- EXT_framebuffer_multisample/no-color 2 depth-computed combined
- EXT_framebuffer_multisample/no-color 2 depth-computed separate
- EXT_framebuffer_multisample/no-color 2 depth-computed single
- EXT_framebuffer_multisample/unaligned-blit 2 color msaa
- EXT_framebuffer_multisample/unaligned-blit 2 depth msaa

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80991
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>

i965: Add missing persample_shading field to brw_wm_debug_recompile.

Otherwise, the performance warning for shader recompiles will just say
"something else".

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965/disasm: Don't disassemble the URB complete field on Broadwell.

It doesn't exist, so attempting to read it will trigger generation
assertions in the brw_inst API.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Disable hex offset printing in disassembly.

Printing the hex offsets makes it basically impossible to diff assembly:
if you add even a single instruction, the entire shader shows up as a
difference.  So, every time I want to compare assembly, I have to strip
this out.

The hex offsets might be useful when debugging compaction, or when
inspecting the program cache buffer.  Since it's occasionally useful,
but uncommon, this patch disables it by default, but makes it easy to
re-enable it temporarily when the need arises.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Use foreach_inst_in_block a couple more places.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Replace cfg instances with calls to calculate_cfg().

Avoids regenerating it unnecessarily.

Every program in shader-db improved, none by an amount less than a 1/3
reduction. One Dota2 shader decreased from 62 -> 24.

cfg calculations:     429492 -> 193197 (-55.02%)

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/cfg: Add a foreach_block_and_inst macro.

Will let us abstract how the instructions are stored.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Add cfg to backend_visitor.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

radeonsi/compute: Add support scratch buffer support v2

The scratch buffer will be used for private memory and also register
spilling.

v2:
  - Code cleanups

radeonsi/compute: Bump number of user sgprs for LLVM 3.5

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

winsys/radeon:  Query the kernel for the number of SEs and SHs per SE

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi/compute: Share COMPUTE_DBG macro with r600g

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: Read rodata from ELF and append it to the end of shaders

The is used for programs that have arrays of constants that
are accessed using dynamic indices.  The shader will compute
the base address of the constants and then access them using
SMRD instructions.

glsl: Fix bad indentation

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Silence unused parameter warning

brw_fs_visitor.cpp:2400:1: warning: unused parameter 'ir' [-Wunused-parameter]

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Silence 'comparison is always true' warning

The parameter is an int16_t, and we're check that it's value will fit in
16-bits.  Yes, the value that is stored in 16-bits will surely fit in
16-bits.

brw_inst.h: In function 'brw_inst_set_gen6_jump_count':
brw_inst.h:321:66: warning: comparison is always true due to limited range of data type [-Wtype-limits]
brw_inst.h:321:66: warning: comparison is always true due to limited range of data type [-Wtype-limits]

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Silence many unused parameter warnings

brw_inst.h: In function 'brw_inst_set_src1_vstride':
brw_inst.h:118:76: warning: unused parameter 'brw' [-Wunused-parameter]

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

configure.ac: Add LLVM patch version to error message.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

main/format_pack: Fix a wrong datatype in pack_ubyte_R8G8_UNORM

Before it was only storing one of the color components due to truncation.
With this patch it now properly stores all of them.

Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>

docs: Import 10.2.4 release notes

And add a news item.

Add support for RGBA8 and RGBX8 textures in intel_texsubimage_tiled_memcpy

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>

i965: Improve debug output in intelTexImage and intelTexSubimage

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>

radeonsi: only update vertex buffers when they need updating

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: remove nr_vertex_buffers

Unused.

Also inline util_set_vertex_buffers_count and simplify it.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: move vertex buffer descriptors from IB to memory

This removes the intermediate storage (pm4 state) and generates descriptors
directly in a staging buffer.

It also reduces the number of flushes, because the descriptors no longer
take CS space.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: add support for fine-grained sampler view updates

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: move si_set_sampler_views to si_descriptors.c

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: move sampler descriptors from IB to memory

Sampler descriptors are now represented by si_descriptors.
This also adds support for fine-grained sampler state updates and
the border color update is now isolated in a separate function.

Border colors have been broken if texturing from multiple shader stages is
used. This patch doesn't change that.

BTW, blitting already makes use of fine-grained state updates.
u_blitter uses 2 textures at most, so we only have to save 2.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: implement ARB_draw_indirect

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: don't add info->start to the index buffer offset

info->start will be invalid once info->indirect isn't NULL, so it shouldn't
be added to ib.offset.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: use an SGPR instead of VGT_INDX_OFFSET

The draw indirect packets cannot set VGT_INDX_OFFSET, they can only set user
data SGPRs. This is the only way to support start/index_bias with indirect
drawing.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: assume LLVM 3.4.2 is always present

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

configure.ac: require LLVM 3.4.2 for radeon

Needed by ARB_draw_indirect.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

st/mesa,gallium: add a workaround for Unigine Heaven 4.0 and Valley 1.0

Most (all?) Unigine shaders fail to compile without this if sample shading
is advertised. This is, of course, Unigine developers' fault.

Reviewed-by: Brian Paul <brianp@vmware.com>

glsl: add a mechanism to allow #extension directives in the middle of shaders

This is needed to make Unigine Heaven 4.0 and Unigine Valley 1.0 work
with sample shading.

Also, if this is disabled, the error message at least makes sense now.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

r600g: Implement GL_ARB_texture_gather

Only supported on evergreen and later. Currently limited
to single component textures as the hardware GATHER4
instruction ignores texture swizzles.

Piglit quick run passes on radeon 6670 with all
applicable textureGather tests, no regressions.

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

i965: Fix z_offset computation in intel_miptree_unmap_depthstencil()

The bug is triggered by using glTexSubImage2d() with GL_DEPTH_STENCIL
as base internal format and non-zero x, y offsets. Currently x, y
offsets are ignored while updating the texture image.

Fixes Khronos GLES3 CTS tests:
npot_tex_sub_image_2d
npot_tex_sub_image_3d
npot_pbo_tex_sub_image_2d
npot_pbo_tex_sub_image_2d

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

Revert "i965: Extend compute-to-mrf pass to understand blocks of MOVs"

This reverts commit bbefb15e01e1c16af69646898918982ae00f8c92.
Fixes the 11 regressions caused in framebuffer_blit tests in
Khronos GLES3 CTS tests:

Original patch reduced the instruction count but had no performance
benefits. So, it's safe to revert it without causing any performance
regressions.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Acked-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i915: Fix up intelInitScreen2 for DRI3

Commit 442442026eb updated both i915 and i965 for DRI3 support,
but one check in intelInitScreen2 was missed for i915 causing crashes
when trying to use i915 with DRI3.

So fix that up.

Reported-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
References: https://bugzilla.redhat.com/show_bug.cgi?id=1115323
References: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=754297
Tested-by: František Zatloukal <Zatloukal.Frantisek@gmail.com>
Tested-by: Dirk Griesbach <spamthis@freenet.de>
Signed-off-by: Adel Gadllah <adel.gadllah@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>

mesa: Fix regression introduced by commit "mesa: fix packing of float texels to GL_SHORT/GL_BYTE".

This commit "mesa: fix packing of float texels to GL_SHORT/GL_BYTE" replaced *_TO_BYTE to *_TO_BYTE_TEX because *_TO_FLOAT_TEX are used to unpack the texels to floats.
In this case *_TO_FLOATZ in function extract_float_rgba also should be replaced to *_TO_FLOAT_TEX. Underline that these macros automatically preserve zero when converting.

The regression was observed on 3 oglconform tests:
    snorm-textures basic.getTexImage
    snorm-textures advanced.mipmap.manual.getTex
    snorm-textures advanced.mipmap.upload.getTex

Signed-off-by: Pavel Popov <pavel.e.popov@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

nv50: fix build failure on m68k due to invalid struct alignment assumptions

Make alignment assumptions explicit by inserting correct padding with
unknown struct members.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

clover: Call end_query before getting timestamp result v2

v2:
  - Move the end_query() call into the timestamp constructor.
  - Still pass false as the wait parameter to get_query_result().

Reviewed-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
CC: "10.2" <mesa-stable@lists.freedesktop.org>

glsl: handle a switch where default is in the middle of cases

This fixes following tests in es3conform:

   shaders.switch.default_not_last_dynamic_vertex
   shaders.switch.default_not_last_dynamic_fragment

and makes following tests in Piglit pass:

   glsl-1.30/execution/switch/fs-default-notlast-fallthrough
   glsl-1.30/execution/switch/fs-default_notlast

No Piglit regressions.

v2: take away unnecessary ir_if, just use conditional assignment
v3: use foreach_in_list instead of foreach_list

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v2)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v3)

glsl: Make the tree rebalancer use vector_elements, not components().

components() includes matrix columns, so if this code encountered a
matrix, it would ask for something like a vec9 or vec16.  This is
clearly not what you want.

Earlier code now prevents this from seeing matrices, but we should still
use vector_elements, for clarity.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Guard against error_type in the tree rebalancer.

This helped me track down the bug fixed in the previous commit.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Make the tree rebalancer bail on matrix operands.

It doesn't handle things like (vector * matrix) correctly, and
apparently Matt's intention was to bail.

Fixes shader compilation in Natural Selection 2.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

Revert "i965: Implement GL_PRIMITIVES_GENERATED with non-zero streams."

This reverts commit 3178d2474ae5bdd1102fb3d76a60d1d63c961ff5.

This caused GPU hangs on Ivybridge for some users and huge (80%)
performance regressions across the board on multiple platforms.

We need to find a better solution.  I've made several attempts, but none
of them have worked yet.  In the meantime, we should revert this.

Reverting it breaks GL_PRIMITIVES_GENERATED for non-zero streams, but
that's okay, since we don't expose GL_ARB_gpu_shader5 yet.

Fixes Piglit's EXT_transform_feedback/generatemipmap prims_generated
test case on Haswell.

ilo: add some missing formats

Map more pipe formats to hardware formats.  Enable more VB formats on Haswell.

ilo: update and tailor the surface format table

Recreate the table from scratch with the help of a pdf-table-to-csv converter.
Switch to a form that is more suitable for ilo.

i965: Don't copy propagate abs into Broadwell logic instructions.

It's not clear what abs on logical instructions means on Broadwell, and
it doesn't appear to do anything sensible.

Fixes 270 Piglit tests (the bitand/bitor/bitxor tests with abs).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81157
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>

i965/fs: Use WE_all for gl_SampleID header register munging.

This code should execute without regard to the currently executing
channels.  Asking for gl_SampleID inside control flow might break in
strange ways.  It appears to break even at the top of the program in
SIMD16 mode occasionally as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: mesa-stable@lists.freedesktop.org

i965/fs: Set force_uncompressed and force_sechalf on samplepos setup.

gen8_fs_generator uses these to decide whether to set the execution size
to 8 or 16, so we incorrectly made both of these MOVs the full width in
SIMD16 shaders.  (It happened to work out on Gen4-7.)

Setting them should also help inform optimization passes what's really
going on, which could help avoid bugs.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: mesa-stable@lists.freedesktop.org

i965: Set execution size to 8 for instructions with force_sechalf set.

Both inst->force_uncompressed and inst->force_sechalf mean that the
generated instruction should be uncompressed and have an execution size
of 8.  We don't require the visitor to set both flags - setting
inst->force_sechalf by itself is supposed to be enough.

On Gen4-7, guess_execution_size() demoted instructions to 8-wide based
on the default compression state.  On Gen8+, we instead set a default
execution size, which worked great...except that we forgot to check
inst->force_sechalf when deciding whether to use 8 or 16.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: mesa-stable@lists.freedesktop.org

nvc0: fix translate path for PRIM_RESTART_WITH_DRAW_ARRAYS

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: add support for indirect drawing

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nouveau: check if a fence has already been signalled

nouveau_fence_update does real work unconditionally. Avoid doing that if
the fence we're checking on has already been signalled.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: Don't declare variables in for-loop declaration.

Reported-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

exec_list: Make various places use the new length() method.

Instead of hand-rolling it.

v2 [mattst88]: Rename get_size to length. Expand comment in ir_reader.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> [v1]
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Connor Abbott <connor.abbott@intel.com>

exec_list: Add a function to give the length of a list.

v2 [mattst88]: Remove trailing whitespace. Rename get_size to length.
               Mark as const.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> [v1]
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Connor Abbott <connor.abbott@intel.com>

exec_list: Add a prepend function.

This complements the existing append function. It's implemented in a
rather simple way right now; it could be changed if performance is a
concern.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Connor Abbott <connor.abbott@intel.com>

mesa: Don't allow GL_TEXTURE_{LUMINANCE,INTENSITY}_* queries outside compat profile

There are no queries for GL_TEXTURE_LUMINANCE_SIZE,
GL_TEXTURE_INTENSITY_SIZE, GL_TEXTURE_LUMINANCE_TYPE, or
GL_TEXTURE_INTENSITY_TYPE in any version of OpenGL ES or desktop OpenGL
core profile.

NOTE: Without changes to piglit, this regresses
required-sized-texture-formats.

v2: Rebase on different initial change.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: "10.2 <mesa-stable@lists.freedesktop.org>

mesa: Don't allow GL_TEXTURE_BORDER queries outside compat profile

There are no texture borders in any version of OpenGL ES or desktop
OpenGL core profile.

Fixes piglit's gl-3.2-texture-border-deprecated.

v2: Rebase on different initial change.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: "10.2 <mesa-stable@lists.freedesktop.org>

mesa: Handle uninitialized textures like other textures in get_tex_level_parameter_image

Instead of catching the special case early, handle it by constructing a
fake gl_texture_image that will cause the values required by the OpenGL
4.0 spec to be returned.

Previously, calling

    glGenTextures(1, &t);
    glBindTexture(GL_TEXTURE_2D, t);
    glGetTexLevelParameteriv(GL_TEXTURE_2D, 0, 0xDEADBEEF, &value);

would not generate an error.

Anuj: Can you verify this does not regress proxy_textures_invalid_size?

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Suggested-by: Brian Paul <brianp@vmware.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Cc: Anuj Phogat <anuj.phogat@gmail.com>

i965/fs: Relax interference check in register coalescing.

A similar attempt was made in commit 5ff1e446 and was reverted in commit
a39428cf after causing a regression in an ES 3 conformance test. The
test still passes after this commit.

total instructions in shared programs: 1994827 -> 1992858 (-0.10%)
instructions in affected programs:     128247 -> 126278 (-1.54%)
GAINED:                                0
LOST:                                  1

Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Perform CSE on sends-from-GRF rather than textures.

Should potentially allow a few more cases, while avoiding doing CSE on
texture operations on Gen <= 6 with the MRF.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80211
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: lu hua <huax.lu@intel.com>

glsl: Update expression types after rebalancing the tree.

If we saw a tree that looked like

            vec3
           /   \
         vec3 float
        /   \
      vec3 float
     /   \
   vec3 float

We would see that all of the expression types were vec3, and then
rebalance to

           vec3
        /        \
      vec3       vec3 <-- should be float
     /   \      /    \
   vec3 float float float

This patch adds code to visit the rebalanced tree and update the
expression types from the bottom up.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80880
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Add callback_leave to ir_hierarchical_visitor.

i965: Initialize new chunks of realloc'd memory.

Otherwise we'd compare uninitialized pointers with NULL and dereference,
leading to crashes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeon/llvm: Fix LLVM diagnostic error reporting

We were trying to print the error message after disposing the
message object.

Tested-by and Reviewed-by: Aaron Watry <awatry@gmail.com>

util/tgsi: Fix ureg_EMIT/ENDPRIM prototype.

0cbefc1bea703378381afff946e30c27a21f191d added a source argument to
EMIT/ENDPRIM, but it did not update tgsi_ureg accordingly, causing all
users of ureg_EMIT/ENDPRIM to fail at runtime with an assertion failure.

Trivial.

glapi: Use GetProcAddress instead of dlsym on Windows.

This patch fixes this MinGW build error.

glapi_gentable.c: In function '_glapi_create_table_from_handle':
glapi_gentable.c:123:9: error: implicit declaration of function 'dlsym' [-Werror=implicit-function-declaration]
         *procp = dlsym(handle, symboln);
         ^

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Acked-by: Brian Paul <brianp@vmware.com>

ilo: raise texture size limits

Report the hardware limits now that max-texture-size piglit test has been
fixed.

ilo: move away from drm_intel_bo_alloc_tiled

We want to know the exact sizes of the BOs, and the driver has the knowledge
to do so.  Refactoring of the resource allocation code is needed though.

radeonsi: partially revert "switch descriptors to i32 vectors"

It indeed breaks LLVM 3.4.2.

i965/vec4: Invalidate live intervals in opt_cse, not _local.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Move aeb list into opt_cse_local.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Invalidate live intervals in opt_cse, not _local.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Move aeb list into opt_cse_local.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Fix aggregates with dynamic initializers.

Vectors are falling in to the ir_dereference_array() path.

Without this change, the following glsl aborts the debug driver,
or gets the wrong answer in release:

mat2x2 a = mat2( vec2( 1.0, vertex.x ), vec2( 0.0, 1.0 ) );

Also submitting piglit tests, will reference in bug.

v2: Rebase on Mesa master.

v3: Remove unneeded check for arrays, which are covered by
    process_array_constructor(), recommended by Timothy Arceri.

Signed-off-by: Cody Northrop <cody@lunarg.com>
Reviewed-by: Courtney Goeltzenleuchter <courtney@lunarg.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79373

Avoid mesa_dri_drivers import lib being installed

On Cygwin and MinGW, linking a shared library also generates an import library

Use a wildcard which also matches the name of the megadriver import lib,
mesa_dri_drivers.dll.a, so that is also removed after megadriver symlinks are
created

(This then matches src/gallium/targets/dri/Makefile.am, which already does
things this way)

Signed-off-by: Jon TURNEY <jon.turney@dronecode.org.uk>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

i965/vec4: Silence warnings about unhandled interpolation ops

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

docs: Mark off ARB_gpu_shader5 interpolation functions for i965

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

i965/fs: add support for ir_*_interpolate_at_* expressions

SIMD8-only for now.

V5: - Fix style complaints
    - Move prototype to be with other oddball emit functions
    - Use unreachable() instead of assert() where possible

V6: - Describe what is happening with the clamping
    - Add reg_width to make some expressions clearer

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Skip channel expressions splitting for interpolation

The backend will have to do a message send, so we want to keep these in
one piece, just like texture ops.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: add generator support for pixel interpolator query

V5: - Split into separate opcodes
    - Pass message data in src1 immediate
    - Put noperspective bit in fs_inst rather than adding any junk to
      backend_instruction

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: add low-level support for send to pixel interpolator

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/disasm: add support for pixel interpolator messages

V3: Rework for brw_inst changes

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add message descriptor bit definitions for pixel interpolator

These got lost in the big brw_inst shakeup.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/disasm: Disassemble indirect sends more properly

- Don't try to disassemble send's src1 as a descriptor if it's not an
  immediate.

- In the same case, show src1 as an operand (makes it easier to see
  bogus register regions, etc -- the hardware is very fussy)

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Avoid crashing while dumping vec4 insn operands

We'd otherwise go looking into virtual_grf_sizes for things that aren't
in there at all.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Fix two broken asserts in brw_eu_emit

These were looking in the wrong field.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: add new interpolateAt* builtin functions

V2: - Don't assume everyone wants interpolateAtSample() lowered to
      interpolateAtOffset. It turns out this isn't what we want most
      of the time for i965. Lowering can be added later in an ir pass
      which drivers opt into, rather than bolting it straight into the
      builtin definition.
    - Only expose the interpolateAt* builtins in the fragment language.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: add new expression types for interpolateAt*

Will be used to implement interpolateAt*() from ARB_gpu_shader5

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

allow builtin functions to require parameters to be shader inputs

The new interpolateAt* builtins have strange restrictions on the
<interpolant> parameter.

- It must be a shader input, or an element of a shader input array.
- It must not include a swizzle.

V2: Don't abuse ir_var_mode_shader_in for this; make a new flag.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

radeonsi: rename definitions of shader limits

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

radeonsi: switch descriptors to i32 vectors

This is a follow-up to the commit which adds texture fetches with offsets.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

radeonsi: properly implement texture opcodes that take an offset

Instead of using intr_name in lp_build_tgsi_action, this selects the names
with a switch statement in the emit function. This allows emitting
llvm.SI.sample for instructions without offsets and llvm.SI.image.sample.*.o
otherwise.

This depends on my LLVM changes.

When LLVM 3.5 is released, I'll switch all texture instructions to the new
intrinsics.

radeonsi: fix texture fetches with derivatives for 1DArray and 3D textures

radeonsi: fix samplerCubeShadow with bias

Pack the depth value before overwriting it with cube coordinates.

Cc: mesa-stable@lists.freedesktop.org

st/mesa: fix samplerCubeShadow with bias

It has 5 coordinates: (x,y,z,depth,lodbias)

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>