Jacob Lifshay [Wed, 13 Dec 2023 00:49:24 +0000 (16:49 -0800)]
caller.py: XLEN must be accessed as self.XLEN
Luke Kenneth Casson Leighton [Sat, 9 Dec 2023 06:47:26 +0000 (06:47 +0000)]
reenable tests
Luke Kenneth Casson Leighton [Thu, 7 Dec 2023 17:52:33 +0000 (17:52 +0000)]
correction syntax error
Luke Kenneth Casson Leighton [Tue, 5 Dec 2023 14:45:37 +0000 (14:45 +0000)]
bug 672: remove redundant/incorrect comment in pospopcount
Luke Kenneth Casson Leighton [Fri, 1 Dec 2023 09:05:12 +0000 (09:05 +0000)]
bug 672: pospopcount, cleanup, no functional change
Luke Kenneth Casson Leighton [Thu, 30 Nov 2023 15:26:00 +0000 (15:26 +0000)]
bug 672: pospopcount, correct NGI Grant
Luke Kenneth Casson Leighton [Wed, 29 Nov 2023 19:43:26 +0000 (19:43 +0000)]
bug #672: more code-comments
Luke Kenneth Casson Leighton [Wed, 29 Nov 2023 19:41:22 +0000 (19:41 +0000)]
comments
Luke Kenneth Casson Leighton [Wed, 29 Nov 2023 19:36:17 +0000 (19:36 +0000)]
bug #672: shorten pospopcount further
by setting VL=MVL=8 the sv.popcntd/sw=8 will wipe out the unused destinations
to zeros, so no need to clear them manually. loses one additional instruction
Luke Kenneth Casson Leighton [Wed, 29 Nov 2023 19:29:12 +0000 (19:29 +0000)]
bug #672: pospopcount working with large arrays
pospopcount is supposed to be able to handle long arrays of data,
but it turns out that sv.lbzu/pi/dw=8 was calculating an EA in 8-bit,
meaning that it wrapped around to a zero memory address.
now this is resolved the code which has been made shorter actually works
Luke Kenneth Casson Leighton [Wed, 29 Nov 2023 19:27:23 +0000 (19:27 +0000)]
bug #672: pospopcount using sv.lbzu/pi/dw=8 error
COMPLEX! this turns out to be a spec violation where RA (EA)
*must* be treated as 64-bit *NOT* have its width overridden
just because destination elwidth is set to 8-bit.
* source elwidth is supposed to apply to STORE
* dest elwidth is supposed to apply to LOAD
but those are MEMORY DATA not memory ADDRESSes they are
supposed to apply to.
TODO, most likely LDST_IDX needs fixing (RB may also need
an elwidth cancellation/override, have to check the spec)
Luke Kenneth Casson Leighton [Wed, 29 Nov 2023 15:06:18 +0000 (15:06 +0000)]
bug #672: shorter pospopcount but not fully working
variant on pospopcount but when 241 array items instead of 240 are used
it produces the wrong answer. under investigation
Jacob Lifshay [Wed, 29 Nov 2023 06:13:25 +0000 (22:13 -0800)]
ISACaller/parser: kludge: support (RA|0) when elwidth != 64
https://bugs.libre-soc.org/show_bug.cgi?id=1221
Jacob Lifshay [Wed, 29 Nov 2023 06:12:17 +0000 (22:12 -0800)]
isatables: update generated csvs
Luke Kenneth Casson Leighton [Tue, 28 Nov 2023 22:45:42 +0000 (22:45 +0000)]
bug #672: pospopcount finally got the right answer
forgot to add popcntd initially, lots of futzing around, still work to do
but it gives a correct answer now
Luke Kenneth Casson Leighton [Tue, 28 Nov 2023 21:03:43 +0000 (21:03 +0000)]
bug #672: fixing pospopcount assembler
there is a lot going on here, this is pushing the boundaries of
what ISAcaller can do (or hasnt been asked to do... until now)
* gbbd (gather bits and bytes double) had to be added
* sw=8,dw=64 had to be fixed (XLEN is actually 64 there
but source elements have to be ZERO-EXTENDED...)
* a bug in sv.addi/sw=8 was found
https://bugs.libre-soc.org/show_bug.cgi?id=1221
* some changes to setvl have to be made/written (!)
* sv.bc in CTR-reduction mode needs to potentially be fixed
or at least properly examined
Luke Kenneth Casson Leighton [Tue, 28 Nov 2023 20:41:01 +0000 (20:41 +0000)]
fix elwidth overrides when sw=8
the way that XLEN works is it must be MAX(sw,dw) which is not what
was happening, it was fixed at sw (source width)
Luke Kenneth Casson Leighton [Mon, 27 Nov 2023 13:55:53 +0000 (13:55 +0000)]
add gbbd (bmatflip) test case - just the one for now
Luke Kenneth Casson Leighton [Mon, 27 Nov 2023 13:45:12 +0000 (13:45 +0000)]
whitespace
Luke Kenneth Casson Leighton [Mon, 27 Nov 2023 13:29:18 +0000 (13:29 +0000)]
add gbbd to minor_22.csv, add OP_BMAT to power_enums.py
Luke Kenneth Casson Leighton [Mon, 27 Nov 2023 13:14:43 +0000 (13:14 +0000)]
add first gather instruction pseudocode
Luke Kenneth Casson Leighton [Sun, 3 Dec 2023 18:08:36 +0000 (18:08 +0000)]
project standard is to use c standard string specifiers NOT format
NOT php-style "f"
Luke Kenneth Casson Leighton [Sun, 3 Dec 2023 18:07:33 +0000 (18:07 +0000)]
project standard is to use c standard string specifiers NOT format
NOT php-style "f"
Luke Kenneth Casson Leighton [Sun, 3 Dec 2023 18:05:30 +0000 (18:05 +0000)]
project standard is to use c standard string specifiers NOT format
NOT php-style "f"
Luke Kenneth Casson Leighton [Sun, 3 Dec 2023 18:02:43 +0000 (18:02 +0000)]
project standard is to use c standard string specifiers NOT format
NOT php-style "f"
Luke Kenneth Casson Leighton [Sun, 3 Dec 2023 17:45:53 +0000 (17:45 +0000)]
bug 1228: dcbt* to match against nop, not dc* in ISACaller
Luke Kenneth Casson Leighton [Sat, 9 Dec 2023 06:40:35 +0000 (06:40 +0000)]
bug #672: fix sv.minmax dd-ffirst-single unit test
Luke Kenneth Casson Leighton [Fri, 8 Dec 2023 15:38:26 +0000 (15:38 +0000)]
bug #672: invert testing in sv.minmax and add Rc=1
Luke Kenneth Casson Leighton [Fri, 8 Dec 2023 15:21:34 +0000 (15:21 +0000)]
bug #676: add sv.minmax dd-ffirst-single test
Shriya Sharma [Thu, 7 Dec 2023 20:15:13 +0000 (20:15 +0000)]
added a log func on the expected results for scalar ddffirst
Shriya Sharma [Thu, 7 Dec 2023 20:04:04 +0000 (20:04 +0000)]
added a log func on the expected results for scalar ddffirst
Luke Kenneth Casson Leighton [Thu, 7 Dec 2023 20:00:12 +0000 (20:00 +0000)]
add repr function to CR field
Luke Kenneth Casson Leighton [Thu, 7 Dec 2023 19:52:29 +0000 (19:52 +0000)]
correction to idx
Luke Kenneth Casson Leighton [Thu, 7 Dec 2023 19:52:02 +0000 (19:52 +0000)]
correction to ra
Luke Kenneth Casson Leighton [Thu, 7 Dec 2023 19:51:38 +0000 (19:51 +0000)]
correction to VL
Shriya Sharma [Thu, 7 Dec 2023 19:54:19 +0000 (19:54 +0000)]
added the expected results for scalar ddffirst
Shriya Sharma [Thu, 7 Dec 2023 19:43:50 +0000 (19:43 +0000)]
starting on the unit test for scalar ddffirst
Luke Kenneth Casson Leighton [Thu, 7 Dec 2023 19:28:29 +0000 (19:28 +0000)]
bug #1183: add test function sv_cmpi
based on https://bugs.libre-soc.org/show_bug.cgi?id=1183#c3
Luke Kenneth Casson Leighton [Thu, 7 Dec 2023 17:26:15 +0000 (17:26 +0000)]
bug #1183: attempt first ddffirst mapreduce mode
Luke Kenneth Casson Leighton [Sun, 3 Dec 2023 11:32:28 +0000 (11:32 +0000)]
bug 1231: all dc* instructions to be treated as nop
https://bugs.libre-soc.org/show_bug.cgi?id=1231#c1
Jacob Lifshay [Fri, 1 Dec 2023 20:57:34 +0000 (12:57 -0800)]
elf/simple_cases: deepcopy is unnecessary, call dict.copy
Luke Kenneth Casson Leighton [Fri, 1 Dec 2023 17:49:51 +0000 (17:49 +0000)]
bug 1169: elf-support correct syntax errors
Luke Kenneth Casson Leighton [Fri, 1 Dec 2023 14:42:25 +0000 (14:42 +0000)]
bug 1169: elf support, minor coding style adjustment, clearer
Jacob Lifshay [Fri, 1 Dec 2023 09:17:05 +0000 (01:17 -0800)]
openpower/test/elf/simple_cases: add some simple ELF test cases
Jacob Lifshay [Fri, 1 Dec 2023 07:55:41 +0000 (23:55 -0800)]
add utilities for testing ELF files
Jacob Lifshay [Fri, 1 Dec 2023 07:54:48 +0000 (23:54 -0800)]
SimRunner: support running an ELFFile
Jacob Lifshay [Fri, 1 Dec 2023 07:51:08 +0000 (23:51 -0800)]
ISACaller: support loading an ELFFile
Jacob Lifshay [Fri, 1 Dec 2023 07:46:50 +0000 (23:46 -0800)]
mem.py: add load_elf
Jacob Lifshay [Fri, 1 Dec 2023 07:40:51 +0000 (23:40 -0800)]
mem.py: fix SIGBUS when accessing file mapped by mmap_syscall
this fixes SIGBUS errors caused by accessing beyond the end of a
file but still in the last page of the file, which is a valid thing to
do, except that we have to account for host pages having a different
size than emulated pages and map zeros to fill out the rest of the
emulated page.
Jacob Lifshay [Fri, 1 Dec 2023 07:29:18 +0000 (23:29 -0800)]
caller.py: implement write syscall
Jacob Lifshay [Fri, 1 Dec 2023 07:27:48 +0000 (23:27 -0800)]
caller.py: implement exit_group syscall
Jacob Lifshay [Fri, 1 Dec 2023 07:15:45 +0000 (23:15 -0800)]
ISACaller: fix syscall emulation
there were two bugs fixed:
1. sc emulation was missing a `return`, so it tried to run sc
again after running sc and rfid, giving the wrong CIA and
MSR values.
2. the code to replace and restore the instruction with rfid
had the wrong endian on the load, so it was corrupting the
instruction for the next time it was used. I just deleted
the save/replace/restore code since it isn't needed anymore.
I then changed the syscall tests to ensure both the
bugs above don't happen again.
Jacob Lifshay [Thu, 30 Nov 2023 03:04:26 +0000 (19:04 -0800)]
setup: add pyelftools v0.30 as dependency
Jacob Lifshay [Mon, 27 Nov 2023 05:43:46 +0000 (21:43 -0800)]
add g++-powerpc64le-linux-gnu to .gitlab-ci.yml
Jacob Lifshay [Mon, 27 Nov 2023 03:14:21 +0000 (19:14 -0800)]
add mmap_syscall tests
Jacob Lifshay [Mon, 27 Nov 2023 03:13:25 +0000 (19:13 -0800)]
implement MemMMap.mmap_syscall
Jacob Lifshay [Mon, 27 Nov 2023 03:11:35 +0000 (19:11 -0800)]
add ppc_flags.py so we can get the ppc versions of all the flags we need
tells gcc to dump all #defines, and parses that.
Luke Kenneth Casson Leighton [Fri, 1 Dec 2023 17:57:12 +0000 (17:57 +0000)]
replace print() with log()
Luke Kenneth Casson Leighton [Fri, 1 Dec 2023 17:54:16 +0000 (17:54 +0000)]
replace print() with log()
Luke Kenneth Casson Leighton [Fri, 1 Dec 2023 17:52:24 +0000 (17:52 +0000)]
replace print() with log()
Jacob Lifshay [Thu, 30 Nov 2023 22:55:08 +0000 (14:55 -0800)]
pytest: try to improve scheduling
Jacob Lifshay [Thu, 30 Nov 2023 22:54:05 +0000 (14:54 -0800)]
test_caller_svp64_powmod: rename to test_aaa_caller_svp64_powmod so pytest tries to run it earlier
Jacob Lifshay [Thu, 30 Nov 2023 22:21:36 +0000 (14:21 -0800)]
speed up CI by disabling logging and VCD generation
Jacob Lifshay [Thu, 30 Nov 2023 22:20:54 +0000 (14:20 -0800)]
test/runner: allow disabling VCD using SIM_NO_VCD=1 env var
Jacob Lifshay [Tue, 17 Oct 2023 05:22:50 +0000 (22:22 -0700)]
powmod asm tests pass!
Jacob Lifshay [Mon, 16 Oct 2023 23:09:07 +0000 (16:09 -0700)]
switch powmod to using new divmod implementation -- test not enabled yet
Jacob Lifshay [Mon, 16 Oct 2023 23:08:44 +0000 (16:08 -0700)]
call log, not print
Jacob Lifshay [Mon, 16 Oct 2023 22:39:17 +0000 (15:39 -0700)]
make parser work for pypy
pypy's ast classes' constructors seem to only work if all arguments or
no arguments are passed, not only some of them.
Jacob Lifshay [Mon, 16 Oct 2023 04:17:09 +0000 (21:17 -0700)]
add comments telling people to keep the asm and python versions in sync
Jacob Lifshay [Mon, 16 Oct 2023 04:06:02 +0000 (21:06 -0700)]
divmod: asm version of Knuth's algorithm D works!
Jacob Lifshay [Mon, 16 Oct 2023 03:59:36 +0000 (20:59 -0700)]
add labels to DIVMOD REGEX log
Jacob Lifshay [Mon, 16 Oct 2023 03:54:12 +0000 (20:54 -0700)]
put DIVMOD REGEX under new LogType: LogType.OutputMatching
Jacob Lifshay [Fri, 13 Oct 2023 22:13:15 +0000 (15:13 -0700)]
WIP divmod: finished writing out asm knuth's algorithm d, still buggy
Jacob Lifshay [Thu, 12 Oct 2023 03:29:51 +0000 (20:29 -0700)]
WIP getting asm version of knuth's algorithm d working
Jacob Lifshay [Wed, 11 Oct 2023 05:07:17 +0000 (22:07 -0700)]
WIP divmod: implemented division by single word
Jacob Lifshay [Wed, 11 Oct 2023 05:05:49 +0000 (22:05 -0700)]
support ignoring integer registers for ExpectedState
Jacob Lifshay [Wed, 11 Oct 2023 05:03:38 +0000 (22:03 -0700)]
convert assigned values to SVSHAPE when writing to SVSHAPE[0-3] SPRs
this makes mtspr SVSHAPE0, reg properly maintain ISACaller invariants
Jacob Lifshay [Tue, 10 Oct 2023 04:05:17 +0000 (21:05 -0700)]
add WIP Knuth's algorithm D assembly
Jacob Lifshay [Tue, 10 Oct 2023 03:38:30 +0000 (20:38 -0700)]
divmod: assign registers to variables
Jacob Lifshay [Tue, 10 Oct 2023 03:35:40 +0000 (20:35 -0700)]
adapt divmod algorithm for putting variables in registers
Jacob Lifshay [Tue, 10 Oct 2023 03:30:43 +0000 (20:30 -0700)]
add more features for _DivModRegsRegexLogger
Jacob Lifshay [Tue, 10 Oct 2023 01:25:43 +0000 (18:25 -0700)]
finish moving Knuth algorithm D into a class
Jacob Lifshay [Tue, 10 Oct 2023 01:21:40 +0000 (18:21 -0700)]
merely indent function
[skip ci]
Jacob Lifshay [Tue, 10 Oct 2023 01:19:25 +0000 (18:19 -0700)]
start adding DivModKnuthAlgorithmD class
Jacob Lifshay [Tue, 10 Oct 2023 01:18:28 +0000 (18:18 -0700)]
format code
Jacob Lifshay [Mon, 9 Oct 2023 04:46:57 +0000 (21:46 -0700)]
finish writing python_divmod_knuth_algorithm_d
Jacob Lifshay [Mon, 9 Oct 2023 04:46:14 +0000 (21:46 -0700)]
fix generating invalid divmod tests
Jacob Lifshay [Mon, 9 Oct 2023 04:43:00 +0000 (21:43 -0700)]
speed up divmod shift-sub tests by removing most test cases
Jacob Lifshay [Sat, 7 Oct 2023 00:08:35 +0000 (17:08 -0700)]
add WIP knuth algorithm D python implementation
Jacob Lifshay [Fri, 6 Oct 2023 22:21:07 +0000 (15:21 -0700)]
rename divmod algorithm -> divmod_shift_sub in prep for adding divmod based on Knuth's Algorithm D
Jacob Lifshay [Fri, 6 Oct 2023 02:57:29 +0000 (19:57 -0700)]
add WIP powmod_256 -- asm test is currently disabled since divmod is too slow
Jacob Lifshay [Fri, 6 Oct 2023 02:53:45 +0000 (19:53 -0700)]
fix assemble to properly look for whole symbols to replace
previously if there were labels foo and foobar, it would partially
replace foobar giving 0x<addr>bar, which is wrong.
also optimized to use dict instead of linear search for label names
Luke Kenneth Casson Leighton [Thu, 30 Nov 2023 03:03:14 +0000 (03:03 +0000)]
whitespace in pseudocode to aid clarity
Luke Kenneth Casson Leighton [Mon, 27 Nov 2023 10:08:43 +0000 (10:08 +0000)]
got sv.bc working for pospopcount
Luke Kenneth Casson Leighton [Mon, 27 Nov 2023 09:47:29 +0000 (09:47 +0000)]
try ctrtest mode in pospopcount
Luke Kenneth Casson Leighton [Thu, 23 Nov 2023 07:03:49 +0000 (07:03 +0000)]
reduce indentation
Luke Kenneth Casson Leighton [Tue, 21 Nov 2023 17:40:27 +0000 (17:40 +0000)]
starting on pospopcount assembler
Luke Kenneth Casson Leighton [Tue, 21 Nov 2023 12:39:28 +0000 (12:39 +0000)]
add cut/paste copy of strncpy example as basis for pospopcount
https://bugs.libre-soc.org/show_bug.cgi?id=672
Jacob Lifshay [Tue, 21 Nov 2023 01:45:23 +0000 (17:45 -0800)]
fix vertical-first sv.bc
https://bugs.libre-soc.org/show_bug.cgi?id=1210
Andrey Miroshnikov [Fri, 17 Nov 2023 14:55:52 +0000 (14:55 +0000)]
Added sv.bc in vertical-first test