gem5.git
5 years agocpu-o3: Add cache read ports limit to LSQ
Gabor Dozsa [Mon, 25 Jun 2018 15:59:26 +0000 (16:59 +0100)]
cpu-o3: Add cache read ports limit to LSQ

This change introduces cache read ports to limit the number of
per-cycle loads. Previously only the number of per-cycle stores
could be limited.

Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13517
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agopython: Make iterator handling Python 3 compatible
Andreas Sandberg [Sat, 26 Jan 2019 09:19:22 +0000 (09:19 +0000)]
python: Make iterator handling Python 3 compatible

Many functions that used to return lists (e.g., dict.items()) now
return iterators and their iterator counterparts (e.g.,
dict.iteritems()) have been removed. Switch calls to the Python 2.7
iterator methods to use the Python 3 equivalent and add explicit list
conversions where necessary.

Change-Id: I0c18114955af8f4932d81fb689a0adb939dafaba
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15992
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
5 years agopython: Add missing operators to NumericParamValue
Andreas Sandberg [Sun, 27 Jan 2019 12:01:08 +0000 (12:01 +0000)]
python: Add missing operators to NumericParamValue

Add missing operators to NumericParamValue and ensure that they are
able to work on the underlying value if the right hand side is a
param.

Change-Id: I2bd86662aee9891bbd89aed7ebe20b827b5528bd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16001
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
5 years agomem-cache: Add a mechanism to iterate all entries of an AssociativeSet
Javier Bueno [Thu, 21 Feb 2019 20:56:09 +0000 (21:56 +0100)]
mem-cache: Add a mechanism to iterate all entries of an AssociativeSet

Added functions to obtain an iterator to access all entries of
an AssociativeSet container.

Change-Id: I1ec555bd97d97e3edaced2b8f61287e922279c26
Reviewed-on: https://gem5-review.googlesource.com/c/16582
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

5 years agoscons: Add a convenience method to set RPATH for local libraries.
Gabe Black [Thu, 21 Feb 2019 01:43:15 +0000 (17:43 -0800)]
scons: Add a convenience method to set RPATH for local libraries.

When linking in a dynamic library which is in the gem5 build directory,
it's useful to set RPATH so that you don't have to set LD_LIBRARY_PATH
when you run gem5 so that the dynamic linker can find it.

Since it's tricky and not entirely obvious how to set up those paths
correctly, this change adds a small convenience function which does
that for you. It also handles situations where the same dynamic
library may be linked into different binaries in different directories
which each need a different relative RPATH. It does that by letting the
environment for each binary set a construction variable which says
how to get from that particular binary back to the build directory.
This helper method then sets RPATH to start at $ORIGIN (the binary),
to follow that relative path to the variant build directory, and then
the per-library but not per-binary path to the library's directory.

This change also adds the -z origin linker flag which makes the linker
handle $ORIGIN properly.

Change-Id: I45f4d72cd14396a73e0b963cea6a39d9bfb7f984
Reviewed-on: https://gem5-review.googlesource.com/c/16566
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agosystemc: Make the verify.py script work when run from different dirs.
Gabe Black [Thu, 21 Feb 2019 00:08:50 +0000 (16:08 -0800)]
systemc: Make the verify.py script work when run from different dirs.

The verify.py script ran scons from the CWD, and that would fail if
there wasn't a SConstruct in that directory, ie if it wasn't from the
source of the checkout.

This change makes verify.py use scons' --directory option to run from
where the SConstruct is, or at least the SConstruct which was checked
out alongside that copy of verify.py. That location can be overridden
using the new -C or --scons-dir options.

Change-Id: I9f033d6dd30e0c2992b7f3102c573b34ea9c49e0
Reviewed-on: https://gem5-review.googlesource.com/c/16562
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agoext: test: Split up the GTEST_CPPFLAGS and CPPFLAGS.
Gabe Black [Thu, 21 Feb 2019 01:59:01 +0000 (17:59 -0800)]
ext: test: Split up the GTEST_CPPFLAGS and CPPFLAGS.

scons seems to get confused in some situations when this is a single
large string and passes it as one big argument to g++ instead of
breaking it up into several arguments.

We need to do the work for it and break it into individual arguments,
like what was already being done with GTEST_LIBS.

Also wrap some overly long lines.

Change-Id: Ib7688a7abced43a9c62994d17b78d358fc0dc000
Reviewed-on: https://gem5-review.googlesource.com/c/16567
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agosystemc: Make sc_(pause|stop) exit to python when not using sc_main.
Gabe Black [Thu, 14 Feb 2019 09:54:20 +0000 (01:54 -0800)]
systemc: Make sc_(pause|stop) exit to python when not using sc_main.

In those cases, there's no sc_main to return control to. The python
config script is serving more or less the same purpose, so we can
return control to there instead.

Change-Id: I3cf0623ae51d989b883fb8556ebbf44651bbec99
Reviewed-on: https://gem5-review.googlesource.com/c/16445
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agosystemc: Init some values in the scheduler for running without sc_main.
Gabe Black [Thu, 14 Feb 2019 09:42:19 +0000 (01:42 -0800)]
systemc: Init some values in the scheduler for running without sc_main.

When running without sc_main, sc_start won't be called, and therefore
runToTime and maxTick won't be initialized. To avoid the scheduler
getting confused and behaving erratically, those values should be
initialized to something that makes sense in situations where there's
no sc_main.

Change-Id: I6ddd7db9ecb36d716eb5ef75e1c38bb99a386092
Reviewed-on: https://gem5-review.googlesource.com/c/16443
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agosystemc: Handle exceptions "correctly" even if sc_main hasn't been run.
Gabe Black [Thu, 14 Feb 2019 06:30:02 +0000 (22:30 -0800)]
systemc: Handle exceptions "correctly" even if sc_main hasn't been run.

If sc_main hasn't run, for instance if there isn't an sc_main and gem5
is orchestrating the simulation directly, then exceptions shouldn't be
thrown to the sc_main fiber since it isn't running and may not be able
to run since sc_main may not even exist.

Instead, we need to check whether it makes sense to throw to sc_main,
and if not pass the exception directly to the report handler since
there likely won't be anyone to catch it if we just throw it from the
scheduler or into general purpose gem5.

Since the name throwToScMain is no longer a complete description for
what that function does, this change renames it to throwUp, since it
will now throw exceptions up the stack, either to sc_main or to the
conceptual top level by going directly to the report handler.

Change-Id: Ibdc92c9cf213ec6aa15ad654862057b7bf2e1c8e
Reviewed-on: https://gem5-review.googlesource.com/c/16442
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agomem-cache: Added the Slim AMPM Prefetcher
Javier Bueno [Thu, 31 Jan 2019 15:24:48 +0000 (16:24 +0100)]
mem-cache: Added the Slim AMPM Prefetcher

Reference:
    Towards Bandwidth-Efficient Prefetching with Slim AMPM.
    Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship.

Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already
in gem5).

Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a
Reviewed-on: https://gem5-review.googlesource.com/c/16383
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

5 years agopython: Fix Param initialization issue in Python 3
Andreas Sandberg [Sat, 26 Jan 2019 08:40:40 +0000 (08:40 +0000)]
python: Fix Param initialization issue in Python 3

When initializing a param with a SimObject NULL pointer, convert()
checks if the 'ptype' attribute has been created and whether the value
is NULL. In that case, it assumes that the object is being
initizalized as a part of SimObject initialization and defers the
conversion. This check is implemented using hasattr() which in turn is
implemented using the __getattr__ implementation that asserts because
all SimObjects haven't been initialized yet.

Implement the check using a lookup in the object's dictionary instead
to prevent the SimObject lookup.

Change-Id: I7367563c4fb71f6d2be541ebdc0be418e9f73d48
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15990
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
5 years agopython: Use __name__ instead of func_name for Py3 compat
Andreas Sandberg [Sat, 26 Jan 2019 10:52:26 +0000 (10:52 +0000)]
python: Use __name__ instead of func_name for Py3 compat

Change-Id: I62a9685b4bce7e9012bc65309fcafe26135fde6d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15997
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
5 years agopython: Add __bool__ helpers in addition to __nonzero__
Andreas Sandberg [Sat, 26 Jan 2019 10:51:29 +0000 (10:51 +0000)]
python: Add __bool__ helpers in addition to __nonzero__

Python 3 uses __bool__ instead of __nonzero__ when performing a
Boolean comparison.

Change-Id: I85185bbe136ecae67346fa23569e24edd7329222
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
5 years agoconfig: Make parameter conversion handle integers in other bases.
Gabe Black [Sat, 16 Feb 2019 01:10:02 +0000 (17:10 -0800)]
config: Make parameter conversion handle integers in other bases.

Python's float() function/type can't handle hexadecimal notation, but
int() can. Since there are also cases where converting to a float and
then back to an int (or long) can cause rounding error, this change
splits toFloat and toInteger apart and makes them call a worker
function which accepts a conversion function which does the work of
converting a numeric string into an actual number.

in the case of toFloat, it still uses the standard float(), and in the
case of toInteger it uses a lambda which wraps int(x, 0).

Change-Id: Ic46cf4ae86b7eba6f55d731d1b25e3f84b8bb64c
Reviewed-on: https://gem5-review.googlesource.com/c/16504
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agox86: Call the base class's regStats in X86ISA::TLB
Bagus Hanindhito [Tue, 19 Feb 2019 23:52:23 +0000 (17:52 -0600)]
x86: Call the base class's regStats in X86ISA::TLB

When I try to build x86 architecture and run the se.py sample script
with helloworld example, there is a panic warning stated "Not all stats
have been initialized. You may need to add <ParentClass>::regStats() to
a new SimObject's regStats() function."

I see that in x86 tlb.cc, there is no initialization in regStats() function
that causes memory allocation error in some machine which make gem5 exit
abnormally. I add the BaseTLB::regStats(); on TLB::regStats() method and
can solve the problem

Change-Id: I8b62bebc15f896c3136ff4f8253dabbf998f618f
Reviewed-on: https://gem5-review.googlesource.com/c/16522
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agosim: Add a mechanism to exit the simulation loop immediately.
Gabe Black [Thu, 14 Feb 2019 09:46:54 +0000 (01:46 -0800)]
sim: Add a mechanism to exit the simulation loop immediately.

There are some cases, specifically when running systemc, that it's
necessary to exit the simulation loop immediately rather than finishing
running events scheduled for the current Tick. When running under
sc_main, sc_stop and sc_pause return control to sc_main which can
happen immediately. When running without sc_main, control needs to
return to the python config script which needs to happen through a
global exit event.

Since sc_pause and sc_stop are supposed to stop simulation without
necessarily letting all the events at the current time run, we need
a way to schedule an exit event with a very high priority (rather than
a very low priority).

This change adds a new exitSimLoopNow function which does that, and
adds a new constructor to the GlobalSimLoopExitEvent which uses that
priority.

Also, a couple of cruft functions from the sim events are removed.

Change-Id: Icfbec17fb10f98084a75740acd839dbf4096fbb3
Reviewed-on: https://gem5-review.googlesource.com/c/16444
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agocpu: Add ISA* getter in Thread interface
Giacomo Gabrielli [Thu, 14 Feb 2019 17:39:37 +0000 (17:39 +0000)]
cpu: Add ISA* getter in Thread interface

This patch is adding a ISA* getter to the TC interface

Change-Id: Ib8ddc5d8fdd44e782f50a2ad15878a6bcf931e58
Reviewed-on: https://gem5-review.googlesource.com/c/16462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

5 years agoarch-generic: Making base TLB class a MemObject
Ivan Pizarro [Thu, 8 Nov 2018 16:32:38 +0000 (17:32 +0100)]
arch-generic: Making base TLB class a MemObject

Allow configuring a TLB hierarchy using ports

Change-Id: I1f791829d4e072a9104e67eacf69a69de9543634
Reviewed-on: https://gem5-review.googlesource.com/c/14117
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agoarch-arm: Move GICv3 detection at startup time
Giacomo Travaglini [Wed, 30 Jan 2019 12:00:21 +0000 (12:00 +0000)]
arch-arm: Move GICv3 detection at startup time

At the moment the haveGicV3 parameter is used only to signal its
presence when reading the MISCREG_ID_AA64PFR0_EL1 register.  It depends
on the system->getGIC pointing to a GICv3 model.  However this pointer
is set in the System only at init time (after construction), which means
that the haveGICv3CPUInterface will always be false.
This patch is fixing this by moving the parameter initialization at
startup time, together with the cpu interface registration.

Change-Id: I8da6711ea741ecd0f78ec8ca60a8c3ae3bca2421
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16483
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agodev-arm: LPI support for GICv3. This doesn't include an ITS model.
Jairo Balart [Tue, 5 Feb 2019 09:16:34 +0000 (10:16 +0100)]
dev-arm: LPI support for GICv3. This doesn't include an ITS model.

Change-Id: Ia2c02cca4f95672d6361fba16201a56e2047ddb7
Reviewed-on: https://gem5-review.googlesource.com/c/16142
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agobase: Fix enums checkpointing
Giacomo Travaglini [Thu, 7 Feb 2019 07:34:56 +0000 (07:34 +0000)]
base: Fix enums checkpointing

Creating an extra version of string to number converters (__to_number)
in base/str.hh; it will be used by enums only when unserializing
them.  The reason not to have a single helper for both enums and
integers is that std::numeric_limits trait is not specialized for enums.
We fix this by using the std::underlying_type trait.

Change-Id: I819e35c0df8c094de7b7a6390152964fa47d513d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16382
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agocpu: Fix fast build broken due to unused variable
Giacomo Travaglini [Fri, 15 Feb 2019 09:47:34 +0000 (09:47 +0000)]
cpu: Fix fast build broken due to unused variable

This fixes fast build for commit 25dc765889d948693995cfa622f001aa94b5364b
(fast build is striping out assertions)

Change-Id: I9536ad58a3d85990b16a1f8c2515f6bf5d3acf71
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16463
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agosystemc: Add a systemc_home directory which maps to the ext headers.
Gabe Black [Fri, 8 Feb 2019 22:48:12 +0000 (14:48 -0800)]
systemc: Add a systemc_home directory which maps to the ext headers.

Some systemc code bases expect to find a SYSTEMC_HOME environment
variable which points to the installed header files provided by
systemc, all under ${SYSTEMC_HOME}/include. The systemc headers in
gem5 are not supposed to be installed anywhere, but to satisfy those
expectations this change creates a dummy systemc_home directory with
an include/ in it which has headers which just include the actual
headers in src/systemc/ext.

More gem5 aware code bases can still access the headers either by
letting gem5's scons environment -I the ext directory, or can do so
themselves if they're not being built by gem5's scons.

Change-Id: I5f2e6bfcf20dd314d525207c2e13ca53474a33f3
Reviewed-on: https://gem5-review.googlesource.com/c/16263
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agosystemc: Make an include in src/systemc/ext use a relative path.
Gabe Black [Fri, 8 Feb 2019 22:46:10 +0000 (14:46 -0800)]
systemc: Make an include in src/systemc/ext use a relative path.

The includes in src/systemc/ext are supposed to use relative paths so
that they can be included in other bodies of code which aren't based
in gem5 and don't share it's -I-s, or potentially even have access to
anything outside of src/systemc/ext.

Change-Id: Icde457329c2c4ab4689221015bfcfe2ff8b051f0
Reviewed-on: https://gem5-review.googlesource.com/c/16262
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agocpu: Added 8KB and 64KB TAGE-SC-L branch predictor
Javier Bueno [Wed, 30 Jan 2019 00:01:50 +0000 (01:01 +0100)]
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor

The original paper of the branch predictor can be found here:
http://www.jilp.org/cbp2016/paper/AndreSeznecLimited.pdf

Change-Id: I684863752407685adaacedebb699205c3559c528
Reviewed-on: https://gem5-review.googlesource.com/c/14855
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agoconfigs: simpoint-profile usable with NonCachingCPUs only
Giacomo Travaglini [Thu, 24 Jan 2019 14:01:59 +0000 (14:01 +0000)]
configs: simpoint-profile usable with NonCachingCPUs only

NonCachingCPU is replacing the Atomic+fastmem option.

Change-Id: I66f5c8a880d1b3fd1331871d89e8d6a229938e57
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15935
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agopython: Remove uses of tuple unpacking in function params
Andreas Sandberg [Sat, 26 Jan 2019 09:07:54 +0000 (09:07 +0000)]
python: Remove uses of tuple unpacking in function params

Python 3 doesn't support tuple unpacking in function parameters and
lambdas.

Change-Id: I36c72962e33a9ad37145089687834becccc76adb
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15991
Reviewed-by: Gabe Black <gabeblack@google.com>
5 years agopython: Replace deprecated repr syntax
Andreas Sandberg [Fri, 25 Jan 2019 18:40:19 +0000 (18:40 +0000)]
python: Replace deprecated repr syntax

Change-Id: I5f9538cf2ca5ee17c51e7c5388d3aef363fcfa54
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15989
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
5 years agopython: Switch from using compare to key in list sort
Andreas Sandberg [Sat, 26 Jan 2019 09:55:35 +0000 (09:55 +0000)]
python: Switch from using compare to key in list sort

Python 3 has deprecated the use of a comparison function in favour of
a key extraction function.

Change-Id: I4b7eab791ecbdfbf7147f57fdbc7cbe8f1de20dd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15995
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
5 years agotests: add cpu tests to the new testing infrastructure
Ayaz Akram [Thu, 24 Jan 2019 06:28:30 +0000 (22:28 -0800)]
tests: add cpu tests to the new testing infrastructure

Change-Id: I42996ddc802ef279ab4970afc37cb0df25c04b08
Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/15857
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agotests: Move test programs paths to related test scripts
Ayaz Akram [Thu, 24 Jan 2019 06:13:29 +0000 (22:13 -0800)]
tests: Move test programs paths to related test scripts

This change is needed to make sure that the DownloadedProgram fixture
does not fail, in case the test binaries are not stored in test-progs/
(e.g. in the case of cpu tests)

Change-Id: Icf96f2537b038502e78da560c7ccebc44984b509
Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/15856
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Rutuja Govind Oza <roza@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agosim-se: update the arm kernel version
Ayaz Akram [Thu, 24 Jan 2019 06:08:44 +0000 (22:08 -0800)]
sim-se: update the arm kernel version

This change is needed to run cpu tests with ARM binaries
compiled with newer linux kernel headers

Change-Id: I6cbf132c38d4b18f971ee32272ddb6a5a791a625
Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/15855
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agotests: Convert memtest to new framework
Jason Lowe-Power [Fri, 24 Aug 2018 00:33:29 +0000 (17:33 -0700)]
tests: Convert memtest to new framework

The original memtest is located at:
https://gem5.googlesource.com/public/gem5/+/master/tests/configs/memtest.py

Change-Id: I58be6fb1675f6502d6644d502915df80aa197a4a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15836
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agotests: Convert tgen-simple-memory to new framework
Jason Lowe-Power [Thu, 23 Aug 2018 23:23:25 +0000 (16:23 -0700)]
tests: Convert tgen-simple-memory to new framework

The original test is located at:
https://gem5.googlesource.com/public/gem5/+/master/tests/configs/tgen-simple-mem.py

Change-Id: I13a58cfb3d01d08ef7c818fc00fb56ba126eb4b6
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15835
Reviewed-by: Rutuja Govind Oza <roza@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agopython: Replace dict.has_key with 'key in dict'
Andreas Sandberg [Fri, 25 Jan 2019 12:12:38 +0000 (12:12 +0000)]
python: Replace dict.has_key with 'key in dict'

Python 3 has removed dict.has_key in favour of 'key in dict'.

Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15987
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
5 years agopython: Add missing defines import
Andreas Sandberg [Tue, 12 Feb 2019 17:04:07 +0000 (17:04 +0000)]
python: Add missing defines import

The _check_tracing helper function in main.py depends on defines to
check if tracing has been enabled at compile time. This module is
imported in main() but not at the module level, which breaks this
function.

Change-Id: I26d65a4320da8618e0e552553695884fd2c880e0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16402
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
5 years agopython: Replace DictMixin with Mapping / MutableMapping
Andreas Sandberg [Fri, 25 Jan 2019 12:00:20 +0000 (12:00 +0000)]
python: Replace DictMixin with Mapping / MutableMapping

Python 3 has removed support for DictMixin, so switch to Mapping /
MutableMapping in collections which provides the same functionality.

Change-Id: I61fbe366d2c9fc6e01b470f82f49cc02b99dec32
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15984
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
5 years agopython: Replace orderdict with collections.OrderedDict
Andreas Sandberg [Tue, 12 Feb 2019 09:57:15 +0000 (09:57 +0000)]
python: Replace orderdict with collections.OrderedDict

Python 2.7 and newer has support for ordered dictionaries in the
standard library. Remove this custom class.

Change-Id: I4b720405aa3c4ce8d5c0b401eefe744a85ac3a3e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16362
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
5 years agopython: Update use of exec to work with Python 3
Andreas Sandberg [Fri, 25 Jan 2019 12:04:31 +0000 (12:04 +0000)]
python: Update use of exec to work with Python 3

Python 3 uses 'exec(code, globals)' instead of 'exec code in
globals'. Switch to the newer syntax since it is supported by Python
2.7. Also, move check_tracing out of main to work around a bug in
Python 2.7.

Change-Id: I6d390160f58783e1b038a572b64cdf3ff09535fa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15986
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
5 years agopython: Switch to using open instead of file
Andreas Sandberg [Fri, 25 Jan 2019 12:03:21 +0000 (12:03 +0000)]
python: Switch to using open instead of file

Python 3 doesn't support the file(name, mode) syntax which has been
deprecated in favour of open.

Change-Id: I35ef8690d97a5243860a64ff985fd22fa86253f1
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15985
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
5 years agomem-cache: Irregular Stream Buffer Prefetcher
Javier Bueno [Wed, 5 Dec 2018 16:27:48 +0000 (17:27 +0100)]
mem-cache: Irregular Stream Buffer Prefetcher

Based in the description of the following publication:
Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses
for improved correlated prefetching. In Proceedings of the 46th Annual
IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM,
New York, NY, USA, 247-259.

Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165
Reviewed-on: https://gem5-review.googlesource.com/c/15215
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
5 years agosystem-arm: Fix dtsi dependencies in Makefile
Kevin Brodsky [Mon, 4 Feb 2019 11:45:52 +0000 (11:45 +0000)]
system-arm: Fix dtsi dependencies in Makefile

Making vexpress_gem5_vX.dtsi depend on vexpress_gem5_vX_base.dtsi
does nothing, since vexpress_gem5_vX.dtsi is never built (much in
the same way as there is no point in making a C header depend on
another).

Fix that by making all the .dts depend on both .dtsi's.

Change-Id: I9131e0b1b2e521bb09d14721dec38bf6a2d98583
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Ruben Ayrapetyan <ruben.ayrapetyan@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16143
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agomem-cache: Added the Delta Correlating Prediction Tables Prefetcher
Javier Bueno [Tue, 5 Feb 2019 22:31:19 +0000 (23:31 +0100)]
mem-cache: Added the Delta Correlating Prediction Tables Prefetcher

Reference:
    Multi-level hardware prefetching using low complexity delta correlating
    prediction tables with partial matching.
    Marius Grannaes, Magnus Jahre, and Lasse Natvig. 2010.
    In Proceedings of the 5th international conference on High Performance
    Embedded Architectures and Compilers (HiPEAC'10)
Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d
Reviewed-on: https://gem5-review.googlesource.com/c/16062
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agotests: Rewrite Makefiles for pthreads test
Andreas Sandberg [Thu, 10 Jan 2019 11:41:57 +0000 (11:41 +0000)]
tests: Rewrite Makefiles for pthreads test

The Makefiles for the pthreads test don't behave like typical
Makefiles that support cross compilation. Rewrite the Makefile to make
cross-compilation more convenient and add targets for aarch{32,64}.

Change-Id: I7cae378492681744b6bb11dd5af69db81ec54229
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16022
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
5 years agopython: Don't assume SimObjects live in the global namespace
Andreas Sandberg [Fri, 25 Jan 2019 14:26:21 +0000 (14:26 +0000)]
python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
5 years agoarch-mips: Remove unused Python file
Andreas Sandberg [Mon, 11 Feb 2019 18:23:50 +0000 (18:23 +0000)]
arch-mips: Remove unused Python file

Change-Id: I7155915fccdec1d9f116f2a8617474188a91165b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16302
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agopython: Make exception handling Python 3 safe
Andreas Sandberg [Fri, 25 Jan 2019 11:32:25 +0000 (11:32 +0000)]
python: Make exception handling Python 3 safe

Change-Id: I9c2cdfad20deb1ddfa224320cf93f2105d126652
Reviewed-on: https://gem5-review.googlesource.com/c/15980
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
5 years agopython: Fix native module initialisation on Python 3
Andreas Sandberg [Mon, 28 Jan 2019 16:14:41 +0000 (16:14 +0000)]
python: Fix native module initialisation on Python 3

The approach we currently use to register our native modules doesn't
work on Python 3. Convert the code to use the Python inittab instead
of the old ad-hoc method.

Change-Id: I961f8a33993c621473732faeaab955a882769a4b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15979
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
5 years agomem-ruby: Fixing Topology
Pouya Fotouhi [Sun, 20 Jan 2019 00:38:27 +0000 (16:38 -0800)]
mem-ruby: Fixing Topology

The constructor assumes the number of nodes (i.e. controllers) equal to
the number of external nodes.
This is a not necessarily valid for all cases (e.g MESI_Three_Level -
where L0s are directly connected to L1s).
MachineType_base_number(MachineType_NUM) provides the total number of
controllers.

Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Change-Id: Id906099dc967ec70aa34dedb0b55351031ff242c
Reviewed-on: https://gem5-review.googlesource.com/c/15716
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agomem-ruby: Fixing MESI Three Level
Pouya Fotouhi [Sat, 19 Jan 2019 23:41:37 +0000 (15:41 -0800)]
mem-ruby: Fixing MESI Three Level

Adding back some changes done in patch 676ae57827.
Transient state IS_I, STALE_DATA, Data_Stale event are necessary.

Issue: (cacheline A, initial state for P0 and P1 is I)
|   P0   |   P1   |
|GETX (A)|        |
|        |GETS (A)|
|Inv_All |        |
P1 never sends the ACK - deadlock
It should ACK, later upon data use it as stale data, and got to I.

Solution:
P1(A):
GETS:    I->IS
Inv_All: IS->IS_I, Send ACK
Data:    IS_I->I, STALE_DATA to L0

Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Change-Id: I1e7b2c05439d08579c68d8eb444e0f332e75e07f
Reviewed-on: https://gem5-review.googlesource.com/c/15715
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agosystemc: config: Don't inject a custom argv[0] in sc_main.py.
Gabe Black [Tue, 12 Feb 2019 00:51:16 +0000 (16:51 -0800)]
systemc: config: Don't inject a custom argv[0] in sc_main.py.

argv[0] is already part of sys.argv, so we don't need to add an
additional argument in front of sys.argv.

The argv[0] which is used in gem5 config scripts is the name of the
config script itself. While it might seem a little odd for the name of
a systemc program to end in .py, it's as arbitrary as any other name,
and generally shouldn't cause a problem. If some other more
sophisticated mechanism for setting argv[0] is necessary, then the user
can write a very slightly more complicated version of this script with
additional logic.

Change-Id: Ifd5d8a02d3cd5db76054151ed6c7a7b1f8495fa8
Reviewed-on: https://gem5-review.googlesource.com/c/16342
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agosystemc: configs: Add a very simple config which just runs sc_main.
Gabe Black [Sat, 9 Feb 2019 12:17:00 +0000 (04:17 -0800)]
systemc: configs: Add a very simple config which just runs sc_main.

This config will just run the sc_main function (which must have been
provided in c++ somehow), passing through any of the scripts command
line arguments to sc_main.

Needing to do this sort of thing is common enough that there should be
a canned config which supports it.

Change-Id: I8f88ba4776b9ec919dd8145a58cd856e11ac4e77
Reviewed-on: https://gem5-review.googlesource.com/c/16287
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agosystemc: Change the type of a loop counter to avoid a warning.
Gabe Black [Sat, 9 Feb 2019 12:01:48 +0000 (04:01 -0800)]
systemc: Change the type of a loop counter to avoid a warning.

g++ complained about comparing an signed int loop counter with the
return value of a size() function. This change changes it to an
unsigned to make g++ happy/quiet.

Change-Id: I28fa79c448465b24d77b5623860f9b991f313561
Reviewed-on: https://gem5-review.googlesource.com/c/16286
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agoscons: Change an = to a += when accumulating sources from filters.
Gabe Black [Sat, 9 Feb 2019 09:37:48 +0000 (01:37 -0800)]
scons: Change an = to a += when accumulating sources from filters.

The loop accidentally used a = when it should have used a +=, meaning
only the sources from the final filter would be used.

Change-Id: Ie066a5f85696f05d9ad3cf61f928b12deb39475b
Reviewed-on: https://gem5-review.googlesource.com/c/16285
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agosystemc: scons: Specify RPATH as a list.
Gabe Black [Sat, 9 Feb 2019 09:35:28 +0000 (01:35 -0800)]
systemc: scons: Specify RPATH as a list.

scons will attempt to use insert() on the value of RPATH when adding in
additional values. That will fail if RPATH is a Literal.

Change-Id: I9da75c6b189f12843a3452cdf92f7b56c0ec340b
Reviewed-on: https://gem5-review.googlesource.com/c/16284
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agocpu: Proposal for changing the indirect branch predictor interface
Jairo Balart [Sun, 6 Jan 2019 19:35:11 +0000 (20:35 +0100)]
cpu: Proposal for changing the indirect branch predictor interface

Now the indirect branch predictor handles its own GHR instead of getting
the one from the direction predictor.

Also, now the commit method of the indirect predictor is called for every
pending branch on an update, as the indirect predictors may want to update
their interal structures/histories with the information of each branch.

Change-Id: I7053fbea42a53960a3bc1ba32912cc99c160511e
Reviewed-on: https://gem5-review.googlesource.com/c/15318
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agoriscv: fix AMO, LR and SC instructions
Tuan Ta [Tue, 13 Feb 2018 04:13:34 +0000 (23:13 -0500)]
riscv: fix AMO, LR and SC instructions

(1) Atomic Memory Operation (AMO)

This patch changes how RISC-V AMO instructions are implemented. For each
AMO, instead of issuing a locking load and an unlocking store request to
downstream memory system, this patch issues a single memory request that
contains a corresponding AtomicOpFunctor to the memory system. Once the
memory system receives the request, the atomic operation is executed in
one single step.

This patch also changes how AMO instructions handle acquire and release
flags in AMOs (e.g., amoadd.aq and amoadd.rl). If an AMO is associated
with an acquire flag, a memory fence is inserted after the AMO completes
as a micro-op. If an AMO is associated with a release flag, another
memory fence is inserted before the AMO executes. If both flags are
specified, the AMO is broken down into a sequence of 3 micro-ops:
mem fence -> atomic RMW -> mem fence. This change makes this AMO
implementation comply to the release consistency model.

(2) Load-Reserved (LR) and Store-Conditional (SC)

Addresses locked by LR instructions are tracked in a stack data
structure. LR instruction pushes its target address to the stack, and SC
instruction pops the top address from the stack. As specified by RISC-V
ISA, a SC fails if its target address does not match with the most recent
LR.

Previously, there was a single stack for all hardware thread contexts.
A shared stack between thread contexts can lead to a infinite sequence
of failed SCs if LRs from other threads keep pushing new addresses to
this stack.

This patch gives each context its private stack to address the problem.

This patch also adds extra memory fence micro-ops to lr/sc to guarantee
a correct execution order of memory instructions with respect to release
consistency model.

Change-Id: I1e95900367c89dd866ba872a5203f63359ac51ae
Reviewed-on: https://gem5-review.googlesource.com/c/8189
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

5 years agocpu: support atomic memory request type with AtomicOpFunctor
Tuan Ta [Mon, 22 Jan 2018 18:12:50 +0000 (13:12 -0500)]
cpu: support atomic memory request type with AtomicOpFunctor

This patch enables all 4 CPU models (AtomicSimpleCPU, TimingSimpleCPU,
MinorCPU and DerivO3CPU) to issue atomic memory (AMO) requests to memory
system.

Atomic memory instruction is treated as a special store instruction in
all CPU models.

In simple CPUs, an AMO request with an associated AtomicOpFunctor is
simply sent to L1 dcache.

In MinorCPU, an AMO request bypasses store buffer and waits for any
conflicting store request(s) currently in the store buffer to retire
before the AMO request is sent to the cache. AMO requests are not buffered
in the store buffer, so their effects appear immediately in the cache.

In DerivO3CPU, an AMO request is inserted in the store buffer so that it
is delivered to the cache only after all previous stores are issued to
the cache. Data forwarding between between an outstanding AMO in the
store buffer and a subsequent load is not allowed since the AMO request
does not hold valid data until it's executed in the cache.

This implementation assumes that a target ISA implementation must insert
enough memory fences as micro-ops around an atomic instruction to
enforce a correct order of memory instructions with respect to its
memory consistency model. Without extra memory fences, this implementation
can allow AMOs and other memory instructions that do not conflict
(i.e., not target the same address) to reorder.

This implementation also assumes that atomic instructions execute within
a cache line boundary since the cache for now is not able to execute an
operation on two different cache lines in one single step. Therefore,
ISAs like x86 that require multi-cache-line atomic instructions need to
either use a pair of locking load and unlocking store or change the
cache implementation to guarantee the atomicity of an atomic
instruction.

Change-Id: Ib8a7c81868ac05b98d73afc7d16eb88486f8cf9a
Reviewed-on: https://gem5-review.googlesource.com/c/8188
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agokern,sim: implement FUTEX_WAKE_OP
Moyang Wang [Mon, 2 Apr 2018 20:23:13 +0000 (16:23 -0400)]
kern,sim: implement FUTEX_WAKE_OP

This patch implements FUTEX_WAKE_OP operation in the futex syscall.
Below is its description:

int futex(int *uaddr, int futex_op, int val,
          const struct timespec *timeout,
          int *uaddr2, int val3);

This operation was added to support some user-space use cases where more
than one futex must be handled at the same time.  The most notable
example is the implementation of pthread_cond_signal(3), which requires
operations on two futexes, the one used to implement the mutex and the
one used in the implementation of the wait queue associated with the
condition variable.  FUTEX_WAKE_OP allows such cases to be implemented
without leading to high rates of contention and context switching.

Reference: http://man7.org/linux/man-pages/man2/futex.2.html

Change-Id: I215f3c2a7bdc6374e5dfe06ee721c76933a10f2d
Reviewed-on: https://gem5-review.googlesource.com/c/9630
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agosim, kern: support FUTEX_CMP_REQUEUE
Moyang Wang [Mon, 2 Apr 2018 20:23:02 +0000 (16:23 -0400)]
sim, kern: support FUTEX_CMP_REQUEUE

This patch supports FUTEX_CMP_REQUEUE operation. Below is its
description from Linux man page:

futex syscall: int futex(int *uaddr, int futex_op, int val,
                         const struct timespec *timeout,
                         int *uaddr2, int val3);

This operation first checks whether the location uaddr still contains
the value val3.  If not, the operation fails with the error EAGAIN.
Otherwise, the operation wakes up a maximum of val waiters that are
waiting on the futex at uaddr.  If there are more than val waiters, then
the remaining waiters are removed from the wait queue of the source
futex at uaddr and added to the wait queue of the target futex at
uaddr2.  The val2 argument specifies an upper limit on the number of
waiters that are requeued to the futex at uaddr2.

Reference: http://man7.org/linux/man-pages/man2/futex.2.html

Change-Id: I6d2ebd19a935b656d19d8342f7ab450c0d2031f4
Reviewed-on: https://gem5-review.googlesource.com/c/9629
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

5 years agosim: handle the case when there're not enough HW thread contexts
Tuan Ta [Mon, 2 Apr 2018 20:22:50 +0000 (16:22 -0400)]
sim: handle the case when there're not enough HW thread contexts

In SE mode, since there's no OS scheduler, the number of active SW
threads is limited by the number of HW thread contexts. Previously, if
there is no spare HW thread context, the simulator just fails and stops.
Instead, this patch returns EAGAIN error code from a clone syscall if
there's no available HW thread context. Then it's up to the simulated
program to handle the error.

Linux man page reference:
http://man7.org/linux/man-pages/man2/clone.2.html
http://man7.org/linux/man-pages/man2/fork.2.html

Change-Id: Ib4e092433e49de4dde376c8cb81f7d3f7851cbc0
Reviewed-on: https://gem5-review.googlesource.com/c/9628
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

5 years agoriscv: fixed syscall return value
Tuan Ta [Mon, 2 Apr 2018 20:22:30 +0000 (16:22 -0400)]
riscv: fixed syscall return value

In case of failure, a syscall returns a negative value encoding the
error code. This patch makes the risc-v implementation returns the
encoded value instead of its absolute value upon a failure of a syscall.

Change-Id: I6032b0337fe1cff5b326dbc6bb3b87a415f03300
Reviewed-on: https://gem5-review.googlesource.com/c/9627
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

5 years agocpu: fix how branching is handled when a thread is suspended in MinorCPU
Tuan Ta [Mon, 2 Apr 2018 20:22:16 +0000 (16:22 -0400)]
cpu: fix how branching is handled when a thread is suspended in MinorCPU

When a thread is suspended, all instructions after the suspension need
to be discarded since the thread will take a different execution stream
when it wakes up.

To do that, in MinorCPU, whenever a thread gets suspended, we change the
current execution stream by updating the current branch with
BranchData::SuspendThread reason.

Change-Id: I7cdcda22c1cf6e8ac8db8800b7d9ec052433fdf3
Reviewed-on: https://gem5-review.googlesource.com/c/9626
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agocpu: stop scheduling suspended threads in all stages of MinorCPU
Tuan Ta [Mon, 2 Apr 2018 20:22:01 +0000 (16:22 -0400)]
cpu: stop scheduling suspended threads in all stages of MinorCPU

This patch makes suspended threads non-schedulable in Fetch1, Fetch2,
Decode and Execute stages in MinorCPU.

Change-Id: Ie79857e13b7b782d9c58c32310993a132b609cf9
Reviewed-on: https://gem5-review.googlesource.com/c/9625
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agoriscv: ignore nanosleep syscall
Tuan Ta [Mon, 2 Apr 2018 20:21:46 +0000 (16:21 -0400)]
riscv: ignore nanosleep syscall

Change-Id: I564a09564da668a5db3e75f15b33efaca363d71a
Reviewed-on: https://gem5-review.googlesource.com/c/9624
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agosim,cpu: make exit_group halt all threads in a group
Tuan Ta [Mon, 2 Apr 2018 20:21:37 +0000 (16:21 -0400)]
sim,cpu: make exit_group halt all threads in a group

When a thread calls exit_group, in addition to halting the thread
itself, it needs to halt all other threads in its group (i.e., threads
sharing the same thread group ID). This patch enables threads to do
that.

Change-Id: Ib2e158fb27cf98843f177a64a2d643b1bbc94d03
Reviewed-on: https://gem5-review.googlesource.com/c/9623
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agoarch-riscv: initialize RISC-V's thread pointer register in clone syscall
Tuan Ta [Mon, 2 Apr 2018 20:21:28 +0000 (16:21 -0400)]
arch-riscv: initialize RISC-V's thread pointer register in clone syscall

This patch initializes thread pointer register to Thread Local Storage
(TLS)'s pointer given to a clone system call.

Change-Id: I03e2cf4763e6a0ed31f357772a513a05e1e3461b
Reviewed-on: https://gem5-review.googlesource.com/c/9622
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

5 years agosim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops
Tuan Ta [Mon, 2 Apr 2018 20:21:09 +0000 (16:21 -0400)]
sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops

This patch adds support for two operations in futex system call:
FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET. The two operations are used to
selectively wake up a certain thread waiting on a futex variable.

Basically each thread waiting on a futex variable is associated with a
bitset that is checked when another thread tries to wake up all threads
waiting on the futex variable.

Change-Id: I2300e53b144d8fae226423fa2efb0238c1d93ef9
Reviewed-on: https://gem5-review.googlesource.com/c/9621
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

5 years agocpu: fixed how O3 CPU executes an exit system call
Tuan Ta [Mon, 2 Apr 2018 19:20:02 +0000 (15:20 -0400)]
cpu: fixed how O3 CPU executes an exit system call

When a thread executed an exit syscall in SE mode, the thread context
was removed immediately in the same cycle, which left inflight squash
operations and trap event incomplete. The problem happened when a new
thread was assigned to the CPU later. The new thread started with some
incomplete transactions of the previous thread (e.g., squashing). This
problem could cause incorrect execution flow for the new thread (i.e.,
pc was not reset properly at the exit point), deadlock (i.e., some
stage-to-stage signals were not reset) and incorrect rename map between
logical and physical registers.

This patch adds a new state called 'Halting' to the thread context and
defers removing thread context from a CPU until a trap event initiated
by an exit syscall execution is processed. This patch also makes sure
that the removal of a thread context happens after all inflight
transactions of the to-be-removed thread in the pipeline complete.

Change-Id: If7ef1462fb8864e22b45371ee7ae67e2a5ad38b8
Reviewed-on: https://gem5-review.googlesource.com/c/8184
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agoarch-arm: Fix Virtual interrupts in AArch64
Giacomo Travaglini [Tue, 29 Jan 2019 13:22:11 +0000 (13:22 +0000)]
arch-arm: Fix Virtual interrupts in AArch64

Checking if cpsr.mode is equal to MODE_HYP doesn't work for AArch64.
This is because AArch64 is using different modes when in EL2, like EL2T
and EL2H.
This made Virtual Interrupts to be triggered even when executing in EL2
(hypervisor) whereas they should interrupt the scheduled VM only
(Non-Secure EL0 and EL1). This patch is fixing this by using the generic
currEL() helper for getting the exception level, which is working for
both AArch32 and AArch64.

Change-Id: I08640050ef06261f280ba1e63ca9f32c805af845
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16202
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agoarch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30
Giacomo Travaglini [Fri, 8 Feb 2019 11:20:57 +0000 (11:20 +0000)]
arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30

Change-Id: I649f8507ccb6c814b46b0b9b7e39dc912ecd9006
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16242

5 years agoarch-arm: Allow ArmPPI usage for PMU
Giacomo Travaglini [Thu, 31 Jan 2019 09:52:07 +0000 (09:52 +0000)]
arch-arm: Allow ArmPPI usage for PMU

Differently from ArmSPIs, ArmPPI interrupts need to be instantiated by
giving a ThreadContext pointer in the ArmPPIGen::get() method. Since the
PMU is registering the ThreadContext only at ISA startup time, ArmPPI
generation in deferred until the PMU has a non NULL pointer.

Change-Id: I17daa6f0e355363b8778d707b440cab9f75aaea2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16204
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agoarch-arm: Fix initialization of PMU counters
Ruben Ayrapetyan [Tue, 29 Jan 2019 19:19:51 +0000 (19:19 +0000)]
arch-arm: Fix initialization of PMU counters

A version of Linux kernel initializes counters before enabling them.
Without this change, gem5 overwrites the value of counter, which causes
incorrect counter values derived by kernel.

Change-Id: If0c515111103018d5f65f74434d7711a67aeaee4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16203
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agoconfigs, arch-arm: Using AddrRange for Realview mem_regions
Giacomo Travaglini [Mon, 4 Feb 2019 13:31:23 +0000 (13:31 +0000)]
configs, arch-arm: Using AddrRange for Realview mem_regions

Physical memory ranges are now saved in Realview objects as pairs of
addresses (start address and size). This patch is substituting them with
a single AddrRange object.

Change-Id: I02d25d557c5c54d062f0dccef8ede45744d0ce6b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16206
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agoconfigs: Unifiy interpretation of Realview mem_regions
Giacomo Travaglini [Mon, 4 Feb 2019 12:11:03 +0000 (12:11 +0000)]
configs: Unifiy interpretation of Realview mem_regions

In every arm platform which is making use of them, mem_regions are
interpreted as a pair of start address and size. However arm
SimpleSystem, which is using VExpress_GEM5_V1, is interpreting them as
start address and end address.  This patch is fixing this mismatch.

Change-Id: I0b2a2193cd07fbc5430f233438269a9c7c353df9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16205
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agoarch-riscv: Enable support for riscv 32-bit in SE mode.
Austin Harris [Thu, 27 Dec 2018 01:19:00 +0000 (19:19 -0600)]
arch-riscv: Enable support for riscv 32-bit in SE mode.

This patch splits up the riscv SE mode support for 32 and 64-bit.
A future patch will add support for decoding rv32 instructions.

Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/15355
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

5 years agoriscv: remove NonSpeculative flag from fence inst
Tuan Ta [Mon, 2 Apr 2018 19:19:51 +0000 (15:19 -0400)]
riscv: remove NonSpeculative flag from fence inst

Fence instruction origially had two flags NonSpeculative and
MemBarrier. In O3 model, MemBarrier instructions are inserted
into the instruction queue by the InstructionQueue::insertBarrier (at
src/cpu/o3/iew_impl.hh:1083). Barrier instructions are implicitly
assumed to be non-speculative.

Adding NonSpeculative flag to fence instruction makes it inserted into
the instruction queue twice (at src/cpu/o3/iew_impl.hh:1083 and :1111).
This can lead to a deadlock if both pointers to the instruction are not
cleared from the queue when the instruction retires.

This patch removes NonSpeculative flag from the fence inst.

Change-Id: I26573d12a0b52f43b73c0e51158286dc98d05ea4
Reviewed-on: https://gem5-review.googlesource.com/c/8183
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

5 years agocpu: fix how a thread starts up in MinorCPU
Tuan Ta [Mon, 2 Apr 2018 19:19:40 +0000 (15:19 -0400)]
cpu: fix how a thread starts up in MinorCPU

When a thread is activated by another thread calling a clone system
call, the child thread's context is initialized in the middle of the
clone system call and before the context is fully initialized.
Therefore, the child thread starts fetching an unitialized PC, which
could lead to a page fault.

This patch adds a pipeline wakeup event that is scheduled later in the
cycle when the thread is activated. This event ensures that the first
fetch only happens after the thread context is fully initialized
(e.g., in case of clone syscall, it is when the parent thread copies
its context over to the child thread).

When a thread first starts or wakes up, input queue to the Fetch2 stage
needs to be drained since the execution flow is likely to change and
previously fetched instructions in the queue may no longer be in the
correct flow. This patch dumps/drains all inputs in the input queue
of a thread context in the Fetch2 stage when the associated thread wakes
up.

Change-Id: Iad970638e435858b7289cd471158cc0afdbbb0e5
Reviewed-on: https://gem5-review.googlesource.com/c/8182
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

5 years agoarch-riscv: Initialize interrupt mask
Tuan Ta [Tue, 5 Feb 2019 15:08:10 +0000 (10:08 -0500)]
arch-riscv: Initialize interrupt mask

This patch initializes RISCV interrupt mask to 0.

Change-Id: I56289d9f3f319e239e305befea006a0ad4d86b75
Reviewed-on: https://gem5-review.googlesource.com/c/16162
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agoscons: fix unused auto-generated blob variable in clang
Ciro Santilli [Sat, 26 Jan 2019 13:16:17 +0000 (13:16 +0000)]
scons: fix unused auto-generated blob variable in clang

Since f2bda876f73af4ecc38406f3562a3d16fd28a5a9, the build system started
adding a length for generated blobs as in:

const std::size_t variable_len = 123;

There were two types of blob files, ones with a header and the ones
without.

The ones with the header, also include the header in the .cc of the blob,
which contains a declaration:

extern const std::size_t variable_len;

Therefore, the ones without header, don't have that extern declaration,
which makes them static according to the C++ standard.

clang then correctly interprets that as problematic due to
-Wunused-const-variable, while GCC does not notice this.

This patch removes the length declaration from the blob files that don't
have the header. Those files currently don't use the length.

Change-Id: I3fc61b28f887fc1015288857328ead2f3b34c6e6
Reviewed-on: https://gem5-review.googlesource.com/c/15955
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agosim: added missed macro definition on MacOS
Andrea Mondelli [Mon, 4 Feb 2019 20:12:40 +0000 (15:12 -0500)]
sim: added missed macro definition on MacOS

A recent patch add the use of the macro:
CMSG_ALIGN
This macro is not very cross-platform, and needs to be
defined according to the platform.

This patch defines the missing macro on MacOS.

Change-Id: I582f69e652dc060b4532358141179ad6d37eafc7
Reviewed-on: https://gem5-review.googlesource.com/c/16102
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

5 years agomisc: added missing override specifier
Andrea Mondelli [Mon, 4 Feb 2019 20:21:40 +0000 (15:21 -0500)]
misc: added missing override specifier

Added missing specifier for various virtual functions.

Change-Id: I4783e92d78789a9ae182fad79aadceafb00b2458
Reviewed-on: https://gem5-review.googlesource.com/c/16103
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agocpu: Made the Loop Predictor a SimObject
Javier Bueno [Mon, 28 Jan 2019 22:59:45 +0000 (23:59 +0100)]
cpu: Made the Loop Predictor a SimObject

The Loop Predictor implementation is now a SimObject so that other branch
predictors can easily use it (including LTAGE, which is now using it).
It has also been updated with the latest
available loop predictor implementation from Andre Seznec:

http://www.irisa.fr/alf/downloads/seznec/TAGE-GSC-IMLI.tar

Change-Id: I60ad079a2c49b00a1f84d5cfd3611631883a4b57
Reviewed-on: https://gem5-review.googlesource.com/c/15775
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agocpu: Made TAGE a SimObject that can be used by other predictors
Jairo Balart [Sat, 5 Jan 2019 09:24:17 +0000 (10:24 +0100)]
cpu: Made TAGE a SimObject that can be used by other predictors

The TAGE implementation is now a SimObject so that other branch predictors
can easily use it. It has also been updated with the latest available TAGE
implementation from Andre Seznec:

http://www.irisa.fr/alf/downloads/seznec/TAGE-GSC-IMLI.tar

Change-Id: I2251b8b2d7f94124f9955f52b917dc3b064f090e
Reviewed-on: https://gem5-review.googlesource.com/c/15317
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agoriscv: Get rid of ISA specific register types in Interrupts.
Austin Harris [Mon, 4 Feb 2019 23:48:52 +0000 (17:48 -0600)]
riscv: Get rid of ISA specific register types in Interrupts.

Change-Id: I5542649c6af27a286f276a289b86c40dd7e32abc
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/16122
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agomem-cache: Updated version of the Signature Path Prefetcher
Javier Bueno [Thu, 13 Dec 2018 10:38:15 +0000 (11:38 +0100)]
mem-cache: Updated version of the Signature Path Prefetcher

This implementation is based in the description available in:
  Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy,
  Chris Wilkerson, and Zeshan Chishti. 2016.
  Path confidence based lookahead prefetching.
  In The 49th Annual IEEE/ACM International Symposium on Microarchitecture
  (MICRO-49). IEEE Press, Piscataway, NJ, USA, Article 60, 12 pages.

Change-Id: I4b8b54efef48ced7044bd535de9a69bca68d47d9
Reviewed-on: https://gem5-review.googlesource.com/c/14819
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

5 years agodev, arm: Removed contextId variable
Anouk Van Laer [Tue, 22 Jan 2019 18:08:44 +0000 (18:08 +0000)]
dev, arm: Removed contextId variable

The contextId variable is only used by the debug flag and will prevent
a more optimised binary (i.e. fast) from compiling.

Change-Id: I6cefb5bc06d0d4b415df62f1278db53ba309fb87
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16042
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

5 years agocpu, arch: Replace the CCReg type with RegVal.
Gabe Black [Thu, 22 Nov 2018 00:20:57 +0000 (16:20 -0800)]
cpu, arch: Replace the CCReg type with RegVal.

Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.

Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agopython: Remove getCode() type workaround
Andreas Sandberg [Mon, 28 Jan 2019 16:12:18 +0000 (16:12 +0000)]
python: Remove getCode() type workaround

Python 2.7 requires a workaround when wrapping exit objects to
explicitly convert the return of getCode() to int to not confuse
sys.exit. This workaround isn't needed and doesn't work on Python 3
since it doesn't have a separate long integer type.

Change-Id: I57bc3fd8f4699676c046ece8a52baa2796959ffd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15978
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
5 years agosim: Prepare C++ side for Python 3
Andreas Sandberg [Fri, 25 Jan 2019 11:13:38 +0000 (11:13 +0000)]
sim: Prepare C++ side for Python 3

Python 3 uses wide strings instead of ordinary strings for many
APIs. Add the necessary conversions to comply with the new API.

Change-Id: I6f45c9c532537d50d54b542f34eb8fd8cb375874
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15977
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
5 years agotests: Add a helper to run external scripts
Andreas Sandberg [Mon, 28 Jan 2019 16:50:35 +0000 (16:50 +0000)]
tests: Add a helper to run external scripts

Some tests are really just a wrapper around a test script in
configs/. Add a helper method to wrap these scripts to make sure they
are executed in a consistent environment. This wrapper sets up a
global environment that is identical to that created by main() when it
executes the script. Unlike the old wrappers, it updates the module
search path to make relative imports work correctly in Python 3.

Change-Id: Ie9f81ec4e2689aa8cf5ecb9fc8025d3534b5c9ca
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15976
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

5 years agotests: Don't override tick rate in Ruby tests
Andreas Sandberg [Sun, 27 Jan 2019 11:12:15 +0000 (11:12 +0000)]
tests: Don't override tick rate in Ruby tests

Most Ruby tests assume that the highest frequency in the system under
test is 1GHz and limits the global tick rate to this frequency. This
assumption is broken since the default Ruby configuration scripts
clock the CPU at 2Ghz, which results in warnings and sometimes
incorrect behaviour.

Change-Id: I4b204660862ce3b0ea4a13df42caacd4398fef8c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15975
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
5 years agopower: Get rid of some ISA specific register types.
Gabe Black [Tue, 20 Nov 2018 03:12:28 +0000 (19:12 -0800)]
power: Get rid of some ISA specific register types.

Change-Id: If63acb10705a9f442255680917d16630748ca8e1
Reviewed-on: https://gem5-review.googlesource.com/c/14465
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agonull: Get rid of some register type definitions.
Gabe Black [Tue, 20 Nov 2018 03:01:13 +0000 (19:01 -0800)]
null: Get rid of some register type definitions.

These are no longer used.

Change-Id: Ic6a35e8a7e25eab9d21a3eef683914e01508c6d7
Reviewed-on: https://gem5-review.googlesource.com/c/14463
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agomips: Stop using architecture specific register types.
Gabe Black [Tue, 20 Nov 2018 02:37:16 +0000 (18:37 -0800)]
mips: Stop using architecture specific register types.

Change-Id: I764f6eea214ba4e03cc0fe19a21abcb0ebd04408
Reviewed-on: https://gem5-review.googlesource.com/c/14462
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agoalpha: Stop using architecture specific register types.
Gabe Black [Tue, 20 Nov 2018 02:28:12 +0000 (18:28 -0800)]
alpha: Stop using architecture specific register types.

Change-Id: I4052000014c9f6f9ecefd3f37e58595c61599484
Reviewed-on: https://gem5-review.googlesource.com/c/14461
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agox86: Stop using/defining some ISA specific register types.
Gabe Black [Wed, 21 Nov 2018 00:58:19 +0000 (16:58 -0800)]
x86: Stop using/defining some ISA specific register types.

These have been replaced with the generic RegVal type.

Change-Id: I75c1134212067dea43aa0903d813633e06f3d6c6
Reviewed-on: https://gem5-review.googlesource.com/c/14476
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agoriscv: Get rid of some ISA specific register types.
Gabe Black [Tue, 20 Nov 2018 03:29:52 +0000 (19:29 -0800)]
riscv: Get rid of some ISA specific register types.

Change-Id: Ie812cf1d42536094273ba2ec731c16cca38db100
Reviewed-on: https://gem5-review.googlesource.com/c/14466
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

5 years agoarch: cpu: Rename *FloatRegBits* to *FloatReg*.
Gabe Black [Tue, 20 Nov 2018 02:14:16 +0000 (18:14 -0800)]
arch: cpu: Rename *FloatRegBits* to *FloatReg*.

Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.

Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>