Benjamin Herrenschmidt [Sun, 4 Sep 2022 14:21:47 +0000 (00:21 +1000)]
Fix build of core_dram_tb and dram_tb and fix tracing
We disabled --trace by default, so we need to stop linking verilated_vcd_c.o
as it doesn't exist in that case.
While at it, make a Makefile variable to enable/disable verilator tracing
and add a couple of generics to those test benches to control tracing
in the L2 and in litedram.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Sun, 4 Sep 2022 14:22:19 +0000 (00:22 +1000)]
Ignore vunit_out in git
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Michael Neuling [Thu, 1 Sep 2022 01:08:59 +0000 (11:08 +1000)]
Merge pull request #401 from shenki/dcscm
Add Antmicro Artix DC-SCM support
Joel Stanley [Tue, 16 Aug 2022 05:14:44 +0000 (15:14 +1000)]
openocd: Add Artix DC-SCM cable type
The Antmicro Artix DC-SCM uses the following FTDI part:
0403:6011 Future Technology Devices International, Ltd FT4232H Quad HS USB-UART/FIFO IC
To use:
$ openocd/flash-arty -c antmicro-artix-dc-scm -f a100 -t bin -a 0x300000 ~/u-boot
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Thu, 25 Aug 2022 09:51:07 +0000 (19:51 +1000)]
antmicro-artix-dc-scm: Add liteeth
As with the DRAM configuration, the DC-SCM board uses the same PHY as
the Nexys Video and works with it's generated VHDL.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Thu, 25 Aug 2022 09:50:47 +0000 (19:50 +1000)]
antmicro-artix-dc-scm: Add Ethernet pins
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Thu, 25 Aug 2022 08:27:19 +0000 (18:27 +1000)]
antmicro-artix-dc-scm: Enable SPI flash
Load from 3MB as the flash is only 4MB on this board.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Thu, 25 Aug 2022 08:26:53 +0000 (18:26 +1000)]
antmicro-artix-dc-scm: Formatting to match top-arty
Make it easier to follow what needs to be updated.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Thu, 25 Aug 2022 08:26:02 +0000 (18:26 +1000)]
antmicro-artix-dc-scm: Add SPI flash pins
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Thu, 25 Aug 2022 09:51:55 +0000 (19:51 +1000)]
antmicro-artix-dc-scm: Update DRAM properties
Most pins are set to SSTL15, but litex generates SSTL135.
This should silence a vivado warning.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Paul Mackerras [Wed, 27 Oct 2021 03:58:34 +0000 (14:58 +1100)]
antmicro-artix-dc-scm: Add DRAM support
This uses the exact same gateware as the nexys video, since the DRAM
connection is identical to the nexys video down to the pin assignments
on the FPGA. The only minor difference is that the DRAM chip on the
dc-scm is a MT41K256M16TW vs. a ...HA part on the nexys video.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
[joel: rebase and tweaks]
Signed-off-by: Joel Stanley <joel@jms.id.au>
Michael Neuling [Wed, 20 Oct 2021 23:50:46 +0000 (10:50 +1100)]
Add Antmicro Artix DC SCM hello world support
works with:
fusesoc build --target=antmicro-artix-dc-scm microwatt --ram_init_file=../hello_world/hello_world.hex
Signed-off-by: Michael Neuling <mikey@neuling.org>
[joel: Fixes and updates]
Signed-off-by: Joel Stanley <joel@jms.id.au>
Anton Blanchard [Tue, 30 Aug 2022 01:49:40 +0000 (11:49 +1000)]
Merge pull request #400 from mikey/githash
syscon: Implement a register for storing git hash info
Michael Neuling [Mon, 29 Aug 2022 05:20:24 +0000 (15:20 +1000)]
Merge pull request #399 from ozbenh/misc
Fix PLRU
Dan Horák [Tue, 1 Sep 2020 20:43:50 +0000 (22:43 +0200)]
hello_world: Debug print the gitinfo syscon register
.oOOo.
." ".
; .mw. ; Microwatt, it works.
. ' ' .
\ || / HDL Git SHA1:
211d23c4ad4fb5-dirty
;..;
;..;
`ww'
Signed-off-by: Dan Horák <dan@danny.cz>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Dan Horák [Fri, 28 Aug 2020 12:24:07 +0000 (14:24 +0200)]
syscon: Implement a register for storing git hash info
It also stores the dirty status so that's known.
This does some Makefile tricks so that we only rebuild when the git
hash changes. This avoids rebuilding the world every time we run
make.
Also adds fusesoc generator, so that should continue to work as
before.
Signed-off-by: Dan Horák <dan@danny.cz>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Benjamin Herrenschmidt [Thu, 25 Aug 2022 03:14:20 +0000 (13:14 +1000)]
Fix PLRU
Jacob Lifshay found a couple of issues with the PLRU implementation:
- The tree array is one bit too long. This is harmless as this bit is never
accessed and thus should be optimized out
- The PLRU read is using the wrong nodes when going down the tree, which leads
to incorrect results.
This fixes it and improves the test bench a bit. I have verified the expected
output using a hand-written tree states, observed the mismatch with the
current implementation and verified the fix.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Sun, 14 Aug 2022 23:32:54 +0000 (09:32 +1000)]
Merge pull request #397 from mikey/metavalue-counts
tests: Update metavalues test count
Michael Neuling [Sat, 13 Aug 2022 05:52:04 +0000 (15:52 +1000)]
tests: Update metavalues test count
With Paulus changes in PR #396 merged in
5c6d57de30, we can now reduce
the metavalue test counts.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Sat, 13 Aug 2022 05:45:57 +0000 (15:45 +1000)]
Merge pull request #396 from paulusmack/reduce-meta
Reduce metavalue warnings
Paul Mackerras [Fri, 12 Aug 2022 12:19:37 +0000 (22:19 +1000)]
execute1: Reduce metavalue warnings
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 12 Aug 2022 09:47:45 +0000 (19:47 +1000)]
loadstore1: Reduce metavalue warnings
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 12 Aug 2022 09:46:45 +0000 (19:46 +1000)]
decode2: Reduce metavalue warnings
Explicitly check for undefined values and propagate them.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 12 Aug 2022 09:46:09 +0000 (19:46 +1000)]
core_debug: Reduce metavalue warnings
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 12 Aug 2022 09:42:35 +0000 (19:42 +1000)]
icache: Reduce metavalue warnings
As in dcache, this changes most signals declared with integer type to
be unsigned bit vectors instead. Some code has been rearranged to do
to_integer() or equality comparisons only when the relevant signals
should be well defined. Non-fatal asserts have been sprinkled
throughout to assist with determining the cause of warnings from
library functions (primarily NUMERIC_STD.TO_INTEGER and
NUMERIC_STD."=").
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 12 Aug 2022 09:38:16 +0000 (19:38 +1000)]
dcache: Reduce metavalue warnings
Among other changes, this makes the things that were previously
declared as signals of integer base type to be unsigned, since
unsigned can carry metavalues, and hence we can get the checking for
metavalues closer to the uses and therefore restrict the checking to
the situations where the signal really ought to be well defined.
We now have a couple more signals that indicate request validity to
help with that.
Non-fatal asserts have been sprinkled throughout to assist with
determining the cause of warnings from library functions (primarily
NUMERIC_STD.TO_INTEGER and NUMERIC_STD."=").
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Michael Neuling [Wed, 10 Aug 2022 05:33:15 +0000 (15:33 +1000)]
Merge pull request #382 from paulusmack/master
Decode in block RAM and other improvements
Michael Neuling [Wed, 10 Aug 2022 02:43:29 +0000 (12:43 +1000)]
Merge pull request #392 from paulusmack/fix-branch-alias
fetch1: Fix bug where BTC entries don't match on MSR[IR]
Paul Mackerras [Wed, 10 Aug 2022 02:03:36 +0000 (12:03 +1000)]
multiply_tb: Fix multiply_tb.vhdl for the new multiplier interface
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Wed, 10 Aug 2022 01:33:10 +0000 (11:33 +1000)]
execute1: Make it clear that divide logic is not included when HAS_FPU=true
This adds a "not HAS_FPU" condition in a few places to make it obvious
that logic to interface to the divide unit is not included when we
have an FPU.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 19 Jul 2022 02:29:47 +0000 (12:29 +1000)]
Remove option for "short" 16x16 bit multiplier
Now that we have a 33 bit x 33 bit signed multiplier in execute1,
there is really no need for the 16 bit multiplier. The coremark
results are just as good without it as with it. This removes the
option for the sake of simplicity.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Michael Neuling [Wed, 10 Aug 2022 00:29:59 +0000 (10:29 +1000)]
Merge branch 'fix-branch-alias' into branch-alias
Merging Anton's test case for this.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Wed, 10 Aug 2022 00:25:59 +0000 (10:25 +1000)]
Merge pull request #388 from antonblanchard/trace-test
tests/trace: Test trace vs system call interrupt
Paul Mackerras [Wed, 10 Aug 2022 00:13:50 +0000 (10:13 +1000)]
fetch1: Fix bug where BTC entries don't match on MSR[IR]
This fixes a bug in the BTC where entries created for a given address
when MSR[IR] = 0 are used when MSR[IR] = 1 and vice-versa. The fix is
to include r.virt_mode (which mirrors MSR[IR]) in the tag portion of
the BTC.
Fixes: 0fb207be6069 ("fetch1: Implement a simple branch target cache", 2020-12-19)
Reported-by: Anton Blanchard <anton@linux.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 8 Aug 2022 12:26:39 +0000 (22:26 +1000)]
Change the multiplier interface to support signed multipliers
This adds an 'is_signed' signal to MultiplyInputType to indicate
whether the data1 and data2 fields are to be interpreted as signed or
unsigned numbers.
The 'not_result' field is replaced by a 'subtract' field which
provides a more intuitive interface for requesting that the product be
subtracted from the addend rather than added, i.e. subtract = 1 gives
C - A * B, vs. subtract = 0 giving C + A * B. (Previously the users
of the multipliers got the same effect by complementing the addend and
setting not_result = 1.)
The is_32bit field is removed because it is no longer used now that we
have a separate 32-bit multiplier.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Anton Blanchard [Tue, 9 Aug 2022 10:32:52 +0000 (20:32 +1000)]
Add branch alias test
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Paul Mackerras [Mon, 8 Aug 2022 07:06:46 +0000 (17:06 +1000)]
xilinx_mult: Prepare for doing signed multiplication
This rearranges the way that partial products are generated and summed
so that the partial products that could be negative in a signed
multiplier are now sign-extended. The inputs are still zero-extended,
however.
The overflow detection logic now only detects 64-bit overflow, since
32-bit multiplications are handled in a separate multiplier.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 16 Jul 2022 01:49:28 +0000 (11:49 +1000)]
execute1: Add a pipelined 33-bit signed multiplier
This adds a pipelined 33-bit by 33-bit signed multiplier with one
cycle latency to the execute pipeline, and uses it for the mullw,
mulhw and mulhwu instructions. Because it has one cycle of latency we
can assume that its result is available in the second execute stage
without needing to add busy logic to the second stage.
This adds both a generic version of the multiplier and a
Xilinx-specific version using four DSP slices of the Artix-7.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 4 Aug 2022 05:25:06 +0000 (15:25 +1000)]
predecode: Add more comments to row_predecode_rom and insn_code values
This adds comments to row_predecode_rom to aid understanding how the
columns in the second half of the table are allocated to different
primary opcodes, and to the insn_code values to assist in locating the
code with a given numeric value. No code change.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 4 Aug 2022 05:17:25 +0000 (15:17 +1000)]
icache: Log 36 bits of instruction rather than 32
This expands the field in the log buffer that stores the instruction
fetched from the icache to 36 bits, so that we get the insn_code and
illegal instruction indication. To do this, we reclaim 3 unused bits
from execute1's portion and one other unused bit (previously just set
to 0 in core.vhdl).
This also alters the trigger behaviour to stop after one quarter of
the log buffer has been filled with samples after the trigger, or 256
entries, whichever is less. This is to ensure that the trigger event
doesn't get overwritten when the log buffer is small.
This updates fmt_log to the new log format. Valid instructions are
printed as a decimal insn_code value followed by the bottom 26 bits of
the instruction. Illegal instructions are printed as "ill" followed
by the full 32 bits of the instruction.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 4 Aug 2022 04:57:12 +0000 (14:57 +1000)]
predecode: Work around apparent yosys/nextpnr bug
This rearranges the synchronous process here to avoid setting fields
of pred(i) to zero or INSN_illegal when valid_in is '0'.
Experimentally, on ECP5 this acts like an asynchronous reset rather
than a synchronous reset.
Instead, handle possible indeterminate input for simulation by making
the maj_predecode and row_predecode fields of predec_t be unsigned
rather than insn_code (an enumerated type), and setting them to X when
the input word is indeterminate.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 29 Jul 2022 10:29:26 +0000 (20:29 +1000)]
Pre-decode instructions when writing them to icache
This splits out the decoding done in the decode0 step into a separate
predecoder, used when writing instructions into the icache. The
icache now holds 36 bits per instruction rather than 32. For valid
instructions, those 36 bits comprise the bottom 26 bits of the
instruction word, a 9-bit insn_code value (which uniquely identifies
the instruction), and a zero in the MSB. For illegal instructions,
the MSB is one and the full instruction word is in the bottom 32 bits.
Having the full instruction word available for illegal instructions
means that it can be printed in the log when simulating, or in future
could be placed in the HEIR register.
If we don't have an FPU, then the floating-point instructions are
regarded as illegal. In that case, the insn_code values would fit
into 8 bits, which could be used in future to reduce the size of
decode_rom from 512 to 256 entries.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 28 Jul 2022 10:28:41 +0000 (20:28 +1000)]
Eliminate use of primary opcode outside of decode1
This changes code that previously looked at the primary opcode (bits
26 to 31) of the instruction to use other methods, in places other
than in stage0 of decode1.
* Extend rc_t to have a new value, RCOE, indicating that the
instruction has both Rc and OE bits.
* Decode2 now tells execute1 whether the instruction has a third
operand, used for distinguishing between multiply and multiply-add
instructions.
* The invert_a field of the decode ROM is overloaded for load/store
instructions to indicate cache-inhibited loads and stores.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 28 Jul 2022 09:00:04 +0000 (19:00 +1000)]
decode1: Divide insn_code values into ranges to indicate register usage
This lets us compute r_out.reg_*_addr and r_out.read_2_enable values
without needing access to the primary opcode value. We also have that
non-FP instructions are < 256.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 26 Jul 2022 08:21:19 +0000 (18:21 +1000)]
decode1: Split instruction decoding into two steps
This reduces the block RAM requirements for instruction decoding by
splitting it into two steps. The first, in a new pipeline stage
called decode0 (implemented by code in decode1.vhdl) maps the
instruction to a 9-bit instruction code using major and row decode
ROMs. The second maps the 9-bit code to the final decode_rom_t (about
44 bits wide). Branch prediction done in decode is now done in
decode0 rather than decode1.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 26 Jul 2022 04:55:29 +0000 (14:55 +1000)]
decode1: Use block RAMs in decode
This combines the various decode arrays in decode1 into two, one
indexed by the major opcode (bits 31--26 of the instruction) together
with bits 4--0 of the instruction, and the other indexed mostly by the
minor opcode (bits 10--1), with some swizzles to accommodate the
relevant parts of the minor opcode space for opcodes 19, 31, 59 and 63
within a 2k entry ROM (11 address bits). These are called the "major"
and the "row" decode ROMs respectively. (Bits 10--6 of the
instruction are called the "row index", and bits 5--1, or 5--0 for
some opcodes, are called the "column index", because of the way the
opcode maps in the ISA are laid out.)
Both ROMs are looked up each cycle and the result from one or other,
or from an override in ri.override_decode, are selected after a clock
edge.
This uses quite a lot of BRAM resources. In future a predecode step
will reduce the BRAM usage substantially.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 29 Jul 2022 23:42:19 +0000 (09:42 +1000)]
decode2: Decode unit and single-pipe attributes for mfspr/mtspr in decode2
Instead of doing that in decode1. That lets us get rid of the
force_single and override_unit fields of reg_internal_t in decode1,
which will simplify following changes to decode1.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 27 May 2022 12:23:50 +0000 (22:23 +1000)]
FPU: Set sign of 0 result of subtraction in pack_dp
When a floating-point subtraction results in a zero result, the sign
of the result is required to be positive in all rounding modes except
the round to minus infinity mode, when it is negative. Consolidate
the logic for doing this in one place, in the pack_dp function,
instead of having it at each place where a zero result is generated.
Since fnmadd[s] and fnmsub[s] negate the result after this rule has
been applied, we use the r.negate signal to indicate a negation which
is now done in pack_dp. Thus the EXC_RESULT state no longer uses
r.negate, and in fact doesn't set v.result_sign at all; that is now
done in the states that lead into EXC_RESULT.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 21 May 2022 09:36:17 +0000 (19:36 +1000)]
FPU: Simplify IDLE state code
Do more decoding of the instruction ahead of the IDLE state
processing so that the IDLE state code becomes much simpler.
To make the decoding easier, we now use four insn_type_t codes for
floating-point operations rather than two. This also rearranges the
insn_type_t values a little to get the 4 FP opcode values to differ
only in the bottom 2 bits, and put OP_DIV, OP_DIVE and OP_MOD next to
them.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 14 May 2022 11:46:40 +0000 (21:46 +1000)]
FPU: Make an explicit exponent data path
With this, the large case statement sets values for a set of control
signals, which then control multiplexers and adders that generate
values for v.result_exp and v.shift. The plan is for the case
statement to turn into a microcode ROM eventually.
The value of v.result_exp is the sum of two values, either of which
can be negated (but not both). The first value can be chosen from the
result exponent, A exponent, B exponent arithmetically shifted right
one bit, or 0. The second value can be chosen from new_exp (which is
r.result_exp - r.shift), B exponent, C exponent or a constant. The
choices for the constant are 0, 56, the maximum exponent (max_exp) or
the exponent bias for trap-enabled overflow conditions (bias_exp).
These choices are controlled by the signals re_sel1, re_neg1, re_sel2
and re_neg2, and the sum is written into v.result_exp if re_set_result
is 1.
For v.shift we also compute the sum of two values, either of which
can be negated (but not both). The first value can be chosen from
new_exp, B exponent, r.shift, or 0. The second value can be chosen
from the A exponent or a constant. The possible constants are 0, 1,
4, 8, 32, 52, 56, 63, 64, or the minimum exponent (min_exp). These
choices are controlled by the signals rs_sel1, rs_neg1, rs_sel2 and
rs_neg2. After the adder there is a multiplexer which selects either
the sum or a shift count for normalization (derived from a count
leading zeroes operation on R) to be written into v.shift. The
count-leading-zeroes result does not go through the adder for timing
reasons.
In order to simplify the logic and help improve timing, settings of
the control signals have been made unconditional in a state in many
places, even if those settings are only required when some condition
is met.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 14 May 2022 01:59:14 +0000 (11:59 +1000)]
FPU: Minor fix and simplifications
In preparation for an explicit exponent data path. The fix is that
fre[s] needs to negate the exponent after renomalization rather than
before, otherwise the exponent adjustment done by the renormalization
is in the wrong direction.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 28 Jul 2022 22:27:10 +0000 (08:27 +1000)]
loadstore1: Simplify address generation in OP_FETCH_FAILED case
Instead of having a multiplexer in loadstore1 in order to be able to
put the instruction address into v.addr, we now set decode.input_reg_a
to CIA in the decode table entry for OP_FETCH_FAILED. That means that
the operand selection machinery in decode2 will supply the instruction
address to loadstore1 on the lv.addr1 input and no special case is
needed in loadstore1. This saves a few LUTs (~40 on the Artix-7).
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 28 Jul 2022 10:46:59 +0000 (20:46 +1000)]
Remove leftover logic for 16-byte loads and stores
This removes some logic that was previously added for the 16-byte
loads and stores (lq, lqarx, stq, stqcx.) and not completely removed
in commit
c9e838b6560f ("Remove support for lq, stq, lqarx and
stqcx.", 2022-06-04).
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 9 Aug 2022 09:48:30 +0000 (19:48 +1000)]
writeback: Eliminate unintentional inferred latch
By not assigning to interrupt_out.srr1 in some circumstances, the
writeback_1 process creates an inferred latch, which is not
desirable. Eliminate it by restructuring the code so
interrupt_out.srr1 is always set, to zeroes if nothing else.
Fixes: bc4d02cb0dcc ("Start removing SPRs from register file", 2022-07-12)
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Michael Neuling [Tue, 9 Aug 2022 06:23:37 +0000 (16:23 +1000)]
Merge pull request #390 from shenki/fix-whide-warnings
Fix -Whide warnings
Anton Blanchard [Tue, 9 Aug 2022 04:15:56 +0000 (14:15 +1000)]
Merge pull request #389 from paulusmack/fix-sc
execute1: Fix trace interrupt on sc instruction
Anton Blanchard [Mon, 8 Aug 2022 21:08:02 +0000 (07:08 +1000)]
tests/trace: Test trace vs system call interrupt
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Paul Mackerras [Tue, 9 Aug 2022 02:30:48 +0000 (12:30 +1000)]
execute1: Fix trace interrupt on sc instruction
This fixes a bug which causes a trace interrupt to store the wrong
value in SRR0 in the case where the instruction that has just
completed is followed by a sc (system call) instruction. What happens
is that first the traced instruction sets ex1.trace_next. Then, when
the sc instruction following it comes in, the execute1_actions process
sets v.e.last_nia to next_nia because it is an sc instruction, even
though it is not going to be executed -- we are going to take the
trace interrupt instead. Then when the trace interrupt is taken, we
incorrectly set SRR0 to the incremented address (the address of the
instruction following the sc).
To fix this, we have execute1_actions set a new flag if the current
instruction is sc, and only set v.e.last_nia to next_nia if we
actually execute the sc (in the "if go = '1'" case).
Fixes: 813e2317bf1f ("execute1: Restructure to separate out execution of side effects", 2022-06-18)
Reported-by: Anton Blanchard <anton@linux.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Joel Stanley [Mon, 8 Aug 2022 10:54:54 +0000 (20:24 +0930)]
soc: Fix -Whide warning
soc.vhdl:847:9:warning: declaration of "uart1" hides if generate statement [-Whide]
uart1: uart_top
^
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Mon, 8 Aug 2022 10:51:27 +0000 (20:21 +0930)]
xics: Fix -Whide warnings
xics.vhdl:83:25:warning: declaration of "v" hides variable "v" [-Whide]
function bswap(v : in std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
xics.vhdl:84:22:warning: declaration of "r" hides signal "r" [-Whide]
variable r : std_ulogic_vector(31 downto 0);
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Fri, 5 Aug 2022 05:42:45 +0000 (15:12 +0930)]
fpu: Fix -Whide warnings
fpu.vhdl:513:18:warning: declaration of "result" hides signal "result" [-Whide]
variable result : std_ulogic_vector(63 downto 0);
Signed-off-by: Joel Stanley <joel@jms.id.au>
Michael Neuling [Mon, 8 Aug 2022 05:54:14 +0000 (15:54 +1000)]
Merge pull request #387 from antonblanchard/gitignore
Add litesdcard/build to gitignore
Anton Blanchard [Sun, 7 Aug 2022 07:44:04 +0000 (17:44 +1000)]
Add litesdcard/build to gitignore
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Paul Mackerras [Fri, 5 Aug 2022 00:52:31 +0000 (10:52 +1000)]
Merge pull request #384 from antonblanchard/litedram-update
Litedram update
Anton Blanchard [Thu, 4 Aug 2022 11:26:17 +0000 (21:26 +1000)]
litedram: Regenerate
Regenerate from upstream litex. Something in the update has improved
memory read and write performance quite a lot on my Nexys Video:
Before:
Write speed: 83.2MiB/s
Read speed: 140.4MiB/s
After:
Write speed: 352.1MiB/s
Read speed: 218.5MiB/s
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 4 Aug 2022 11:25:13 +0000 (21:25 +1000)]
litedram: MIGEN_GIT_SHA1 no longer defined
MIGEN_GIT_SHA1 is no longer defined in upstream litex, so remove it.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Paul Mackerras [Thu, 4 Aug 2022 09:35:52 +0000 (19:35 +1000)]
Merge pull request #383 from antonblanchard/fix-sdcard
litesdcard: Fix and regenerate Verilog
Anton Blanchard [Thu, 4 Aug 2022 08:24:56 +0000 (18:24 +1000)]
litesdcard: Fix and regenerate Verilog
Fix the litex generate script to pass frequencies in Hz. Regenerate
the litesdcard Verilog for both Xilinx and Lattice. This fixes
litesdcard on my Nexys Video.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Paul Mackerras [Mon, 1 Aug 2022 05:53:01 +0000 (15:53 +1000)]
Merge pull request #381 from shingarov/gitignore-artifacts
Gitignore build artifacts
Paul Mackerras [Mon, 1 Aug 2022 05:52:33 +0000 (15:52 +1000)]
Merge pull request #378 from mikey/ux-cleanup
Metavalue cleanup
Boris Shingarov [Fri, 29 Jul 2022 07:47:56 +0000 (03:47 -0400)]
Gitignore build artifacts
Building the mw_debug program leaves build artifacts in
microwatt/scripts/mw_debug
causing noise in the output of `git status`.
This commit adds them to .gitignore.
Signed-off-by: Boris Shingarov <shingarov@labware.com>
Michael Neuling [Thu, 28 Jul 2022 05:29:25 +0000 (15:29 +1000)]
test: Add test for metavalues
Make sure they don't increase in future
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 28 Jul 2022 05:28:25 +0000 (15:28 +1000)]
tests: Update FPU test output
The following commit added two tests but didn't update the tests
outputs:
commit
73cc5167ec1ea591d9da43f2e392b5202f045f32
Author: Paul Mackerras <paulus@ozlabs.org>
Date: Mon May 9 19:18:42 2022 +1000
Use FPU for division instructions if we have an FPU
This patch updates these using tests/update_console_tests
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 28 Jul 2022 04:47:51 +0000 (14:47 +1000)]
tests: Minor script cleanups
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:32:37 +0000 (10:32 +1000)]
Metavalue cleanup for register_file.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:32:37 +0000 (10:32 +1000)]
Metavalue cleanup for pmu.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:32:37 +0000 (10:32 +1000)]
Metavalue cleanup for rotator.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:32:16 +0000 (10:32 +1000)]
Metavalue cleanup for mmu.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:32:05 +0000 (10:32 +1000)]
Metavalue cleanup for loadstore1.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:31:53 +0000 (10:31 +1000)]
Metavalue cleanup for icache.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:31:43 +0000 (10:31 +1000)]
Metavalue cleanup for fpu.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:31:32 +0000 (10:31 +1000)]
Metavalue cleanup for fetch1.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:31:20 +0000 (10:31 +1000)]
Metavalue cleanup for execute1.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:30:57 +0000 (10:30 +1000)]
Metavalue cleanup for decoder1.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:29:11 +0000 (10:29 +1000)]
Metavalue cleanup for helpers.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Wed, 27 Jul 2022 23:50:26 +0000 (09:50 +1000)]
Metavalue cleanup for common.vhdl
This affects other files which have been included here.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Tue, 26 Jul 2022 00:08:33 +0000 (10:08 +1000)]
Merge pull request #379 from paulusmack/master
Lots of improvements
Michael Neuling [Mon, 25 Jul 2022 06:31:12 +0000 (16:31 +1000)]
Merge pull request #380 from iagocaran/master
tests/pmu: Add load/store completed and instruction/cycle count
Michael Neuling [Mon, 25 Jul 2022 05:03:40 +0000 (15:03 +1000)]
tests/pmu: Cleanup whitespace in pmc.c
Fixup tabs vs space and trailing whitespace.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Paul Mackerras [Thu, 14 Jul 2022 05:47:21 +0000 (15:47 +1000)]
Use register addresses from decode1 for dependency tracking
This improves timing a little because the register addresses now come
directly from a latch instead of being calculated by
decode_input_reg_*. The asserts that check that the two are the same
are now in decode2 rather than register_file.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 21 Feb 2022 22:30:05 +0000 (09:30 +1100)]
register_file: Make read access to register file synchronous
With this, the register RAM is read synchronously using the addresses
supplied by decode1. That means the register RAM can now be block RAM
rather than LUT RAM.
Debug accesses are done via the B port on cycles when decode1
indicates that there is no valid instruction or the instruction
doesn't use a [F]RB operand.
We latch the addresses being read in each cycle and use the same
address next cycle if stalled. Data that is being written is latched
and a multiplexer on each read port then supplies the latched write
data if the read address for that port equals the write address.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 21 Feb 2022 08:29:09 +0000 (19:29 +1100)]
decode1: Work out register addresses in decode1
This adds some relatively simple logic to decode1 to compute the
GPR/FPR addresses that an instruction will access. It always computes
three addresses regardless of whether the instruction will actually
use all of them. The main things it computes are whether the
instruction uses the RS field or the RC field for the 3rd operand, and
whether the operands are FPRs or GPRs (it is possible for RS to be an
FPR but RA and RB to be GPRs, as for example with stfdx).
At the moment all we do with these computed register addresses is to
assert that they are identical to the ones coming from decode2 one
cycle later.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Wed, 23 Mar 2022 18:02:28 +0000 (18:02 +0000)]
loadstore1: Do SPR reading in stage 2 rather than stage 3
This eliminates one leg of the output value multiplexer, and seems
to improve timing slightly on the A7-100.
Since SPR values are written in stage 3 and read in stage 2, an mfspr
immediately following an mtspr to the same SPR won't give the correct
value. To avoid this, we make mtspr to the load/store SPRs single
issue in decode1.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 24 Feb 2022 00:37:17 +0000 (11:37 +1100)]
Provide debug access to SPRs in loadstore1 and mmu
They are accessible as GSPR 0x3c - PID, 0x3d - PTCR, 0x3e - DSISR
and 0x3f - DAR.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 25 Feb 2022 05:46:34 +0000 (16:46 +1100)]
Restore debug access to SPRs
This provides access to the SPRs via the JTAG DMI interface. For now
they are still accessed as if they were GPR/FPRs using the same
numbering as before (GPRs at 0 - 0x1f, SPRs at 0x20 - 0x2d, FPRs at
0x40 - 0x5f).
For XER, debug reads now report the full value, not just the bits that
were previously stored in the register file. The "slow" SPR mux is
not used for debug reads.
Decode2 determines on each cycle whether a debug SPR access will
happen next cycle, based on whether there is a request and whether the
current instruction accesses the SPR RAM.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 19 Feb 2022 08:03:49 +0000 (19:03 +1100)]
Finish off taking SPRs out of register file
With this, the register file now contains 64 entries, for 32 GPRs and
32 FPRs, rather than the 128 it had previously. Several things get
simplified - decode1 no longer has to work out the ispr{1,2,o} values,
decode_input_reg_{a,b,c} no longer have the t = SPR case, etc.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 12 Jul 2022 01:20:17 +0000 (11:20 +1000)]
Move LR, CTR and TAR out of the register file
By putting CTR on the odd side and LR and TAR on the even side, we can
read and write CTR for bdnz-style instructions in parallel with
reading LR or TAR for indirect branches and writing LR for branches
with LK=1. Thus we don't need to double up any of these instructions,
giving a simplification in decode2.
We now have logic for printing LR and CTR at the end of a simulation
in execute1, in addition to the similar logic in register_file and
cr_file.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 11 Jul 2022 22:52:05 +0000 (08:52 +1000)]
Start removing SPRs from register file
This starts the process of removing SPRs from the register file by
moving SRR0/1, SPRG0-3, HSRR0/1 and HSPRG0/1 out of the register file
and putting them into execute1. They are stored in a pair of small
RAM arrays, referred to as "even" and "odd". The reason for having
two arrays is so that two values can be read and written in each
cycle. For example, SRR0 and SRR1 can be written in parallel by an
interrupt and read in parallel by the rfid instruction.
The addresses in the RAM which will be accessed are determined in the
decode2 stage. We have one write address for both sides, but two read
addresses, since in future we will want to be able to read CTR at the
same time as either LR or TAR.
We now have a connection from writeback to execute1 which carries the
partial SRR1 value for an interrupt. SRR0 comes from the execute
pipeline; we no longer need to carry instruction addresses along the
LSU and FPU pipelines. Since SRR0 and SRR1 can be written in the same
cycle now, we don't need the little state machine in writeback any
more.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 9 May 2022 09:18:42 +0000 (19:18 +1000)]
Use FPU for division instructions if we have an FPU
- Arrange for XER to be written for OE=1 forms
- Arrange for condition codes to be set for RC=1 forms
(including correct handling for 32-bit mode)
- Don't instantiate the divider if we have an FPU.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 7 May 2022 12:34:23 +0000 (22:34 +1000)]
FPU: Add logic for 32-bit integer division
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>