ilo: move BOs from ilo_texture to ilo_image

We want to work with ilo_image instead of ilo_texture in core.

ilo: move ilo_layout.[ch] to core as ilo_image.[ch]

Move files and s/layout/image/.

ilo: add ilo_format.[ch] to core

The original ilo_format.[ch] are removed.

ilo: add ilo_fence.h to core

Implement pipe_fence_handle on top of ilo_fence.

ilo: add ilo_dev_init() to core

Move init_dev() from ilo_screen.c to core.

ilo: rename ilo_dev_info to ilo_dev

With intel_winsys being embedded in it, drop the "_info" suffix.

ilo: move intel_winsys to ilo_dev_info

We want to use ilo_dev_info instead of ilo_screen in core.

ilo: add ilo_dev.h to core

Move what are remaining in ilo_common.h (that is, ilo_dev_*) to ilo_dev.h.

ilo: add ilo_debug.[ch] to core

They consist of the debug helpers that used to live in ilo_common.h and
ilo_screen.c.

ilo: add ilo_core.h to core

ilo_core.h includes the common gallium headers that were included in
ilo_common.h.

ilo: move intel_winsys.h to core

Add a new subdirectory and start moving files that do not depend on
ilo_screen/ilo_context to it.

i965: Upload atomic buffer state for compute shaders

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Emit MEDIA_STATE_FLUSH after WALKER

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Implement brw_emit_gpgpu_walker

Tested on Ivybridge, Haswell and Broadwell.

v2:
 * Use SET_FIELD. (Ken)
 * Use simd_size / 16 to support SIMD8/16/32. Ken suggested
   that we might be able to do it arithmetically rather than just
   supporting SIMD8 and SIMD16 with a conditional.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/state: Emit pipeline select when changing pipelines

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Implement DispatchCompute() back-end

brw_emit_gpgpu_walker will be implemented in a subsequent patch.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

main/cs: Implement front end code for glDispatchCompute().

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa/cs: Add DispatchCompute() to driver function table.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Emit state base address

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Add CS shader time support

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Upload brw_cs_state

v3:
 * Add defines. Misc cleanup suggestions. (Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Support CS program precompile

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add brw_setup_tex_for_precompile. Use in VS, GS & FS.

Suggested-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Emit compute shader code and upload programs

v2:
 * Don't bother checking for 'gen > 5' (krh)
 * Populate sampler data in key (krh)

v3:
 * Drop no8 support, and simplify code in several places (Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Set invocation counts based on max_cs_threads

For ES, we set the max counts based on SIMD8, which is currently
accurate.

For desktop GL, we set the max counts based on SIMD16, which can fail
in some cases where a SIMD16 program is not currently supported.
Therefore, this value is not currently accurate, but will work fine in
many cases, and lets us run more test cases. Eventually we want to
always be able to generate a SIMD16 program.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Add max_cs_threads

Add values for gen7 & gen8. These are the number threads in a
subslice.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Remove comment about chv device numbers being preliminary

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Support compute programs in fs_visitor

v2:
 * Clean out some unneeded code copied from run_fs (krh)
 * Always use NIR
 * Split shader time out into a separate commit

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cache: Add support for CS in program state cache

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Add brw_cs_prog_data, brw_cs_prog_key and brw_context::cs.

jordan.l.justen@intel.com:
 * Added brw_cs_prog_key structure
 * Added brw_cs_prog_data::dispatch_grf_start_reg_16
 * Added brw_cs_prog_data::local_size
 * Added brw_cs_prog_data::simd_size

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Add generator support for CS_OPCODE_CS_TERMINATE

v2:
 * Don't rely on brw_eu* to generate the send instruction. We now
   generate the send here, and drop the "i965/cs: Add support for the
   SEND message that terminates a CS thread" brw_eu* patch.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Mark g0 as used by CS_OPCODE_CS_TERMINATE

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Add emit_cs_terminate to emit CS_OPCODE_CS_TERMINATE

v2:
 * Do more work at the visitor level. g0 is loaded and sent to the
   generator now.

v3:
 * Use Ken's comment explaining g0 usage

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Add CS_OPCODE_CS_TERMINATE

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Add BRW_NEW_CS_PROG_DATA and BRW_CACHE_CS_PROG

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add an INTEL_DEBUG=cs option.

At the moment it's not wired up to anything.  Later patches will hook
it up to the compute shader back-end.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa/cs: Add compute support to update_program().

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa/cs: Update program.c for compute shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa/cs: Add inline functions for dealing with compute shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Add BRW_NEW_COMPUTE_PROGRAM state flag.

Also add code to brw_upload_state to set it when the compute program
changes.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Strip trailing constant zeroes in sample messages

If a send message is emitted with a message length that is less than
required for the message then the remaining parameters default to
zero. We can take advantage of this to save a register when a shader
passes constant zeroes as the final coordinates to the sample
function.

I think this might be useful for GLES applications that are using 2D
textures to simulate 1D textures.

On Skylake it will be useful for shaders that do
texelFetch(tex,something,0) which I think is fairly common. This helps
more on Skylake because in that case the order of the instruction
operands are u,v,lod,r which is good for 2D textures whereas before
they were u,lod,v,r which is only good for 1D textures.

On Haswell:
total instructions in shared programs: 8535730 -> 8533261 (-0.03%)
instructions in affected programs:     236968 -> 234499 (-1.04%)
helped:                                1174

On Skylake:
total instructions in shared programs: 10345646 -> 10341237 (-0.04%)
instructions in affected programs:     293011 -> 288602 (-1.50%)
helped:                                1218

Reviewed-by: Matt Turner <mattst88@gmail.com>
v2: Applied suggestions by Kenneth Graunke:
    - Only apply on Gen5+
    - Apply to all texture opcodes, not just TEX and TXF.
    Moved the optimisation into the loop as suggested by Matt Turner.
    Fix the array index when there is a header.

i965/skl: Force the exec size to 8 when initing header for SIMD4x2

On Gen9+ there needs to be a header when sampling using SIMD4x2. The
header is set up by copying from the g0 register. Commit 07c571a39f
tried to fix this mov instruction to always use an exec size of 8
because previously it was incorrectly using 4. It did this by casting
the type of the destination register to vec8. This was done because
there is code in brw_set_dest to guess the exec size based on the
width of the dest register. However I misunderstood how this works
because it is actually only used when the width is less than 8. That
means the patch actually changed it to use the default exec size which
on SIMD16 would be 16 and the MOV would clobber over the first
register in the send message. This patch makes it additionally set the
default exec size to 8. This is similar to how the message is set up
in fs_generator::generate_tex.

I think this wasn't picked up by any Piglit tests because we don't
have any fragment shaders that hit this code path so nothing was using
SIMD16. However the patch caused failures in deqp tests.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90153
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Tapani Pälli <tapani.palli@intel.com>

i965: Unhardcode a few more stage names and abbreviations.

The stage_abbrev and stage_name fields in backend_visitor provide what
we need without any additional effort.  It also means we'll get the
right names for compute shaders, SIMD8 geometry shaders, and both kinds
of tessellation shaders.

This does unfortunately change the capitalization of the stage
abbreviation in the INTEL_DEBUG=optimizer output filenames.  It doesn't
seem worth adding code to handle, though.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

docs/relnotes: document the new EGL sync extensions

st/dri: implement the fence interface for CL events

gallium,clover: add OpenCL interoperability support for CL events

v2: - move interop.cpp to clover/api
    - change intptr_t to void* in the interface
    - add a virtual function fence() to simplify some code

v3: - use bool in the interface
v4: - enclose the last two interop functions in try..catch

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

st/dri: implement the fence interface

egl/dri2: return the latest sync status in eglGetSyncAttribKHR

egl/dri2: implement EGL_KHR_cl_event2 (v2)

v2: fix the SYNC_CONDITION query

egl/dri2: implement EGL_KHR_wait_sync

egl/dri2: implement EGL_KHR_fence_sync

mesa: add GL_OES_EGL_sync

This is an empty extension whose presence means that EGL sync objects can be
used with ES contexts.

dri_interface: add an interface for fences

egl/dri: don't expose configs with an accumulation buffer

nvc0/ir: fix predicated PFETCH for real

Commit a9d08a250 accidentally didn't make use of the new src1 variable.
Use it.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

nv50/ir: fix asFlow() const helper for OP_JOIN

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

nvc0/ir: fix predicated PFETCH emission

src1 would contain the predicate, which would get emitted as a register
source by an undiscerning srcId helper. Work around this in the same way
as in emitTEX.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

gk110/ir: fix set with a register dest to not auto-set the abs flag

This was causing src0 to always have the absolute value flag set.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

i965/blorp: Prepare drawing rectangle for flipped coordinates

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Add support for layered rendering

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Allow blend state to be set for multiple render targets

Original blorp writes only one buffer per shader invocation. Once
the launch mechanism is shared with glsl-based programs there will
be need for supporting multiple render targets.

Also drop the always constant color write disable settings.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Prepare for attributes other than render position

Note that the magic number of one in gen7 logic is replaced by
BRW_SF_URB_ENTRY_READ_OFFSET ( == 1 also) for clarity.

On gen6 the change from zero to one (BRW_SF_URB_ENTRY_READ_OFFSET)
has no effect for native blorp as blorp doesn't use any
additional attributes. In fact, regular pipeline setup always
uses BRW_SF_URB_ENTRY_READ_OFFSET even when there are no additional
attributes. Hence the change makes the two (blorp and regular)
consistent.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Remove unused arguments

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/gen7/blorp: Remove unused arguments

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Allow caller to provide sampler settings

v2 (Ken): s/use_unorm_coords/non_normalized_coords/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Refactor vertex buffer state setup

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Remove constant parameter

This was still needed when we had support for blorp clears but now
this is fixed to nop.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/gen8: Expose state base address setup

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/ps/gen8: Refactor state uploading

v2: Use SET_FIELD() for sampler count, and for that reason
    added GEN7_PS_SAMPLER_COUNT_MASK.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/ps/gen7: Refactor state uploading

Now the uploading depends only on the input parameters instead
of consulting the current gl-state.

v2: Rebased on top of sampler count clamping

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Refactor sampler state setup

v2 (Matt): Moved * to the name.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Remove dependency to tex object in default color setup

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Refactor and expose brw_upload_binding_table()

Read and write parts of the state stage are also split into
explicit arguments allowing future patches to use constant
program data.

v2 (Ken): s/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Expose and refactor brw_update_renderbuffer_surfaces()

Note that brw_update_renderbuffer_surfaces() already had a helper
variable which was used in parallel to direct access of the current
draw buffer of the context.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Refactor rb surface setup to allow caller to store offsets

Notice that in gen7_wm_surface_state.c there is also indentation
change in the surrounding code removing tabs.

v2 (Matt): Fixed whitespace: tabs -> spaces

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/gen8: Use constant pointers for reading miptree details

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/ps: Use SET_FIELD() for sampler count

The value is actually clamped to 0-16 as sample state pointer
can be used to support more than 16 samplers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

glx: Massive update of comments in struct extension_info

In response to another patch, Emil asked for some clarification how this
stuff works.  Rather than just reply to the e-mail, I decided to update
the exlanation in the code.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: Emil Velikov <emil.l.velikov@gmail.com>

winsys/radeon: add a private interface for radeon_surface

winsys/radeon: move radeon_winsys.h to drivers/radeon

clover: remove util/compat

Acked-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

i965: Don't try to apply the opt_sampler_eot extension for vs

The opt_sampler_eot optimisation of fs_visitor effectively assumes
that it is running on a fragment shader because it casts the program
key to a brw_wm_prog_key. However on Skylake fs_visitor can also be
used for vertex shaders. It looks like this usually works anyway
because the optimisation is skipped if key->nr_color_regions != 1.
However for a vertex shader the key is actually a brw_vs_prog_key so
the space for nr_color_regions is probably taken up by
key->base.program_string_id. This can end up making nr_color_regions
be 1 in which case the function will later assert when the last
instruction is not FS_OPCODE_FB_WRITE. This was making the DEQP test
suite assert. Presumably this only happens there because that compiles
a lot of shaders so it would end up with a high value for
program_string_id.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

r300: do not link against libdrm_intel

Accidentally added since the introduction of the file.

Cc: "10.4 10.5" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

clover: make module::symbol::name a string

Acked-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

clover: remove compat::string

Acked-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

clover: remove compat classes that match std one

Acked-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

clover: compile all sources with c++11

Later we can remove the compat code

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

st/nine: Remove Managed texture hack.

Previously binding an unitialized managed texture
was causing a crash, and a workaround was added to
prevent the crash.

This patch removes this workaround and instead set the initial
state of managed textures as dirty, so that when the texture is bound
for the first time, it is always initialized.

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Enforce LOD 0 for D3DUSAGE_AUTOGENMIPMAP

For D3DUSAGE_AUTOGENMIPMAP textures, applications can only
lock/copy from/get surface descriptor for/etc the first level.
Thus it makes sense to restrict the LOD to 0, and use only the first
level to generate the sublevels.

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Some D3DUSAGE_AUTOGENMIPMAP fixes

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: util_gen_mipmap doesn't need we reset states.

util_gen_mipmap uses pipe->blit, and thus doesn't need
we restore all states after using it.

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: D3DUSAGE_AUTOGENMIPMAP is forbidden for volumes

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Fix NineBaseTexture9_PreLoad

It wasn't uploading the texture when the lod
had changed.

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Rewrite Managed texture uploads

That part of the code was quite obscure.
This new implementation tries to make it clearer
by separating the differents parts, and commenting more.

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Bound the dirty regions to resource size

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Simplify Surface9 Managed resources implementation

Remove the Surface9 code for dirty rects, used only for Managed
resources. Instead convey the information to the parent texture.

According to documentation, this seems to be the expected behaviour,
and if documentation is wrong there, that's not a problem since it can
only leads to more texture updates in corner cases.

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Remove impossible cases with Managed textures

Copying to/from a Managed texture is forbidden.
Rendering to a Managed texture is forbidden.

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Encapsulate variables for MANAGED resource

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Rework texture data allocation

Some applications assume the memory for multilevel
textures is allocated per continuous blocks.

This patch implements that behaviour.

v2: cache offsets

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Fix update_vertex_elements bad rebase

This code was supposed to be removed, but a rebase seems to have
made it stay.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>