GDB Administrator [Mon, 3 Jul 2023 00:00:10 +0000 (00:00 +0000)]
Automatic date update in version.in
GDB Administrator [Sun, 2 Jul 2023 00:00:10 +0000 (00:00 +0000)]
Automatic date update in version.in
Vladimir Mezentsev [Thu, 29 Jun 2023 20:11:09 +0000 (13:11 -0700)]
gprofng: fix data race
In our GUI project (https://savannah.gnu.org/projects/gprofng-gui), we use
the output of gprofng to display the data. Sometimes this data is corrupted.
gprofng/ChangeLog
2023-06-29 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
* src/ipc.cc (ipc_doWork): Fix data race.
* src/ipcio.cc (IPCresponse::print): Fix data race.
Remove unused variables and functions.
* src/ipcio.h: Declare two variables.
* src/StringBuilder.cc (StringBuilder::write): New function.
* src/StringBuilder.h: Likewise.
Christoph Müllner [Fri, 30 Jun 2023 21:30:58 +0000 (23:30 +0200)]
binutils: NEWS: Announce new RISC-V vector crypto extensions
This commit adds the recently added support of the RISC-V vector crypto
extensions to the NEWS file.
binutils/ChangeLog:
* NEWS: Announce new RISC-V vector crypto extensions.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Nathan Huckleberry [Fri, 30 Jun 2023 20:44:42 +0000 (22:44 +0200)]
RISC-V: Add support for the Zvksc ISA extension
Zvksc is part of the vector crypto extensions.
Zvksc is shorthand for the following set of extensions:
- Zvks
- Zvbc
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvksc extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvksc.d: New test.
* testsuite/gas/riscv/zvksc.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Nathan Huckleberry [Fri, 30 Jun 2023 20:44:37 +0000 (22:44 +0200)]
RISC-V: Add support for the Zvknc ISA extension
Zvknc is part of the vector crypto extensions.
Zvknc is shorthand for the following set of extensxions:
- Zvkn
- Zvbc
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvknc extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvknc.d: New test.
* testsuite/gas/riscv/zvknc.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Nathan Huckleberry [Fri, 30 Jun 2023 20:44:32 +0000 (22:44 +0200)]
RISC-V: Add support for the Zvksg ISA extension
Zvksg is part of the vector crypto extensions.
Zvksg is shorthand for the following set of extensions:
- Zvks
- Zvkg
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvksg extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvksg.d: New test.
* testsuite/gas/riscv/zvksg.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Christoph Müllner [Fri, 30 Jun 2023 20:44:28 +0000 (22:44 +0200)]
RISC-V: Add support for the Zvks ISA extension
Zvks is part of the vector crypto extensions.
Zvks is shorthand for the following set of extensions:
- Zvksed
- Zvksh
- Zvbb
- Zvkt
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvks extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvks.d: New test.
* testsuite/gas/riscv/zvks.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Nathan Huckleberry [Fri, 30 Jun 2023 20:44:23 +0000 (22:44 +0200)]
RISC-V: Add support for the Zvkng ISA extension
Zvkng is part of the vector crypto extensions.
Zvkng is shorthand for the following set of extensions:
- Zvkn
- Zvkg
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvkng extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvkng.d: New test.
* testsuite/gas/riscv/zvkng.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Nathan Huckleberry [Fri, 30 Jun 2023 20:44:17 +0000 (22:44 +0200)]
RISC-V: Allow nested implications for extensions
Certain extensions require two levels of implications. For example,
zvkng implies zvkn and zvkn implies zvkned. Enabling zvkng should also
enable zvkned.
This patch fixes this behavior.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_add_implicit_subsets): Allow nested
implications for extensions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Christoph Müllner [Fri, 30 Jun 2023 20:44:12 +0000 (22:44 +0200)]
RISC-V: Add support for the Zvkn ISA extension
Zvkn is part of the vector crypto extensions.
Zvkn is shorthand for the following set of extensions:
- Zvkned
- Zvknhb
- Zvbb
- Zvkt
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvkn extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvkn.d: New test.
* testsuite/gas/riscv/zvkn.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Christoph Müllner [Fri, 30 Jun 2023 20:44:05 +0000 (22:44 +0200)]
RISC-V: Add support for the Zvksh ISA extension
Zvksh is part of the vector crypto extensions.
This extension adds the following instructions:
- vsm3me.vv
- vsm3c.vi
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvksh.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvksh.d: New test.
* testsuite/gas/riscv/zvksh.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VSM3C_VI): New.
(MASK_VSM3C_VI): New.
(MATCH_VSM3ME_VV): New.
(MASK_VSM3ME_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvksh.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvksh instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Christoph Müllner [Fri, 30 Jun 2023 20:44:01 +0000 (22:44 +0200)]
RISC-V: Add support for the Zvksed ISA extension
Zvksed is part of the vector crypto extensions.
This extension adds the following instructions:
- vsm4k.vi
- vsm4r.[vv,vs]
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvksed.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvksed.d: New test.
* testsuite/gas/riscv/zvksed.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VSM4K_VI): New.
(MASK_VSM4K_VI): New.
(MATCH_VSM4R_VS): New.
(MASK_VSM4R_VS): New.
(MATCH_VSM4R_VV): New.
(MASK_VSM4R_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvksed.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvksed instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Christoph Müllner [Fri, 30 Jun 2023 20:43:55 +0000 (22:43 +0200)]
RISC-V: Add support for the Zvknh[a,b] ISA extensions
Zvknh[a,b] are parts of the vector crypto extensions.
This extension adds the following instructions:
- vsha2ms.vv
- vsha2c[hl].vv
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvknh[a,b].
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvknha.d: New test.
* testsuite/gas/riscv/zvknha_zvknhb.s: New test.
* testsuite/gas/riscv/zvknhb.d: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VSHA2CH_VV): New.
(MASK_VSHA2CH_VV): New.
(MATCH_VSHA2CL_VV): New.
(MASK_VSHA2CL_VV): New.
(MATCH_VSHA2MS_VV): New.
(MASK_VSHA2MS_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvknh[a,b].
opcodes/ChangeLog:
* riscv-opc.c: Add Zvknh[a,b] instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Christoph Müllner [Fri, 30 Jun 2023 20:43:50 +0000 (22:43 +0200)]
RISC-V: Add support for the Zvkned ISA extension
Zvkned is part of the vector crypto extensions.
This extension adds the following instructions:
- vaesef.[vv,vs]
- vaesem.[vv,vs]
- vaesdf.[vv,vs]
- vaesdm.[vv,vs]
- vaeskf1.vi
- vaeskf2.vi
- vaesz.vs
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvkned.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvkned.d: New test.
* testsuite/gas/riscv/zvkned.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VAESDF_VS): New.
(MASK_VAESDF_VS): New.
(MATCH_VAESDF_VV): New.
(MASK_VAESDF_VV): New.
(MATCH_VAESDM_VS): New.
(MASK_VAESDM_VS): New.
(MATCH_VAESDM_VV): New.
(MASK_VAESDM_VV): New.
(MATCH_VAESEF_VS): New.
(MASK_VAESEF_VS): New.
(MATCH_VAESEF_VV): New.
(MASK_VAESEF_VV): New.
(MATCH_VAESEM_VS): New.
(MASK_VAESEM_VS): New.
(MATCH_VAESEM_VV): New.
(MASK_VAESEM_VV): New.
(MATCH_VAESKF1_VI): New.
(MASK_VAESKF1_VI): New.
(MATCH_VAESKF2_VI): New.
(MASK_VAESKF2_VI): New.
(MATCH_VAESZ_VS): New.
(MASK_VAESZ_VS): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvkned.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvkned instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Christoph Müllner [Fri, 30 Jun 2023 20:43:46 +0000 (22:43 +0200)]
RISC-V: Add support for the Zvkg ISA extension
Zvkg is part of the vector crypto extensions.
This extension adds the following instructions:
- vghsh.vv
- vgmul.vv
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvkg.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvkg.d: New test.
* testsuite/gas/riscv/zvkg.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VGHSH_VV): New.
(MASK_VGHSH_VV): New.
(MATCH_VGMUL_VV): New.
(MASK_VGMUL_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvkg.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvkg instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Nathan Huckleberry [Fri, 30 Jun 2023 20:43:40 +0000 (22:43 +0200)]
RISC-V: Add support for the Zvbc extension
Zvbc is part of the crypto vector extensions.
This extension adds the following instructions:
- vclmul.[vv,vx]
- vclmulh.[vv,vx]
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvbc.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvbc.d: New test.
* testsuite/gas/riscv/zvbc.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VCLMUL_VV): New.
(MASK_VCLMUL_VV): New.
(MATCH_VCLMUL_VX): New.
(MASK_VCLMUL_VX): New.
(MATCH_VCLMULH_VV): New.
(MASK_VCLMULH_VV): New.
(MATCH_VCLMULH_VX): New.
(MASK_VCLMULH_VX): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvbc.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvbc instruction.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Christoph Müllner [Fri, 30 Jun 2023 20:43:33 +0000 (22:43 +0200)]
RISC-V: Add support for the Zvbb ISA extension
Zvbb is part of the vector crypto extensions.
This extension adds the following instructions:
- vandn.[vv,vx]
- vbrev.v
- vbrev8.v
- vrev8.v
- vclz.v
- vctz.v
- vcpop.v
- vrol.[vv,vx]
- vror.[vv,vx,vi]
- vwsll.[vv,vx,vi]
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvbb.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Add 'l' as new format
string directive.
(riscv_ip): Likewise.
* testsuite/gas/riscv/zvbb.d: New test.
* testsuite/gas/riscv/zvbb.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VANDN_VV): New.
(MASK_VANDN_VV): New.
(MATCH_VANDN_VX): New.
(MASK_VANDN_VX): New.
(MATCH_VBREV8_V): New.
(MASK_VBREV8_V): New.
(MATCH_VBREV_V): New.
(MASK_VBREV_V): New.
(MATCH_VCLZ_V): New.
(MASK_VCLZ_V): New.
(MATCH_VCPOP_V): New.
(MASK_VCPOP_V): New.
(MATCH_VCTZ_V): New.
(MASK_VCTZ_V): New.
(MATCH_VREV8_V): New.
(MASK_VREV8_V): New.
(MATCH_VROL_VV): New.
(MASK_VROL_VV): New.
(MATCH_VROL_VX): New.
(MASK_VROL_VX): New.
(MATCH_VROR_VI): New.
(MASK_VROR_VI): New.
(MATCH_VROR_VV): New.
(MASK_VROR_VV): New.
(MATCH_VROR_VX): New.
(MASK_VROR_VX): New.
(MATCH_VWSLL_VI): New.
(MASK_VWSLL_VI): New.
(MATCH_VWSLL_VV): New.
(MASK_VWSLL_VV): New.
(MATCH_VWSLL_VX): New.
(MASK_VWSLL_VX): New.
(DECLARE_INSN): New.
* opcode/riscv.h (EXTRACT_RVV_VI_UIMM6): New.
(ENCODE_RVV_VI_UIMM6): New.
(enum riscv_insn_class): Add instruction class for Zvbb.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add 'l' as new format string
directive.
* riscv-opc.c: Add Zvbb instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
GDB Administrator [Sat, 1 Jul 2023 00:00:26 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom Tromey [Fri, 30 Jun 2023 01:38:10 +0000 (19:38 -0600)]
Fix regressions caused by agent expression C++-ification
Simon pointed out that my agent expression C++-ification patches
caused a regression with the native-gdbserver target board. The bug
is that append_const is supposed to write in big-endian order, but I
switched this by mistake.
Philipp Tomsich [Fri, 30 Jun 2023 14:02:11 +0000 (16:02 +0200)]
binutils: NEWS: announce new RISC-V extensions
We picked up support for a few new extensions over the last weeks
(this may need further updating prior to the next release), list them
in the NEWS file.
binutils/ChangeLog:
* binutils/NEWS: announce suuport for the new RISC-V
extensions (Zicond, Zfa, XVentanaCondOps).
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Christoph Müllner [Mon, 27 Mar 2023 07:27:31 +0000 (09:27 +0200)]
RISC-V: Add support for the Zfa extension
This patch adds support for the RISC-V Zfa extension,
which introduces additional floating-point instructions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of FP registers in case XLEN < FLEN
* fleq/fltq (quiet comparison instructions)
Zfa defines its instructions in combination with the following
extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)
This patch is based on an earlier version from Tsukasa OI:
https://sourceware.org/pipermail/binutils/2022-September/122939.html
Most significant change to that commit is the switch from the rs1-field
value to the actual floating-point value in the last operand of the fli*
instructions. Everything that strtof() can parse is accepted and
the '%a' printf specifier is used to output hex floating-point literals
in the disassembly.
The Zfa specification is frozen (and has passed public review). It is
available as a chapter in "The RISC-V Instruction Set Manual: Volume 1":
https://github.com/riscv/riscv-isa-manual/releases
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for 'Zfa' extension.
(riscv_multi_subset_supports_ext): Likewise.
(riscv_implicit_subsets): Add 'Zfa' -> 'F' dependency.
gas/ChangeLog:
* config/tc-riscv.c (flt_lookup): New helper to lookup a float value
in an array.
(validate_riscv_insn): Add 'Wfv' as new format string directive.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Add floating-point chapter and describe
limiations of the Zfa FP literal parsing.
* testsuite/gas/riscv/zfa-32.d: New test.
* testsuite/gas/riscv/zfa-32.s: New test.
* testsuite/gas/riscv/zfa-64.d: New test.
* testsuite/gas/riscv/zfa-64.s: New test.
* testsuite/gas/riscv/zfa-fail.d: New test.
* testsuite/gas/riscv/zfa-fail.l: New test.
* testsuite/gas/riscv/zfa-fail.s: New test.
* testsuite/gas/riscv/zfa.d: New test.
* testsuite/gas/riscv/zfa.s: New test.
* testsuite/gas/riscv/zfa.s: New test.
* opcode/riscv-opc.h (MATCH_FLI_H): New.
(MASK_FLI_H): New.
(MATCH_FMINM_H): New.
(MASK_FMINM_H): New.
(MATCH_FMAXM_H): New.
(MASK_FMAXM_H): New.
(MATCH_FROUND_H): New.
(MASK_FROUND_H): New.
(MATCH_FROUNDNX_H): New.
(MASK_FROUNDNX_H): New.
(MATCH_FLTQ_H): New.
(MASK_FLTQ_H): New.
(MATCH_FLEQ_H): New.
(MASK_FLEQ_H): New.
(MATCH_FLI_S): New.
(MASK_FLI_S): New.
(MATCH_FMINM_S): New.
(MASK_FMINM_S): New.
(MATCH_FMAXM_S): New.
(MASK_FMAXM_S): New.
(MATCH_FROUND_S): New.
(MASK_FROUND_S): New.
(MATCH_FROUNDNX_S): New.
(MASK_FROUNDNX_S): New.
(MATCH_FLTQ_S): New.
(MASK_FLTQ_S): New.
(MATCH_FLEQ_S): New.
(MASK_FLEQ_S): New.
(MATCH_FLI_D): New.
(MASK_FLI_D): New.
(MATCH_FMINM_D): New.
(MASK_FMINM_D): New.
(MATCH_FMAXM_D): New.
(MASK_FMAXM_D): New.
(MATCH_FROUND_D): New.
(MASK_FROUND_D): New.
(MATCH_FROUNDNX_D): New.
(MASK_FROUNDNX_D): New.
(MATCH_FLTQ_D): New.
(MASK_FLTQ_D): New.
(MATCH_FLEQ_D): New.
(MASK_FLEQ_D): New.
(MATCH_FLI_Q): New.
(MASK_FLI_Q): New.
(MATCH_FMINM_Q): New.
(MASK_FMINM_Q): New.
(MATCH_FMAXM_Q): New.
(MASK_FMAXM_Q): New.
(MATCH_FROUND_Q): New.
(MASK_FROUND_Q): New.
(MATCH_FROUNDNX_Q): New.
(MASK_FROUNDNX_Q): New.
(MATCH_FLTQ_Q): New.
(MASK_FLTQ_Q): New.
(MATCH_FLEQ_Q): New.
(MASK_FLEQ_Q): New.
(MATCH_FCVTMOD_W_D): New.
(MASK_FCVTMOD_W_D): New.
(MATCH_FMVH_X_D): New.
(MASK_FMVH_X_D): New.
(MATCH_FMVH_X_Q): New.
(MASK_FMVH_X_Q): New.
(MATCH_FMVP_D_X): New.
(MASK_FMVP_D_X): New.
(MATCH_FMVP_Q_X): New.
(MASK_FMVP_Q_X): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction
classes for the Zfa extension.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add support for
new format string directive 'Wfv'.
* riscv-opc.c: Add Zfa instructions.
Co-Developed-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Co-Developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Nick Clifton [Fri, 30 Jun 2023 12:54:03 +0000 (13:54 +0100)]
strings: Improve code to detect excessively large minimum string lengths.
PR 30598
* strings.c (set_string_min): New function. (main): Use it. (print_unicode_stream): Calculate buffer size using a size_t.
Nick Clifton [Fri, 30 Jun 2023 10:18:42 +0000 (11:18 +0100)]
Prevent an illegal memory access when running the strings program with an excessively lerge minimum string length.
PR 30595
* strings.c (main): Check for an excessively large minimum string length.
Nick Clifton [Fri, 30 Jun 2023 09:45:20 +0000 (10:45 +0100)]
Fix used-before-initialized warnings when compiling elf.c with Clang-16.
mengqinggang [Fri, 30 Jun 2023 09:04:16 +0000 (17:04 +0800)]
LoongArch: gas: Fix code style issues
Blocks of 8 spaces be replaced with tabs.
Fix alignment issues.
mengqinggang [Fri, 30 Jun 2023 09:04:15 +0000 (17:04 +0800)]
LoongArch: gas: Add LVZ and LBT instructions support
gas/ChangeLog:
* config/tc-loongarch.c (md_parse_option): Add LARCH_opts.ase_lvz and
LARCH_opts.ase_lbt.
* testsuite/gas/loongarch/uleb128.d: Regenerated.
* testsuite/gas/loongarch/lvz-lbt.d: New test.
* testsuite/gas/loongarch/lvz-lbt.s: New test.
include/ChangeLog:
* opcode/loongarch.h (ase_lvz): New.
(ase_lbt): New.
opcodes/ChangeLog:
* loongarch-dis.c (set_default_loongarch_dis_options): Add
LARCH_opts.ase_lvz and LARCH_opts.ase_lbt.
* loongarch-opc.c (struct loongarch_ase): Add LVZ and LBT instructions.
WANG Xuerui [Thu, 29 Jun 2023 16:35:04 +0000 (00:35 +0800)]
LoongArch: Deprecate $v[01], $fv[01] and $x names per spec
As outlined in the LoongArch ELF psABI spec [1], it is actually already
2 versions after the initial LoongArch support, and the $v[01] and
$fv[01] names should really get sunset by now.
In addition, the "$x" name for $r21 was never included in any released
version of the ABI spec, and such usages are all fixed to say just $r21
for every project I could think of that accepted a LoongArch port.
Plus, the upcoming LSX/LASX support makes use of registers named
"$vrNN" and "$xrNN", so having "$vN" and "$x" alongside would almost
certainly create confusion for developers.
Issue warnings for such usages per the deprecation procedure detailed
in the spec, so we can finally remove support in the next release cycle
after this.
[1]: https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html
gas/ChangeLog:
* config/tc-loongarch.c: Init canonical register ABI name
mappings and deprecated register names.
(loongarch_args_parser_can_match_arg_helper): Warn in case of
deprecated register name usage.
* testsuite/gas/loongarch/deprecated_reg_aliases.d: New test.
* testsuite/gas/loongarch/deprecated_reg_aliases.l: Likewise.
* testsuite/gas/loongarch/deprecated_reg_aliases.s: Likewise.
include/ChangeLog:
* opcode/loongarch.h: Rename global variables.
opcodes/ChangeLog:
* loongarch-opc.c: Rename the alternate/deprecated register name
mappings, and move $x to the deprecated name map.
Signed-off-by: WANG Xuerui <git@xen0n.name>
WANG Xuerui [Thu, 29 Jun 2023 16:35:03 +0000 (00:35 +0800)]
opcodes/loongarch: print unrecognized insn words with the .word directive
For better round-trip fidelity and readability in general.
gas/ChangeLog:
* testsuite/gas/loongarch/uleb128.d: Update test case.
* testsuite/gas/loongarch/raw-insn.d: New test.
* testsuite/gas/loongarch/raw-insn.s: Likewise.
opcodes/ChangeLog:
* loongarch-dis.c (disassemble_one): Print ".word" if !opc.
Signed-off-by: WANG Xuerui <git@xen0n.name>
WANG Xuerui [Thu, 29 Jun 2023 16:35:02 +0000 (00:35 +0800)]
opcodes/loongarch: do not print hex notation for signed immediates
The additional hex notation was minimally useful when one had to
inspect code with heavy bit manipulation, or of unclear signedness, but
it clutters the output, and the style is not regular assembly language
syntax either.
Precisely how one approaches the original use case is not taken care of
in this patch (maybe we want a disassembler option forcing a certain
style for immediates, like for example printing every immediate in
decimal or hexadecimal notation), but at least let's stop the current
practice.
ChangeLog:
* testsuite/gas/loongarch/imm_ins.d: Update test case.
* testsuite/gas/loongarch/imm_ins_32.d: Likewise.
* testsuite/gas/loongarch/imm_op.d: Likewise.
* testsuite/gas/loongarch/jmp_op.d: Likewise.
* testsuite/gas/loongarch/load_store_op.d: Likewise.
* testsuite/gas/loongarch/macro_op.d: Likewise.
* testsuite/gas/loongarch/macro_op_32.d: Likewise.
* testsuite/gas/loongarch/privilege_op.d: Likewise.
* testsuite/gas/loongarch/uleb128.d: Likewise.
* testsuite/gas/loongarch/vector.d: Likewise.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/jmp_op.d: Update test case.
* testsuite/ld-loongarch-elf/macro_op.d: Likewise.
* testsuite/ld-loongarch-elf/macro_op_32.d: Likewise.
opcodes/ChangeLog:
* loongarch-dis.c (dis_one_arg): Remove the "(0x%x)" part from
disassembly output of signed immediate operands.
Signed-off-by: WANG Xuerui <git@xen0n.name>
WANG Xuerui [Thu, 29 Jun 2023 16:35:01 +0000 (00:35 +0800)]
opcodes/loongarch: style disassembled address offsets as such
Add a modifier char 'o' telling the disassembler to print the immediate
using the address offset style, and mark the memory access instructions'
offset operands as such.
opcodes/ChangeLog:
* loongarch-dis.c (dis_one_arg): Style disassembled address
offsets as such when the operand has a modifier char 'o'.
* loongarch-opc.c: Add 'o' to operands that represent address
offsets.
Signed-off-by: WANG Xuerui <git@xen0n.name>
WANG Xuerui [Thu, 29 Jun 2023 16:35:00 +0000 (00:35 +0800)]
opcodes/loongarch: implement style support in the disassembler
Update the LoongArch disassembler to supply style information to the
disassembler output. The output formatting remains unchanged.
opcodes/ChangeLog:
* disassemble.c: Mark LoongArch as created_styled_output=true.
* loongarch-dis.c (dis_one_arg): Use fprintf_styled_func
throughout with proper styles.
Signed-off-by: WANG Xuerui <git@xen0n.name>
WANG Xuerui [Thu, 29 Jun 2023 16:34:59 +0000 (00:34 +0800)]
opcodes/loongarch: remove unused code
Remove some unused declarations and code.
include/ChangeLog:
* opcode/loongarch.h: Remove unused declarations.
opcodes/ChangeLog:
* loongarch-dis.c (loongarch_parse_dis_options): Remove.
(my_print_address_func): Likewise.
(loongarch_disassemble_one): Likewise.
Signed-off-by: WANG Xuerui <git@xen0n.name>
WANG Xuerui [Thu, 29 Jun 2023 16:34:58 +0000 (00:34 +0800)]
LoongArch: support disassembling certain pseudo-instructions
Add a flag in the pinfo field for being able to mark certain specialized
matchers as disassembler-only, so some degree of isolation between
assembler-side and disassembler-side can be achieved.
This isolation is necessary, firstly because some pseudo-instructions
cannot be fully described in the opcode table, like `li.[wd]`, so the
corresponding opcode entry cannot have meaningful match/mask values.
Secondly, some of these pseudo-instructions can be realized in more than
one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can
be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie
disassembly of such aliases with the corresponding GAS support, only one
canonical form among the above would be recognized as `li.w`, and it
would mildly impact the readability of disassembly output.
People wanting the exact disassembly can always set `-M no-aliases` to
get the original behavior back.
In addition, in certain cases, information is irreversibly lost after
assembling, so perfect round-trip would not be possible in such cases.
For example, `li.w` and `li.d` of immediates within int32_t range
produce the same code; in this patch, `addi.d rd, $zero, imm` is treated
as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`,
due to the expressible value range well within 32 bits.
gas/ChangeLog:
* config/tc-loongarch.c (get_loongarch_opcode): Ignore
disassembler-only aliases.
* testsuite/gas/loongarch/64_pcrel.d: Update test case.
* testsuite/gas/loongarch/imm_ins.d: Likewise.
* testsuite/gas/loongarch/imm_ins_32.d: Likewise.
* testsuite/gas/loongarch/jmp_op.d: Likewise.
* testsuite/gas/loongarch/li.d: Likewise.
* testsuite/gas/loongarch/macro_op.d: Likewise.
* testsuite/gas/loongarch/macro_op_32.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_abs.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_pc.d: Likewise.
* testsuite/gas/loongarch/nop.d: Likewise.
* testsuite/gas/loongarch/relax_align.d: Likewise.
* testsuite/gas/loongarch/reloc.d: Likewise.
include/ChangeLog:
* opcode/loongarch.h (INSN_DIS_ALIAS): Add.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/jmp_op.d: Update test case.
* testsuite/ld-loongarch-elf/macro_op.d: Likewise.
* testsuite/ld-loongarch-elf/macro_op_32.d: Likewise.
* testsuite/ld-loongarch-elf/relax-align.dd: Likewise.
opcodes/ChangeLog:
* loongarch-dis.c: Move register name map declarations to top.
(get_loongarch_opcode_by_binfmt): Consider aliases when
disassembling without the no-aliases option.
(parse_loongarch_dis_option): Support the no-aliases option.
* loongarch-opc.c: Collect pseudo instructions into a new
dedicated table.
Signed-off-by: WANG Xuerui <git@xen0n.name>
GDB Administrator [Fri, 30 Jun 2023 00:00:09 +0000 (00:00 +0000)]
Automatic date update in version.in
Indu Bhagat [Thu, 29 Jun 2023 23:29:16 +0000 (16:29 -0700)]
binutils/NEWS: announce SFrame version 2 as the new default
Indu Bhagat [Thu, 29 Jun 2023 23:29:12 +0000 (16:29 -0700)]
doc: sframe: update specification for SFRAME_VERSION_2
Add details for the changes made from Version 1 to Version 2 of the format.
Also add details about alignment in the SFrame format. A portion of the
SFrame stack trace format has an unaligned on-disk representation. Add
description at relevant points in the specificatin to clarify the
alignment related details.
Indu Bhagat [Thu, 29 Jun 2023 23:29:09 +0000 (16:29 -0700)]
sframe: bfd: gas: ld: format bump to SFrame version 2
SFrame version 2 encodes the size of repetitive insn block explicitly
in the format. Add information in the SFrame FDE to convey the size
of the block of repeating instructions. This information is used only
for SFrame FDEs of type SFRAME_FDE_TYPE_PCMASK.
Introduce two extra bytes for padding: this ensures that the memory
accesses to the members of the SFrame Frame Descriptor Entry (FDE) are
naturally aligned.
gas generates SFrame section with version SFRAME_VERSION_2 by default.
libsframe provides two new APIs to:
- get an SFrame FDE data from the decoder context, and
- add an SFrame FDE to the encoder context.
The additional argument (for rep_block_size) is useful for SFrame FDEs
where FDE type is SFRAME_FDE_TYPE_PCMASK.
The linker will generate the output SFrame sections in the
SFRAME_VERSION_2 format. If the input sections offered to the linker
are not all in the SFRAME_VERSION_2 format, the linker issues an error
to the user.
objdump/readelf will show the following message to the user if .sframe
section in SFRAME_VERSION_1 format is seen:
"No further information can be displayed. SFrame version not
supported."
In other words, like the rest of the binutils, only the current SFrame
format version, i.e., SFRAME_VERSION_2 is supported by the textual dump
facilities.
bfd/
* elf-sframe.c (_bfd_elf_merge_section_sframe): Generate an
output SFrame section with version SFRAME_VERSION_2. Also,
error out if the SFrame sections do not all have
SFRAME_VERSION_2.
* elfxx-x86.c (_bfd_x86_elf_create_sframe_plt): Generate SFrame
section for plt entries with version SFRAME_VERSION_2.
gas/
* gen-sframe.c (sframe_set_version): Update to SFRAME_VERSION_2.
(output_sframe): Likewise.
gas/testsuite/
* gas/cfi-sframe/cfi-sframe-aarch64-1.d: Use SFRAME_VERSION_2.
* gas/cfi-sframe/cfi-sframe-aarch64-2.d: Likewise.
* gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-1.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-2.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-3.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-4.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-5.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-6.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-7.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-8.d: Likewise.
* gas/cfi-sframe/cfi-sframe-x86_64-1.d: Likewise.
* gas/cfi-sframe/common-empty-1.d: Likewise.
* gas/cfi-sframe/common-empty-2.d: Likewise.
* gas/cfi-sframe/common-empty-3.d: Likewise.
ld/testsuite/
* ld-aarch64/sframe-simple-1.d: Adjust for SFRAME_VERSION_2.
* ld-x86-64/sframe-plt-1.d: Likewise.
* ld-x86-64/sframe-simple-1.d: Likewise.
libsframe/
* libsframe.ver: Add the new APIs.
* sframe.c (sframe_decoder_get_funcdesc_v2): New definition.
(sframe_encoder_add_funcdesc_v2): Likewise.
(sframe_header_sanity_check_p): Include SFRAME_VERSION_2.
(sframe_fre_check_range_p): Get rep_block_size info from SFrame
FDE.
* sframe-dump.c (dump_sframe_header): Add support for
SFRAME_VERSION_2.
(dump_sframe): Inform user if SFrame section in SFRAME_VERSION_1
format is seen.
libsframe/testsuite/
* libsframe.decode/DATA-BE: Regenerated data file.
* libsframe.decode/DATA1: Likewise.
* libsframe.decode/DATA2: Likewise.
* libsframe.find/plt-findfre-1.c: Use new API in the testcase.
include/
* sframe.h: Add member to encode size of the code block of
repeating instructions. Add 2 bytes of padding.
* sframe-api.h (sframe_decoder_get_funcdesc_v2): New
declaration.
(sframe_encoder_add_funcdesc_v2): Likewise.
Indu Bhagat [Thu, 29 Jun 2023 23:28:56 +0000 (16:28 -0700)]
libsframe: add new APIs to get SFrame version
While the SFrame preamble is guaranteed to not change between versions,
providing these access APIs from the SFrame decoder and encoder APIs is
for convenience only. The linker may want to use these APIs as the
format evolves.
include/
* sframe-api.h (sframe_decoder_get_version): New declaration.
(sframe_encoder_get_version): Likewise.
libsframe/
* libsframe/libsframe.ver: Add new APIs.
* libsframe/sframe.c (sframe_decoder_get_version): New
definition.
(sframe_encoder_get_version): Likewise.
Indu Bhagat [Thu, 29 Jun 2023 18:03:32 +0000 (11:03 -0700)]
libsframe: fix sframe_find_fre for pltN entries
For a toy application on x86_64, for example, following is the SFrame
stack trace information for the 3 pltN entries of 16 bytes each:
func idx [1]: pc = 0x401030, size = 48 bytes
STARTPC[m] CFA FP RA
0000000000000000 sp+8 u u
000000000000000b sp+16 u u
The data in first column is the start_ip_offset. Also note that the FDE
is of type SFRAME_FDE_TYPE_PCMASK (denoted by the [m] on LHS).
Where each pltN (note: excluding plt0 entry) entry looks like:
401030: jmp *0x2fca(%rip)
401036: push $0x0
40103b: jmp 401020<_init+0x20>
401040: jmp *0x2fc2(%rip)
401046: push $0x1
40104b: jmp 401020<_init+0x20>
401050: jmp *0x2fba(%rip)
401056: push $0x2
40105b: jmp 401020<_init+0x20>
Now, to find SFrame stack trace information from an FDE of type
SFRAME_FDE_TYPE_PCMASK, sframe_find_fre () was doing an operation
like,
(start_ip_offset & 0xf) >= (pc & 0xf)
This works for pltN entry of size, say, less than 16 bytes. But if the
pltN entries or similar code stubs (for which SFrame FDE of type
SFRAME_FDE_TYPE_PCMASK may be used), evolve to be of size > 16 bytes,
this will cease to work.
To match the range covered by the SFrame FRE, one should instead perform
a modulo operation. The constant for the modulo operation must be the
size of the pltN entry. Further, this constant should ideally be
encoded in the format, as it may be different for each ABI.
In SFrame Version 2 of the format, we will move towards encoding it
explicitly in the SFrame FDE. For now, fix up the logic to at least
move towards modulo operation.
libsframe/
* sframe.c (sframe_fre_check_range_p): New definition.
(sframe_find_fre): Refactor a bit and use the new definition
above.
include/
* sframe.h (SFRAME_FDE_TYPE_PCMASK): Update comment.
libsframe/doc/
* sframe-spec.texi: Fix the text for SFRAME_FDE_TYPE_PCMASK FDE
type.
H.J. Lu [Mon, 9 Mar 2020 21:37:26 +0000 (14:37 -0700)]
ld: Add -z nosectionheader test to bootstrap.exp
PR ld/25617
* testsuite/ld-bootstrap/bootstrap.exp: Add -z nosectionheader
test.
H.J. Lu [Sat, 7 Mar 2020 16:24:35 +0000 (08:24 -0800)]
ld: Add tests for -z nosectionheader and --strip-section-headers
Add tests to verify that the linker option, -z nosectionheader and
objcopy and strip option, --strip-section-headers, work correctly as well
as linker issues an error when dynamic symbol table from PT_DYNAMIC
segment is used.
PR ld/25617
* testsuite/ld-elf/hash-2.d: New file.
* testsuite/ld-elf/no-section-header.exp: Likewise.
* testsuite/ld-elf/pr25617-1-no-sec-hdr.nd: Likewise.
* testsuite/ld-elf/pr25617-1-no-sec-hdr.rd: Likewise.
* testsuite/ld-elf/pr25617-1-static-no-sec-hdr.rd: Likewise.
* testsuite/ld-elf/pr25617-1a-no-sec-hdr.nd: Likewise.
* testsuite/ld-elf/pr25617-1a-no-sec-hdr.rd: Likewise.
* testsuite/ld-elf/pr25617-1a-sec-hdr.rd: Likewise.
* testsuite/ld-elf/pr25617-1a.c: Likewise.
* testsuite/ld-elf/pr25617-1b.c: Likewise.
* testsuite/ld-elf/start-noheader.rd: Likewise.
* testsuite/ld-elf/start-shared-noheader-gnu.rd: Likewise.
* testsuite/ld-elf/start-shared-noheader-sysv.rd: Likewise.
* testsuite/ld-elf/start-shared-noheader.nd: Likewise.
H.J. Lu [Sat, 7 Mar 2020 13:27:12 +0000 (05:27 -0800)]
binutils: Add a --strip-section-headers test
PR ld/25617
* testsuite/binutils-all/objcopy.exp: Run strip-section-headers-1.
* testsuite/binutils-all/strip-section-headers-1.d: New file.
Kaylee Blake [Thu, 5 Mar 2020 03:12:31 +0000 (13:42 +1030)]
ld: Add simple tests for -z nosectionheader
2020-06-06 Kaylee Blake <klkblake@gmail.com>
H.J. Lu <hongjiu.lu@intel.com>
PR ld/25617
* testsuite/ld-elf/nosectionheader-1.d: New file.
* testsuite/ld-elf/nosectionheader-2.d: Likewise.
H.J. Lu [Thu, 5 Mar 2020 04:32:35 +0000 (20:32 -0800)]
bfd: Improve nm and objdump without section header
When there is no section header in an executable or shared library, we
reconstruct dynamic symbol table from the PT_DYNAMIC segment, which
contains DT_HASH/DT_GNU_HASH/DT_MIPS_XHASH, DT_STRTAB, DT_SYMTAB,
DT_STRSZ, and DT_SYMENT entries, to improve nm and objdump. For DT_HASH,
the number of dynamic symbol table entries equals the number of chains.
For DT_GNU_HASH/DT_MIPS_XHASH, only defined symbols with non-STB_LOCAL
indings are in hash table. Since DT_GNU_HASH/DT_MIPS_XHASH place all
symbols with STB_LOCAL binding before symbols with other bindings and
all undefined symbols defined ones in dynamic symbol table, the highest
symbol index in DT_GNU_HASH/DT_MIPS_XHASH is the highest dynamic symbol
table index. We can also get symbol version from DT_VERSYM, DT_VERDEF
and DT_VERNEED entries.
dt_symtab, dt_versym, dt_verdef, dt_verneed, dt_symtab_count,
dt_verdef_count, dt_verneed_count and dt_strtab are added to
elf_obj_tdata to store dynamic symbol table information.
PR ld/25617
* elf-bfd.h (elf_obj_tdata): Add dt_symtab, dt_verdef, dt_verneed,
dt_symtab_count, dt_verdef_count, dt_verneed_count and dt_strtab.
(elf_use_dt_symtab_p): New.
(_bfd_elf_get_dynamic_symbols): Likewise.
(_bfd_elf_get_section_from_dynamic_symbol): Likewise.
* elf.c (bfd_elf_get_elf_syms): Use dynamic symbol table if
neeeded.
(_bfd_elf_get_dynamic_symtab_upper_bound): Likewise.
(_bfd_elf_slurp_version_tables): Likewise.
(offset_from_vma): New function.
(get_hash_table_data): Likewise.
(_bfd_elf_get_dynamic_symbols): Likewise.
(_bfd_elf_get_section_from_dynamic_symbol): Likewise.
(_bfd_elf_get_symbol_version_name): Likewise.
* elfcode.h (elf_object_p): Call _bfd_elf_get_dynamic_symbols
to reconstruct dynamic symbol table from PT_DYNAMIC segment if
there is no section header.
(elf_slurp_symbol_table): Use dynamic symbol table if neeeded.
Don't free isymbuf when dynamic symbol table is used.
* elflink.c (elf_link_is_defined_archive_symbol): Return wrong
format error when dynamic symbol table is used.
(elf_link_add_object_symbols): Likewise.
H.J. Lu [Wed, 31 May 2023 19:36:49 +0000 (12:36 -0700)]
ELF: Discard non-alloc sections without section header
Discard non-alloc sections when section headers are stripped.
bfd/
PR ld/25617
* elf.c (_bfd_elf_assign_file_positions_for_non_load): Skip
non-load sections without section header.
(_bfd_elf_write_object_contents): Don't set the sh_name field
without section header. Write out the .shstrtab section only
if its sh_offset field isn't -1.
binutils/
PR ld/25617
* objcopy.c (is_strip_section_1): Remove non-alloc sections for
--strip-section-headers.
ld/
PR ld/25617
* ldlang.c (lang_discard_section_p): Discard non-alloc sections
if we are stripping section headers.
Kaylee Blake [Wed, 4 Mar 2020 08:48:07 +0000 (19:18 +1030)]
ELF: Strip section header in ELF objects
Section header isn't mandatory on ELF executable nor shared library.
This patch adds a new linker option, -z nosectionheader, to omit ELF
section header, a new objcopy and strip option, --strip-section-headers,
to remove ELF section headers.
bfd/
2023-06-06 H.J. Lu <hongjiu.lu@intel.com>
Kaylee Blake <klkblake@gmail.com>
PR ld/25617
* bfd.c (BFD_NO_SECTION_HEADER): New.
(BFD_FLAGS_SAVED): Add BFD_NO_SECTION_HEADER.
(BFD_FLAGS_FOR_BFD_USE_MASK): Likewise.
* elfcode.h (elf_swap_ehdr_out): Omit section header with
BFD_NO_SECTION_HEADER.
(elf_write_shdrs_and_ehdr): Likewise.
* elfxx-target.h (TARGET_BIG_SYM): Add BFD_NO_SECTION_HEADER
to object_flags.
(TARGET_LITTLE_SYM): Likewise.
* bfd-in2.h: Regenerated.
binutils/
2023-06-06 H.J. Lu <hongjiu.lu@intel.com>
PR ld/25617
* NEWS: Mention --strip-section-headers for objcopy and strip.
* objcopy.c (strip_section_headers): New.
(command_line_switch): Add OPTION_STRIP_SECTION_HEADERS.
(strip_options): Add --strip-section-headers.
(copy_options): Likewise.
(copy_usage): Add --strip-section-headers.
(strip_usage): Likewise.
(copy_object): Handle --strip-section-headers for ELF files.
(strip_main): Handle OPTION_STRIP_SECTION_HEADERS.
(copy_main): Likewise.
* doc/binutils.texi: Document --strip-section-headers for objcopy
and strip.
ld/
2023-06-06 H.J. Lu <hongjiu.lu@intel.com>
Kaylee Blake <klkblake@gmail.com>
PR ld/25617
* NEWS: Mention -z nosectionheader.
* emultempl/elf.em: Support -z sectionheader and
-z nosectionheader.
* ld.h (ld_config_type): Add no_section_header.
* ld.texi: Document -z sectionheader and -z nosectionheader.
* ldlang.c (ldlang_open_output): Handle
config.no_section_header.
* lexsup.c (parse_args): Enable --strip-all with
-z nosectionheader. Disallow -r with -z nosectionheader.
(elf_static_list_options): Add -z sectionheader and
-z nosectionheader.
Matthias Klose [Thu, 29 Jun 2023 13:44:52 +0000 (14:44 +0100)]
Ignore --prefix-file-map compiler option whist running testsuite.
Matthias Klose [Thu, 29 Jun 2023 13:30:55 +0000 (14:30 +0100)]
ignore lto-wrapper warnings for lto builds.
I see these warnings from time to time, when configuring a build with --enable-pgo-build=lto, I haven't yet found out why I see these sometime, and why not. E.g. https://gcc.gnu.org/PR109241. Just ignore these when they appear in test cases. lto-wrapper: warning: using serial compilation of N LTRANS jobs
GDB Administrator [Thu, 29 Jun 2023 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
Vladimir Mezentsev [Mon, 26 Jun 2023 21:36:50 +0000 (14:36 -0700)]
gprofng: Add new tests
gprofng/ChangeLog
2023-06-26 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
* Makefile.am: Pass CLOCK_GETTIME_LINK to the testsuite
* Makefile.in: Rebuild.
* testsuite/gprofng.display/gp-archive.exp: New file.
* testsuite/gprofng.display/gp-collect-app_F.exp: New file.
* testsuite/gprofng.display/setpath_map.exp: New file.
* testsuite/lib/smalltest.c: New file.
Andrew Carlotti [Wed, 28 Jun 2023 17:05:28 +0000 (18:05 +0100)]
aarch64: Remove version dependencies from features
Many instructions were enabled only when both a feature flag and a minimum
architecture version are specified. This behaviour differs from GCC, which (in
most cases) allows features to be enabled at any architecture version.
There is no need for the toolchain to restrict combinations of unrelated
features in this way, so this patch removes the unnecessary dependencies.
Tom Tromey [Wed, 28 Jun 2023 15:39:37 +0000 (09:39 -0600)]
Remove Python 2 from gdb documentation
GDB can't be built using Python 2 any more, so remove the remaining
vestiges of this from the documentation.
Approved-By: Eli Zaretskii <eliz@gnu.org>
Michael Matz [Mon, 26 Jun 2023 15:11:31 +0000 (17:11 +0200)]
section-match: Check parent archive name as well
rewriting the section matching routines lost a special case
of matching: section statements of the form
NAME(section-glob)
normally match against NAME being an object file, but like in
the exclude list we happened to accept archive names as NAME
(undocumented). The documented way to specify (all) archive members
is by using e.g.
lib.a:(section-glob)
(that does work also with the prefix tree matcher).
But I intended to not actually change behaviour with the prefix
tree implementation. So, let's also implement checking against
archive names with a similar FIXME comment we already have in
walk_wild_file_in_exclude_list.
PR 30590
ld/
* ldlang.c (walk_wild_section_match): Also look at archive
parents for a name match.
Tom Tromey [Tue, 13 Jun 2023 15:36:35 +0000 (09:36 -0600)]
Fix handling of DW_TAG_unspecified_type for Ada
Commit
80eaec735e ("[gdb/symtab] Handle named DW_TAG_unspecified_type
DIE") changed the handling of DW_TAG_unspecified_type. Before this
change, such types were not entered into the symbol table.
It turns out that, when such a type is in the symtab, it can cause
failures in Ada. In particular, a private type in another package may
be seen locally as "void".
Now, it would probably be better to fix this via check_typedef.
However, that is somewhat difficult given the state of the DWARF
reader -- in particular with gdb_index, this would require expanding
potentially many CUs to find the correct type.
Instead, this patch changes gdb to not enter a symbol for an
unspecified type -- but only for Ada.
Tom Tromey [Tue, 13 Jun 2023 18:51:55 +0000 (12:51 -0600)]
Remove some Python 2 code
I found some Python 2 compatibility code in gdb's Python library.
There's no need for this any more, so this removes it. There is still
a bit more of this remaining in __init__.py, but I haven't tried
removing that yet.
Reviewed-By: Bruno Larsen <blarsen@redhat.com>
Nick Clifton [Wed, 28 Jun 2023 12:49:43 +0000 (13:49 +0100)]
Stop the linker's --dependency-file option from including temporary lto files.
PR 30568
* ldfile.c (ldfile_try_open_bfd): Do not track lto generated temporary files.
Nick Clifton [Wed, 28 Jun 2023 10:43:13 +0000 (11:43 +0100)]
Updated French translation for the gold sub-directory
mengqinggang [Thu, 22 Jun 2023 02:32:49 +0000 (10:32 +0800)]
LoongArch: gas: Add LSX and LASX instructions test
gas/ChangeLog:
* testsuite/gas/loongarch/vector.d: New test.
* testsuite/gas/loongarch/vector.s: New test.
mengqinggang [Thu, 22 Jun 2023 02:35:28 +0000 (10:35 +0800)]
LoongArch: gas: Add lsx and lasx instructions support
gas/ChangeLog:
* config/tc-loongarch.c (md_parse_option): Add lsx and lasx option.
(loongarch_after_parse_args): Add lsx and lasx option.
opcodes/ChangeLog:
* loongarch-opc.c (struct loongarch_ase): Add lsx and lasx
instructions.
mengqinggang [Sun, 25 Jun 2023 09:47:42 +0000 (17:47 +0800)]
LoongArch: Add R_LARCH_64_PCREL relocation support
Gas defaults to emit R_LARCH_ADD64/R_LARCH_SUB64 unless explcitly declared
to emit R_LARCH_64_PCREL.
The LoongArch ABI at here:
https://github.com/loongson/la-abi-specs/blob/release/la-abi.adoc
bfd/ChangeLog:
* bfd-in2.h (not): Add R_LARCH_64_PCREL
* elfnn-loongarch.c (perform_relocation): Likewise.
* elfxx-loongarch.c: Likewise.
* libbfd.h: Likewise.
* reloc.c: Likewise.
gas/ChangeLog:
* config/tc-loongarch.c (loongarch_args_parser_can_match_arg_helper):
(md_apply_fix): Add R_LARCH_64_PCREL.
* testsuite/gas/loongarch/64_pcrel.d: New test.
* testsuite/gas/loongarch/64_pcrel.s: New test.
include/ChangeLog:
* elf/loongarch.h (RELOC_NUMBER): Add R_LARCH_64_PCREL.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/ld-loongarch-elf.exp: Add test.
* testsuite/ld-loongarch-elf/64_pcrel.d: New test.
* testsuite/ld-loongarch-elf/64_pcrel.s: New test.
GDB Administrator [Wed, 28 Jun 2023 00:00:25 +0000 (00:00 +0000)]
Automatic date update in version.in
Indu Bhagat [Tue, 27 Jun 2023 18:57:44 +0000 (11:57 -0700)]
binutils/NEWS: add note about upcoming libsframe changes
Some of these changes update the ABI in an incompatible way.
Indu Bhagat [Tue, 27 Jun 2023 18:56:26 +0000 (11:56 -0700)]
libsframe: bfd: use uint32_t for return type of get_num_fidx APIs
Keep the data types usage in libsframe look consistent.
bfd/
* elf-sframe.c (_bfd_elf_merge_section_sframe): Use uint32_t
type alias.
* libsframe/sframe.c (sframe_decoder_get_funcdesc_at_index):
Likewise.
(sframe_decoder_get_num_fidx): Likewise.
(sframe_encoder_get_num_fidx): Likewise.
include/
* sframe-api.h (sframe_decoder_get_num_fidx): Likewise.
(sframe_encoder_get_num_fidx): Likewise.
Indu Bhagat [Tue, 27 Jun 2023 18:56:13 +0000 (11:56 -0700)]
libsframe: use appropriate data types for args of sframe_encode
include/
* sframe-api.h (sframe_encode): Use of uint8_t is more
appropriate.
libsframe/
* sframe.c (sframe_encode): Likewise.
Indu Bhagat [Tue, 27 Jun 2023 18:56:04 +0000 (11:56 -0700)]
libsframe: use uint8_t for return type of sframe_fre_get_base_reg_id
Use a more appropriate data type.
include/
* sframe-api.h (sframe_fre_get_base_reg_id): Use uint8_t as
return type.
libsframe/
* sframe-dump.c (dump_sframe_func_with_fres): Use uint8_t type
for base reg id.
* sframe.c (sframe_fre_get_base_reg_id): Use uin8_t as return
type.
Indu Bhagat [Tue, 27 Jun 2023 18:55:59 +0000 (11:55 -0700)]
libsframe: use uint8_t instead of unsigned char for abi_arch
Use uint8_t consistently for identifying ABI/arch in SFrame format.
bfd/
* elf-sframe.c (_bfd_elf_merge_section_sframe):
libsframe/
* sframe-dump.c (is_sframe_abi_arch_aarch64): Use uint8_t for
local variable.
* sframe.c (sframe_decoder_get_abi_arch): Update return type to
uint8_t.
(sframe_encoder_get_abi_arch): Likewise.
include/
* sframe-api.h (sframe_decoder_get_abi_arch): Likewise.
(sframe_encoder_get_abi_arch): Likewise.
Indu Bhagat [Tue, 27 Jun 2023 18:55:38 +0000 (11:55 -0700)]
libsframe: bfd: use uint32_t for return type of sframe_calc_fre_type
Use uint32_t type alias consistently for all APIs in libsframe.
bfd/
* elfxx-x86.c (_bfd_x86_elf_create_sframe_plt): Adjust for the
changed return type.
libsframe/
* sframe.c (sframe_calc_fre_type): Use uint32_t for return type.
include/
* sframe-api.h (sframe_calc_fre_type): Likewise.
Indu Bhagat [Tue, 27 Jun 2023 18:55:08 +0000 (11:55 -0700)]
libsframe: use uint32_t for fre_type and fde_type function args
The API sframe_fde_create_func_info is provided by libsframe. Current
users are the bfd linker. Adjust the argument type for the variables
carrying the SFrame FRE type and SFrame FDE type to consistenly use
uint32_t type alias.
include/
* sframe-api.h (sframe_fde_create_func_info): Use uint32_t
instead of unsigned int.
libsframe/
* sframe.c (sframe_get_fre_type): Likewise.
(sframe_get_fde_type): Likewise.
(flip_fre_start_address): Likewise.
(sframe_fre_start_addr_size): Likewise.
(sframe_fre_entry_size): Likewise.
(flip_fre): Likewise.
(flip_sframe): Likewise.
(sframe_fde_create_func_info): Likewise.
(sframe_calc_fre_type): Likewise.
(sframe_decode_fre_start_address): Likewise.
(sframe_decode_fre): Likewise.
(sframe_find_fre): Likewise.
(sframe_decoder_get_fre): Likewise.
(sframe_encoder_add_fre): Likewise.
(sframe_encoder_write_fre_start_addr): Likewise.
(sframe_encoder_write_fre): Likewise.
(sframe_encoder_write_sframe): Likewise.
Indu Bhagat [Tue, 27 Jun 2023 18:55:00 +0000 (11:55 -0700)]
libsframe: update the semantics of sframe_fre_get_fp_offset
Until now, sframe_fre_get_fp_offset () would return
SFRAME_ERR_FREOFFSET_NOPRESENT if the ABI uses fixed FP offset. A stack
tracer, then, would call an explicit sframe_decoder_get_fixed_fp_offset ()
to get the FP offset.
On second look, it appears to make sense to hide these details of
whether the FP offset is fixed or not in an ABI from the consumer. Now,
with the changed semantics, the call to sframe_fre_get_fp_offset () will
fetch the fixed FP offset if applicable, or get the FP offset from FRE
when there is no fixed FP offset.
This patch changes the behavior of sframe_fre_get_fp_offset (): it turns
an error into non-error. This change will be included with the next
release of libsframe, where all the exposed symbols will be versioned
with version node LIBSFRAME_1.0 for the first time.
libsframe/
* sframe.c (sframe_fre_get_fp_offset): Return the fixed offset, if
applicable. Else return the FP offset from the FRE.
Indu Bhagat [Tue, 27 Jun 2023 18:54:49 +0000 (11:54 -0700)]
libsframe: update the semantics of sframe_fre_get_ra_offset
Until now, sframe_fre_get_ra_offset () would return
SFRAME_ERR_FREOFFSET_NOPRESENT if the ABI uses fixed RA offset (e.g.,
AMD64). A stack tracer, then, will call an explicit
sframe_decoder_get_fixed_ra_offset () to get the RA offset.
On second look, it appears to make sense to hide these details of
whether the RA offset is fixed or not from the consumer. Now, with the
changed semantics, the call to sframe_fre_get_ra_offset () will fetch
the fixed RA offset if applicable, or get the RA offset from FRE when
there is no fixed RA offset.
Adjustments need to be made to ensure the textual dump remains the same
as preivous. Currently, e.g., if RA is not being tracked per FRE,
following is seen with objdump --sframe:
STARTPC CFA FP RA
000000000000NNNN sp+X u u
This patch changes the behavior of sframe_fre_get_ra_offset: it turns an
error into non-error. This change will be included with the next
release of libsframe, where all exposed symbols will be versioned for
the first time.
libsframe/
* sframe.c (sframe_fre_get_ra_offset): Return the fixed offset,
if applicable. Else return the RA offset from the FRE.
* sframe-dump.c (dump_sframe_func_with_fres): Make adjustments
to keep the textual dump same as previous.
Indu Bhagat [Tue, 27 Jun 2023 18:54:12 +0000 (11:54 -0700)]
libsframe: add symbol versioning
Define an empty base version LIBSFRAME_0.0 and add all symbols to
version LIBSFRAME_1.0.
The previous release of libsframe (libsframe.so.0) did not have
versioned symbols. Adding a libsframe.ver file so that future releases
of the library (and its consumers) can manage the changes better.
For Solaris ld, use -M mapfile command line option. libsframe does not
restrict the set of exported symbols, so at this time there is no need
to fall back on the libtool's -export-symbols option for platforms where
some other linker (with a different command line option for symbol
versioning) may be used.
libsframe/
* Makefile.am: Use symbol versioning for libsframe.
* Makefile.in: Regenerated.
* configure: Check for Solaris ld.
* configure.ac: Regenerated.
* libsframe.ver: New file.
Indu Bhagat [Tue, 27 Jun 2023 18:53:40 +0000 (11:53 -0700)]
libsframe: remove sframe_get_funcdesc_with_addr API
This is an incompatible ABI change in libsframe.
The interface provided by this function is not a healthy abstraction to
expose: the return type sframe_func_desc_entry, which is defined in
include/sframe.h (the SFrame binary format definition). This ties up
the library in a undesirable way. Most importantly, this function
should technically not be directly necessary for a stack tracer. A
stack tracer will likely only need to do a sframe_find_fre ().
Rename the API to continue to use the functionality internally in the
library. bfd/linker does not use this function.
Change the return type of the previous definition and make a note about
its planned deprecation.
include/
* sframe-api.h: Change return type of sframe_get_funcdesc_with_addr.
Add comment for intention to deprecate.
libsframe/
*sframe.c (sframe_get_funcdesc_with_addr): Change return type
and set error code. This API is deprecated.
(sframe_get_funcdesc_with_addr_internal): New definition for
internal use.
(sframe_find_fre): Use sframe_get_funcdesc_with_addr_internal
instead.
Indu Bhagat [Tue, 27 Jun 2023 18:52:43 +0000 (11:52 -0700)]
libsframe: add library versioning
lisbframe was first released with Bintuils 2.40. As the library
evolves, some changes will break the ABI. Add library versioning for
users to manage these changes.
For the next release of the library (libsframe.so.1), incompatible ABI
changes are planned. These will include:
- Deprecation of some APIs, like sframe_get_funcdesc_with_addr (), and
- Change in the contract of some APIs (e.g., return type, behavior).
In libtool-version, set the current to 1 to prepare for the upcoming
release. Reset revision and age to 0.
Add libtool-version file to EXTRA_DIST.
libsframe/
* Makefile.am: Use libtool versioning.
* Makefile.in: Regenerated.
* libtool-version: New file.
Philipp Tomsich [Tue, 27 Jun 2023 13:22:49 +0000 (07:22 -0600)]
RISC-V: Support Zicond extension
This implements the Zicond (conditional integer operations) extension,
as of version 1.0-rc2.
The Zicond extension acts as a building block for branchless sequences
including conditional-arithmetic, conditional-logic and
conditional-select/move.
The following instructions constitute Zicond:
- czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1
- czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1
See
https://github.com/riscv/riscv-zicond/releases/download/v1.0-rc2/riscv-zicond-v1.0-rc2.pdf
for the proposed specification and usage details.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Recognize
INSN_CLASS_ZICOND.
(riscv_multi_subset_supports_ext): Recognize INSN_CLASS_ZICOND.
gas/ChangeLog:
* testsuite/gas/riscv/zicond.d: New test.
* testsuite/gas/riscv/zicond.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CZERO_EQZ): Define.
(MASK_CZERO_EQZ): Define.
(MATCH_CZERO_NEZ): Define,
(MASK_CZERO_NEZ): Define.
(DECLARE_INSN): Add czero.eqz and czero.nez.
* opcode/riscv.h (enum riscv_insn_class): Add
INSN_CLASS_ZICOND.
opcodes/ChangeLog:
* riscv-opc.c: Add czero.eqz and czero.nez.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Nick Clifton [Tue, 27 Jun 2023 09:15:51 +0000 (10:15 +0100)]
Add note about adding ChangeLog.git to src-release.sh
Cui, Lili [Tue, 27 Jun 2023 07:58:12 +0000 (07:58 +0000)]
gprofng: Update intel url
Since the old software.intel.com has been removed, update a new one.
gprofng/ChangeLog
2023-06-27 Lili Cui <lili.cui@intel.com>
* gp-display-html/gp-display-html.in: Update intel url.
GDB Administrator [Tue, 27 Jun 2023 00:00:23 +0000 (00:00 +0000)]
Automatic date update in version.in
Nick Clifton [Mon, 26 Jun 2023 16:37:19 +0000 (17:37 +0100)]
Fix gas tests for aarch64-pe
Nick Clifton [Mon, 26 Jun 2023 14:47:15 +0000 (15:47 +0100)]
Synchromize libiberty sources with master version in gcc repository
Nick Clifton [Mon, 26 Jun 2023 13:11:30 +0000 (14:11 +0100)]
Sync config.guess and config.sub with upstream master versions.
Nick Clifton [Mon, 26 Jun 2023 12:24:19 +0000 (13:24 +0100)]
Updated French translation for the gprof sub-directory
GDB Administrator [Mon, 26 Jun 2023 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
Feiyang Chen [Fri, 16 Jun 2023 03:16:10 +0000 (11:16 +0800)]
LoongArch: Support referring to FCSRs as $fcsrX
Previously, FCSRs were referred to as $rX, which seemed strange.
We refer to FCSRs as $fcsrX, which ensures compatibility with LLVM
IAS as well.
gas/ChangeLog:
* config/tc-loongarch.c:
(loongarch_fc_normal_name): New definition.
(loongarch_fc_numeric_name): New definition.
(loongarch_single_float_opcodes): Modify `movgr2fcsr` and
`movfcsr2gr`.
testsuite/gas/loongarch/float_op.d: Likewise.
testsuite/gas/loongarch/float_op.s: Likewise.
include/ChangeLog:
* opcode/loongarch.h:
(loongarch_fc_normal_name): New extern.
(loongarch_fc_numeric_name): New extern.
opcodes/ChangeLog:
* opcodes/loongarch-dis.c (loongarch_after_parse_args): Support
referring to FCSRs as $fcsrX.
* opcodes/loongarch-opc.c (loongarch_args_parser_can_match_arg_helper):
Likewise.
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
GDB Administrator [Sun, 25 Jun 2023 00:00:09 +0000 (00:00 +0000)]
Automatic date update in version.in
GDB Administrator [Sat, 24 Jun 2023 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
Thiago Jung Bauermann [Wed, 31 May 2023 19:46:29 +0000 (21:46 +0200)]
gdb/testsuite: Avoid infinite loop in gdb.reverse/step-reverse.exp
This testcase sometimes gets stuck in a loop for hours when running in our
CI. The problem is that due to an issue unrelated to reverse debugging the
inferior exits early, and because of the overly generic ".*" pattern the
testcase keeps sending the "next" command without noticing that the
inferior is gone.
gdb_test_multiple has a pattern to detect that "The program is not being
run.", but since it is placed after the patterns from the caller it won't
be triggered. It also has a timeout pattern but because it is triggered
between successful matches, each time the test matches the '-re -wrap ".*"'
this counts as a successful match and the timeout is reset.
Since the test binary is compiled with debug information, fix by changing
one of the generic patterns to match entering the main function and the
other one to match the source code line number that is shown by GDB right
after the "step" command.
Also, as a precaution add a maximum number of times the "next" command will
be sent.
Co-Authored-By: Tom de Vries <tdevries@suse.de>
Reviewed-By: Bruno Larsen <blarsen@redhat.com>
Approved-By: Tom de Vries <tdevries@suse.de>
Alan Modra [Fri, 23 Jun 2023 01:07:53 +0000 (10:37 +0930)]
[GOLD] PowerPC64 huge branch dynamic relocs
PowerPC64 gold and ld.bfd implement an indirect branch trampoline,
used when the destination of a branch exceeds a bounce through another
"b" instruction. When generating PIEs or shared libraries, the
addresses need dynamic relocations. This was implemented in gold
using a dedicated relocation section, but this means the relative
relocations for these addresses are not sorted properly with other
dynamic relative relocations: gold doesn't support merging relocation
sections, then sorting. Instead we need to use a single .rela.dyn
section.
This is done by increasing the size of rela_dyn_ during do_relax to
account for needed dynamic relocations, delaying adding the actual
relocations until the end of relaxation once the layout has
stabilised.
* powerpc.cc (Target_powerpc): Add rela_dyn_size_;
(update_current_size): New function.
(Target_powerpc::do_relax): Capture the size of rela_dyn_ at
the start of relaxation. Artifically increase its size during
relaxation to account for needed indirect branches, and add
those relocations at the end.
(Output_data_brlt_powerpc::rel_, reset_brlt_sizes),
(finalize_brlt_sizes, add_reloc, set_current_size): Delete.
(Target_powerpc::make_brlt_section): Don't make reloc section.
Alan Modra [Fri, 23 Jun 2023 00:08:13 +0000 (09:38 +0930)]
[GOLD] Support setting DT_RELACOUNT late
PowerPC gold adds relative dynamic relocs in do_relax. These aren't
accounted for in the value set in add_target_dynamic_tags, which is
called before do_relax. Provide a way of setting DT_RELCOUNT and
DT_RELACOUNT at the point where .dynamic is written.
* layout.cc (Layout::add_target_dynamic_tags): Add custom_relcount
parameter. Emit DT_RELCOUNT/RELACOUNT as a custom target handled
dynamic tag if set.
* layout.h(Layout::add_target_dynamic_tags): Update prototype.
* aarch64.cc (Target_aarch64::do_finalize_sections): Adjust
add_target_dynamic_tags call.
* arm.cc (Target_arm::do_finalize_sections): Likewise.
* i386.cc (Target_i386::do_finalize_sections): Likewise.
* mips.cc (Target_mips::do_finalize_sections): Likewise.
* s390.cc (Target_s390::do_finalize_sections): Likewise.
* sparc.cc (Target_sparc::do_finalize_sections): Likewise.
* tilegx.cc (Target_tilegx::do_finalize_sections): Likewise.
* x86_64.cc (Target_x86_64::do_finalize_sections): Likewise.
* powerpc.cc (Target_powerpc::do_finalize_sections): Likewise.
(Target_powerpc::do_dynamic_tag_custom_value): New function.
Alan Modra [Thu, 22 Jun 2023 23:18:38 +0000 (08:48 +0930)]
[GOLD] powerpc DT_RELACOUNT
DT_RELACOUNT was calculated incorrectly, and relative relocs not
sorted as they should be to the start of .rela.dyn, due to adding one
particular class of dynamic reloc using the wrong "add" method.
* powerpc.cc (Target_powerpc::Scan::global): Add relative
dyn relocs for ADDR64 and similar using add_global_relative.
Alan Modra [Fri, 23 Jun 2023 02:06:13 +0000 (11:36 +0930)]
lto test fails with -fno-inline in CFLAGS
Putting -fno-inline in CFLAGS results in these failures.
FAIL: Build liblto-17b.so 1
FAIL: PR ld/12365
FAIL: PR ld/13183
* ld-plugin/lto.exp: Add -finline to compiler flags in some tests.
Tom Tromey [Fri, 23 Jun 2023 02:34:56 +0000 (20:34 -0600)]
Fix off-by-one error
Simon pointed out that commit
a2bbca9fa5e ("Use std::vector<bool> for
agent_expr::reg_mask") caused a regression in libstdc++ debug mode.
This was due to an off-by-one error in a vector resize. This patch
fixes the problem.
GDB Administrator [Fri, 23 Jun 2023 00:00:10 +0000 (00:00 +0000)]
Automatic date update in version.in
Ilya Leoshkevich [Wed, 21 Jun 2023 21:55:42 +0000 (23:55 +0200)]
gdb/testsuite: fix gdb.python/py-unwind.exp with python >= 3.11
Python 3.11 changed the AttributeError message - see commit
0cb765b2cec9 ("bpo-46730: Add more info to @property AttributeError
messages (GH-31311)"). Add the new message to the expectations.
Approved-By: Tom Tromey <tom@tromey.com>
Link: https://sourceware.org/pipermail/gdb-patches/2023-June/200433.html
H.J. Lu [Thu, 22 Jun 2023 19:37:51 +0000 (12:37 -0700)]
Revert "x86: Don't check if AVX512 template requires AVX512VL"
This reverts commit
c7face14225296a2f5d3ebeb8ace88c166d80c3e.
Tom de Vries [Thu, 22 Jun 2023 17:15:23 +0000 (19:15 +0200)]
[gdb/testsuite] Clean or check standard_output_file dir in gdb_init
In commit
e2adba909e7 ("[gdb/testsuite] Clean up before compilation in
gdb.ada/call-no-debug.exp") I added some code in the test-case to remove some
files at the start of the test-case:
...
remote_file host delete [standard_output_file prog.o]
remote_file host delete [standard_output_file prog.ali]
...
Then in commit
b7b77500dc5 ("[gdb/testsuite] Clean standard_output_file dir in
gdb_init") I tried to do this more structurally, by cleaning up the entire
standard_output_file directory, for all test-cases.
This caused a regression when using "make check -j 2", due to the cleanup
removing the active gdb.log, so I reverted the commit.
Try again, this time handling the two cases separately.
If the standard_output_file directory contains an active gdb.log, check that
the directory contains no files other than gdb.log and gdb.sum. This puts
the reponsibility for the cleanup at the callers in gdb/testsuite/Makefile.in
which use --outdir.
If the standard_output_file directory doesn't contain an active gdb.log, clean
it by removing the entire directory.
An exception is made for performance tests, where cleaning up the
standard_output_file dir is the wrong thing to do, because an invocation with
GDB_PERFTEST_MODE == run is intended to reuse binaries left there by an
earlier invocation with GDB_PERFTEST_MODE == compile.
Tested on x86_64-linux.
Suggested-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Tom Tromey <tom@tromey.com>
Tested-By: Luis Machado <luis.machado@arm.com>
Tom Tromey [Thu, 1 Jun 2023 17:54:17 +0000 (11:54 -0600)]
Implement DAP "hover" context
A DAP client can request that an expression be evaluated in "hover"
context, meaning that it should not cause side effects. In gdb, this
can be implemented by temporarily setting a few "may-" parameters to
"off".
In order to make this work, I had to also change "may-write-registers"
so that it can be changed while the program is running. I don't think
there was any reason for this prohibition in the first place.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=30476
Tom Tromey [Wed, 31 May 2023 17:21:09 +0000 (11:21 -0600)]
Implement DAP logging breakpoints
DAP allows a source breakpoint to specify a log message. When this is
done, the breakpoint acts more like gdb's dprintf: it logs a message
but does not cause a stop.
I looked into implement this using dprintf with the new %V printf
format. However, my initial attempt at this did not work, because
when the inferior is continued, the dprintf output is captured by the
gdb.execute call. Maybe this could be fixed by having all
inferior-continuation commands use the "&" form; the main benefit of
this would be that expressions are only parsed a single time.
Tom Tromey [Fri, 26 May 2023 19:35:52 +0000 (13:35 -0600)]
Handle supportsVariablePaging in DAP
A bug report about the supportsVariablePaging capability in DAP
resulted in a clarification: when this capability is not present, DAP
implementations should ignore the paging parameters to the "variables"
request. This patch implements this clarification.
Tom Tromey [Thu, 25 May 2023 18:25:43 +0000 (12:25 -0600)]
Implement type checking for DAP breakpoint requests
I realized that with a small refactoring, it is possible to type-check
the parameters to the various DAP breakpoint requests. This would
have caught the earlier bug involving hitCondition.