Anton Blanchard [Mon, 8 Aug 2022 21:08:02 +0000 (07:08 +1000)]
tests/trace: Test trace vs system call interrupt
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling [Mon, 8 Aug 2022 05:54:14 +0000 (15:54 +1000)]
Merge pull request #387 from antonblanchard/gitignore
Add litesdcard/build to gitignore
Anton Blanchard [Sun, 7 Aug 2022 07:44:04 +0000 (17:44 +1000)]
Add litesdcard/build to gitignore
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Paul Mackerras [Fri, 5 Aug 2022 00:52:31 +0000 (10:52 +1000)]
Merge pull request #384 from antonblanchard/litedram-update
Litedram update
Anton Blanchard [Thu, 4 Aug 2022 11:26:17 +0000 (21:26 +1000)]
litedram: Regenerate
Regenerate from upstream litex. Something in the update has improved
memory read and write performance quite a lot on my Nexys Video:
Before:
Write speed: 83.2MiB/s
Read speed: 140.4MiB/s
After:
Write speed: 352.1MiB/s
Read speed: 218.5MiB/s
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 4 Aug 2022 11:25:13 +0000 (21:25 +1000)]
litedram: MIGEN_GIT_SHA1 no longer defined
MIGEN_GIT_SHA1 is no longer defined in upstream litex, so remove it.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Paul Mackerras [Thu, 4 Aug 2022 09:35:52 +0000 (19:35 +1000)]
Merge pull request #383 from antonblanchard/fix-sdcard
litesdcard: Fix and regenerate Verilog
Anton Blanchard [Thu, 4 Aug 2022 08:24:56 +0000 (18:24 +1000)]
litesdcard: Fix and regenerate Verilog
Fix the litex generate script to pass frequencies in Hz. Regenerate
the litesdcard Verilog for both Xilinx and Lattice. This fixes
litesdcard on my Nexys Video.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Paul Mackerras [Mon, 1 Aug 2022 05:53:01 +0000 (15:53 +1000)]
Merge pull request #381 from shingarov/gitignore-artifacts
Gitignore build artifacts
Paul Mackerras [Mon, 1 Aug 2022 05:52:33 +0000 (15:52 +1000)]
Merge pull request #378 from mikey/ux-cleanup
Metavalue cleanup
Boris Shingarov [Fri, 29 Jul 2022 07:47:56 +0000 (03:47 -0400)]
Gitignore build artifacts
Building the mw_debug program leaves build artifacts in
microwatt/scripts/mw_debug
causing noise in the output of `git status`.
This commit adds them to .gitignore.
Signed-off-by: Boris Shingarov <shingarov@labware.com>
Michael Neuling [Thu, 28 Jul 2022 05:29:25 +0000 (15:29 +1000)]
test: Add test for metavalues
Make sure they don't increase in future
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 28 Jul 2022 05:28:25 +0000 (15:28 +1000)]
tests: Update FPU test output
The following commit added two tests but didn't update the tests
outputs:
commit
73cc5167ec1ea591d9da43f2e392b5202f045f32
Author: Paul Mackerras <paulus@ozlabs.org>
Date: Mon May 9 19:18:42 2022 +1000
Use FPU for division instructions if we have an FPU
This patch updates these using tests/update_console_tests
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 28 Jul 2022 04:47:51 +0000 (14:47 +1000)]
tests: Minor script cleanups
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:32:37 +0000 (10:32 +1000)]
Metavalue cleanup for register_file.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:32:37 +0000 (10:32 +1000)]
Metavalue cleanup for pmu.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:32:37 +0000 (10:32 +1000)]
Metavalue cleanup for rotator.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:32:16 +0000 (10:32 +1000)]
Metavalue cleanup for mmu.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:32:05 +0000 (10:32 +1000)]
Metavalue cleanup for loadstore1.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:31:53 +0000 (10:31 +1000)]
Metavalue cleanup for icache.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:31:43 +0000 (10:31 +1000)]
Metavalue cleanup for fpu.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:31:32 +0000 (10:31 +1000)]
Metavalue cleanup for fetch1.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:31:20 +0000 (10:31 +1000)]
Metavalue cleanup for execute1.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:30:57 +0000 (10:30 +1000)]
Metavalue cleanup for decoder1.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Thu, 14 Jul 2022 00:29:11 +0000 (10:29 +1000)]
Metavalue cleanup for helpers.vhdl
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Wed, 27 Jul 2022 23:50:26 +0000 (09:50 +1000)]
Metavalue cleanup for common.vhdl
This affects other files which have been included here.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Tue, 26 Jul 2022 00:08:33 +0000 (10:08 +1000)]
Merge pull request #379 from paulusmack/master
Lots of improvements
Michael Neuling [Mon, 25 Jul 2022 06:31:12 +0000 (16:31 +1000)]
Merge pull request #380 from iagocaran/master
tests/pmu: Add load/store completed and instruction/cycle count
Michael Neuling [Mon, 25 Jul 2022 05:03:40 +0000 (15:03 +1000)]
tests/pmu: Cleanup whitespace in pmc.c
Fixup tabs vs space and trailing whitespace.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Paul Mackerras [Thu, 14 Jul 2022 05:47:21 +0000 (15:47 +1000)]
Use register addresses from decode1 for dependency tracking
This improves timing a little because the register addresses now come
directly from a latch instead of being calculated by
decode_input_reg_*. The asserts that check that the two are the same
are now in decode2 rather than register_file.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 21 Feb 2022 22:30:05 +0000 (09:30 +1100)]
register_file: Make read access to register file synchronous
With this, the register RAM is read synchronously using the addresses
supplied by decode1. That means the register RAM can now be block RAM
rather than LUT RAM.
Debug accesses are done via the B port on cycles when decode1
indicates that there is no valid instruction or the instruction
doesn't use a [F]RB operand.
We latch the addresses being read in each cycle and use the same
address next cycle if stalled. Data that is being written is latched
and a multiplexer on each read port then supplies the latched write
data if the read address for that port equals the write address.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 21 Feb 2022 08:29:09 +0000 (19:29 +1100)]
decode1: Work out register addresses in decode1
This adds some relatively simple logic to decode1 to compute the
GPR/FPR addresses that an instruction will access. It always computes
three addresses regardless of whether the instruction will actually
use all of them. The main things it computes are whether the
instruction uses the RS field or the RC field for the 3rd operand, and
whether the operands are FPRs or GPRs (it is possible for RS to be an
FPR but RA and RB to be GPRs, as for example with stfdx).
At the moment all we do with these computed register addresses is to
assert that they are identical to the ones coming from decode2 one
cycle later.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Wed, 23 Mar 2022 18:02:28 +0000 (18:02 +0000)]
loadstore1: Do SPR reading in stage 2 rather than stage 3
This eliminates one leg of the output value multiplexer, and seems
to improve timing slightly on the A7-100.
Since SPR values are written in stage 3 and read in stage 2, an mfspr
immediately following an mtspr to the same SPR won't give the correct
value. To avoid this, we make mtspr to the load/store SPRs single
issue in decode1.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 24 Feb 2022 00:37:17 +0000 (11:37 +1100)]
Provide debug access to SPRs in loadstore1 and mmu
They are accessible as GSPR 0x3c - PID, 0x3d - PTCR, 0x3e - DSISR
and 0x3f - DAR.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 25 Feb 2022 05:46:34 +0000 (16:46 +1100)]
Restore debug access to SPRs
This provides access to the SPRs via the JTAG DMI interface. For now
they are still accessed as if they were GPR/FPRs using the same
numbering as before (GPRs at 0 - 0x1f, SPRs at 0x20 - 0x2d, FPRs at
0x40 - 0x5f).
For XER, debug reads now report the full value, not just the bits that
were previously stored in the register file. The "slow" SPR mux is
not used for debug reads.
Decode2 determines on each cycle whether a debug SPR access will
happen next cycle, based on whether there is a request and whether the
current instruction accesses the SPR RAM.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 19 Feb 2022 08:03:49 +0000 (19:03 +1100)]
Finish off taking SPRs out of register file
With this, the register file now contains 64 entries, for 32 GPRs and
32 FPRs, rather than the 128 it had previously. Several things get
simplified - decode1 no longer has to work out the ispr{1,2,o} values,
decode_input_reg_{a,b,c} no longer have the t = SPR case, etc.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 12 Jul 2022 01:20:17 +0000 (11:20 +1000)]
Move LR, CTR and TAR out of the register file
By putting CTR on the odd side and LR and TAR on the even side, we can
read and write CTR for bdnz-style instructions in parallel with
reading LR or TAR for indirect branches and writing LR for branches
with LK=1. Thus we don't need to double up any of these instructions,
giving a simplification in decode2.
We now have logic for printing LR and CTR at the end of a simulation
in execute1, in addition to the similar logic in register_file and
cr_file.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 11 Jul 2022 22:52:05 +0000 (08:52 +1000)]
Start removing SPRs from register file
This starts the process of removing SPRs from the register file by
moving SRR0/1, SPRG0-3, HSRR0/1 and HSPRG0/1 out of the register file
and putting them into execute1. They are stored in a pair of small
RAM arrays, referred to as "even" and "odd". The reason for having
two arrays is so that two values can be read and written in each
cycle. For example, SRR0 and SRR1 can be written in parallel by an
interrupt and read in parallel by the rfid instruction.
The addresses in the RAM which will be accessed are determined in the
decode2 stage. We have one write address for both sides, but two read
addresses, since in future we will want to be able to read CTR at the
same time as either LR or TAR.
We now have a connection from writeback to execute1 which carries the
partial SRR1 value for an interrupt. SRR0 comes from the execute
pipeline; we no longer need to carry instruction addresses along the
LSU and FPU pipelines. Since SRR0 and SRR1 can be written in the same
cycle now, we don't need the little state machine in writeback any
more.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 9 May 2022 09:18:42 +0000 (19:18 +1000)]
Use FPU for division instructions if we have an FPU
- Arrange for XER to be written for OE=1 forms
- Arrange for condition codes to be set for RC=1 forms
(including correct handling for 32-bit mode)
- Don't instantiate the divider if we have an FPU.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 7 May 2022 12:34:23 +0000 (22:34 +1000)]
FPU: Add logic for 32-bit integer division
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 7 May 2022 08:28:33 +0000 (18:28 +1000)]
FPU: Add integer division logic to FPU
This adds logic to the FPU to accomplish 64-bit integer divisions.
No instruction actually uses this yet.
The algorithm used is to obtain an estimate of the reciprocal of the
divisor using the lookup table and refine it by one to three
iterations of the Newton-Raphson algorithm (the number of iterations
depends on the number of significant bits in the dividend). Then the
reciprocal is multiplied by the dividend to get the quotient estimate.
The remainder is calculated as dividend - quotient * divisor. If the
remainder is greater than or equal to the divisor, the quotient is
incremented, or if a modulo operation is being done, the divisor is
subtracted from the remainder. The inverse estimate after refinement
is good enough that the quotient estimate is always equal to or one
less than the true quotient.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sun, 1 May 2022 23:39:26 +0000 (09:39 +1000)]
FPU: Convert internal R, A, B, and C registers to 8.56 format
This changes the representation of the R, A, B and C registers in the
FPU from 10.54 format (10 bits to the left of the binary point and 54
bits to the right) to 8.56 format, to match the representation used in
the P and Y registers and the multiplier operands. This eliminates
the need for shifting when R, A, B or C is an input to the multiplier
and will make it easier to implement integer division in the FPU.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 9 Jul 2022 08:29:48 +0000 (18:29 +1000)]
Track hazards explicitly for XER overflow bits
This provides a mechanism for tracking updates to the XER overflow
bits (SO, OV, OV32) and stalling instructions which need current
values of those bits (mfxer, integer compare instructions, integer
Rc=1 instructions, addex) or which writes carry bits (since all the
XER common bits are written together, if we are writing CA/CA32 we
need up-to-date values of SO/OV/OV32).
This will enable updates to SO/OV/OV32 to be done at other places
besides the ex1 stage.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 9 Jul 2022 03:17:18 +0000 (13:17 +1000)]
fetch1: Fix debug stop again
This fixes a bug which prevents the core from stopping properly. The
same bug was previously fixed in commit
e41cb01bca99 ("fetch1: Fix
debug stop", 2020-12-19) and reintroduced by commit
0fb207be6069
("fetch1: Implement a simple branch target cache", 2020-12-19).
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 9 Jul 2022 01:55:13 +0000 (11:55 +1000)]
control: Reimplement serialization using tags
This lets us get rid of r_int and its 'outstanding' counter. We now
test more directly for excess completions by checking that we don't
get duplicate completions for the same tag.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 8 Jul 2022 06:37:12 +0000 (16:37 +1000)]
decode1: Remove stash buffer
Now that the timing of the busy signal from decode2 doesn't depend on
register numbers or downstream instruction completion, we no longer
need the stash buffer on the output of decode1.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 8 Jul 2022 04:07:28 +0000 (14:07 +1000)]
decode2: Rework to make the stall_out signal come from a register
At present the busy/stall signal going to decode1 depends on whether
control thinks it can issue the current instruction, and that depends
on completion and bypass signals coming from execute1 and writeback.
To improve the timing of stall_out, this rearranges decode2 so that
stall_out is asserted when we have a valid instruction that couldn't
be issued in the previous cycle. This means that decode1 could give
us a new instruction when we haven't issued the previous instruction.
This in turn means that we can only use d_in in the first cycle of
processing an instruction. After the first cycle, we get register
addresses etc. from dc2 rather than d_in.
Then, to avoid the need to read register operands from register_file
in each cycle until the instruction issues, we bring the bypass path
for data being written to the register file into decode2 explicitly
rather than having it in register_file.
A new process called decode2_addrs does the process of calling
decode_input_reg_* and decode_output_reg and sets up the register file
addresses. This was split out (and decode_input_reg_* reworked) to
try to reduce the number of passes through the decode2_1 process that
need to be done in simulation.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 4 Jun 2022 07:37:48 +0000 (17:37 +1000)]
Remove support for lq, stq, lqarx and stqcx.
They are optional in SFFS (scalar fixed-point and floating-point
subset), are not needed for running Linux, and add complexity, so
remove them.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 4 Jul 2022 08:23:03 +0000 (18:23 +1000)]
decode2: Rename 'r' to 'dc2'
Also get rid of a couple of unused variables.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 2 Jul 2022 12:23:35 +0000 (22:23 +1000)]
decode1: Reduce number of single-issue instructions
This reduces the set of instructions marked as single-issue to just
attn and mtspr to "slow" SPRs (those that are not stored in the
register file).
The instructions that were previously single-issue are: isync, dcbf,
dcbst, dcbt, dcbtst, eieio, icbi, mfmsr, mtmsr, mtmsrd, mfspr to slow
SPRS, sync, tlbsync and wait. The synchronization instructions are
mostly no-ops anyway due to the in-order nature of the core, and the
cache-management instructions are unimplemented (except for icbi).
The MSR ops don't need to be single-issue due to the in-order core and
the fact that MSR updates are effective on the following instruction.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 2 Jul 2022 04:17:18 +0000 (14:17 +1000)]
FPU: Add stage-2 stall ability to FPU
This makes the FPU able to stall other units at execute stage 2 and be
stalled by other units (specifically the LSU).
This means that the completion and writeback for an instruction can
now end up being deferred until the second cycle of a following
instruction, i.e. the cycle when the state machine has gone through
IDLE state into one of the DO_* states, which means we need to latch
the destination FPR number, CR mask, etc. from the previous
instruction so that we present the correct information to writeback.
The advantage of this is that we can get rid of the in_progress signal
from the LSU.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 28 Jun 2022 08:18:08 +0000 (18:18 +1000)]
Do CR0 setting for Rc=1 instructions in execute2 instead of writeback
This lets us forward the CR0 result to following instructions that
use CR, meaning they get to issue one cycle earlier.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 27 Jun 2022 08:53:04 +0000 (18:53 +1000)]
Allow integer instructions and load/store instructions to execute together
Execute1 and loadstore1 now send each other stall signals that
indicate that a valid instruction in stage 2 can't complete in this
cycle, and hence any valid instruction in stage 1 in the other unit
can't move to stage 2. With this in place, an ALU instruction can
move into stage 1 while a LSU instruction is in stage 2.
Since the FPU doesn't yet have a way to stall completion, we can't yet
start FPU instructions while any LSU or ALU instruction is in
progress.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 27 Jun 2022 22:40:42 +0000 (08:40 +1000)]
Add a bypass path from the execute2 stage
This enables some instructions to issue earlier and thus improves
performance, at the cost of some extra multiplexers in decode2.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 30 Jun 2022 10:33:33 +0000 (20:33 +1000)]
Add a second execute stage to the pipeline
This adds a second execute stage to the pipeline, in order to match up
the length of the pipeline through loadstore and dcache with the
length through execute1. This will ultimately enable us to get rid of
the 1-cycle bubble that we currently have when issuing ALU
instructions after one or more LSU instructions.
Most ALU instructions execute in the first stage, except for
count-zeroes and popcount instructions (which take two cycles and do
some of their work in the second stage) and mfspr/mtspr to "slow" SPRs
(TB, DEC, PVR, LOGA/LOGD, CFAR). Multiply and divide/mod instructions
take several cycles but the instruction stays in the first stage (ex1)
and ex1.busy is asserted until the operation is complete.
There is currently a bypass from the first stage but not the second
stage. Performance is down somewhat because of that and because this
doesn't yet eliminate the bubble between LSU and ALU instructions.
The forwarding of XER common bits has been changed somewhat because
now there is another pipeline stage between ex1 and the committed
state in cr_file. The simplest thing for now is to record the last
value written and use that, unless there has been a flush, in which
case the committed state (obtained via e_in.xerc) is used.
Note that this fixes what was previously a benign bug in control.vhdl,
where it was possible for control to forget an instructions dependency
on a value from a previous instruction (a GPR or the CR) if this
instruction writes the value and the instruction gets to the point
where it could issue but is blocked by the busy signal from execute1.
In that situation, control may incorrectly not indicate that a bypass
should be used. That didn't matter previously because, for ALU and
FPU instructions, there was only one previous instruction in flight
and once the current instruction could issue, the previous instruction
was completing and the correct value would be obtained from
register_file or cr_file. For loadstore instructions there could be
two being executed, but because there are no bypass paths, failing to
indicate use of a bypass path is fine.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 18 Jun 2022 07:29:43 +0000 (17:29 +1000)]
execute1: Rename 'r' to 'ex1'
Maybe this will give us slightly better names in critical path reports
and the like.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 18 Jun 2022 06:24:30 +0000 (16:24 +1000)]
execute1: Restructure to separate out execution of side effects
We now have a record that represents the actions taken in executing an
instruction, and a process that computes that for the incoming
instruction. We no longer have 'current' or 'r.cur_instr', instead
things like the destination register are put into r.e in the first
cycle of an instruction and not reinitialized in subsequent busy
cycles.
For mfspr and mtspr, we now decode "slow" SPR numbers (those SPRs that
are not stored in the register file) to a new "spr_selector" record
in decode1 (excluding those in the loadstore unit). With this, the
result for mfspr is determined in the data path.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Iago Caran Aquino [Tue, 19 Jul 2022 20:24:14 +0000 (17:24 -0300)]
tests/pmu: Add load/store completed, instruction count and cycle count tests
Signed-off-by: Iago Caran Aquino <iago.caran@gmail.com>
Paul Mackerras [Wed, 29 Jun 2022 10:02:36 +0000 (20:02 +1000)]
Move XER low bits out of register file
Besides the overflow and status carry bits, XER has 18 bits which need
to retain the value written by mtxer (in case software wants to
emulate the move-assist instructions (lswi, lswx, stswi, stswx).
Until now these bits (and others) have been stored in the GPR file as
a "fast" SPR, but this causes complications because XER is not really
a fast SPR.
Instead, we now store these 18 bits in the 'ctrl' signal, which exists
in execute1. This will enable us to simplify the data path in future,
and has the added bonus that with a little bit of plumbing, we can get
the full XER value printed when dumping registers at the end of a
simulation.
Therefore this changes scripts/run_test.sh to remove the greps which
exclude XER from the comparison of actual and expected register
results.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 11 Jun 2022 09:20:57 +0000 (19:20 +1000)]
Simplify flow control in the dcache and loadstore units
Simplify the flow control by stalling the whole upstream pipeline when
a stage can't proceed, instead of trying to let each stage progress
independently when it can.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 16 Jun 2022 23:46:57 +0000 (09:46 +1000)]
Merge pull request #353 from tianrui-wei/master
fix: fix icache_tb not finishing correctly
Michael Neuling [Thu, 16 Jun 2022 23:13:49 +0000 (09:13 +1000)]
Merge pull request #373 from antonblanchard/icache-insn-u-state
icache: Don't output X on i_out.insn
Michael Neuling [Thu, 16 Jun 2022 06:47:33 +0000 (16:47 +1000)]
Merge pull request #376 from antonblanchard/loadstore-init
loadstore1: reduce U state being output
Michael Neuling [Thu, 16 Jun 2022 06:45:41 +0000 (16:45 +1000)]
Merge pull request #374 from antonblanchard/icache-unused-sig
core: Remove unused icache_inv signal
Michael Neuling [Thu, 16 Jun 2022 04:38:12 +0000 (14:38 +1000)]
Merge pull request #364 from shenki/readme-updates
Readme updates
Michael Neuling [Thu, 16 Jun 2022 04:36:50 +0000 (14:36 +1000)]
Merge pull request #372 from antonblanchard/dcache-unused-sig
dcache: remove unused do_write signal
Michael Neuling [Thu, 16 Jun 2022 04:35:10 +0000 (14:35 +1000)]
Merge pull request #371 from antonblanchard/unused-sig
execute1: sub_mux_sel and result_mux_sel are unused
Michael Neuling [Thu, 16 Jun 2022 04:33:45 +0000 (14:33 +1000)]
Merge pull request #370 from antonblanchard/divider-init
divider: Fix d_out.overflow U state issue
Paul Mackerras [Wed, 15 Jun 2022 01:02:58 +0000 (11:02 +1000)]
Merge pull request #368 from antonblanchard/icache-pmu-events
icache: Hook up PMU events
Anton Blanchard [Tue, 14 Jun 2022 08:10:37 +0000 (18:10 +1000)]
Merge pull request #377 from antonblanchard/fpu-init
fpu: Reduce uninitialised signals
Anton Blanchard [Tue, 14 Jun 2022 05:14:19 +0000 (15:14 +1000)]
fpu: Reduce uninitialised signals
Reduce uninitialised signals coming out of the FPU.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling [Tue, 14 Jun 2022 03:09:57 +0000 (13:09 +1000)]
Merge pull request #366 from antonblanchard/hello-world-bss
Zero BSS in hello world test
Anton Blanchard [Sun, 12 Jun 2022 21:15:55 +0000 (07:15 +1000)]
Merge pull request #375 from antonblanchard/core_debug-init
core_debug: Initialise gspr_index
Anton Blanchard [Sun, 12 Jun 2022 12:15:11 +0000 (22:15 +1000)]
loadstore1: reduce U state being output
While these signals should only be read when valid is true, they
are only a small number of bits and we want to reduce the amount of
U/X state bouncing around the chip.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 12 Jun 2022 11:49:13 +0000 (21:49 +1000)]
core_debug: Initialise gspr_index
Another case of U state being driven out of a module.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 12 Jun 2022 11:04:16 +0000 (21:04 +1000)]
core: Remove unused icache_inv signal
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 12 Jun 2022 01:42:32 +0000 (11:42 +1000)]
icache: Don't output X on i_out.insn
decode1 has a lot of logic that uses i_out.insn without first looking at
i_iout.valid. Play it safe and never output X state.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 12 Jun 2022 01:39:31 +0000 (11:39 +1000)]
dcache: remove unused do_write signal
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 12 Jun 2022 00:49:26 +0000 (10:49 +1000)]
execute1: sub_mux_sel and result_mux_sel are unused
Remove them.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 12 Jun 2022 00:34:20 +0000 (10:34 +1000)]
divider: Fix d_out.overflow U state issue
While we should only look at this when d_out.valid = 1, we may as remove
some U state across interfaces.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 12 Jun 2022 00:24:54 +0000 (10:24 +1000)]
Merge pull request #369 from antonblanchard/loadstore-pmu-init
loadstore1: Initialise PMU events
Anton Blanchard [Sat, 11 Jun 2022 23:29:46 +0000 (09:29 +1000)]
loadstore1: Initialise PMU events
The loadstore1 PMU events are U state until a load and a store completes.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 11 Jun 2022 23:32:59 +0000 (09:32 +1000)]
Merge pull request #367 from antonblanchard/fpu-typo
fpu: Fix capitalisation of Execute1ToFPUType
Anton Blanchard [Sat, 11 Jun 2022 23:21:56 +0000 (09:21 +1000)]
icache: Hook up PMU events
We weren't connecting the icache PMU events up.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 9 Jun 2022 22:10:27 +0000 (08:10 +1000)]
fpu: Fix capitalisation of Execute1ToFPUType
While this is not an issue in VHDL, I noticed this when running
a script over the source and we may as well fix it.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 8 Jun 2022 05:20:07 +0000 (15:20 +1000)]
Zero BSS in hello world test
While trying to reduce U/X state issues, I notice that our BSS is not
being initialised in the hello world test.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 8 Jun 2022 04:54:48 +0000 (14:54 +1000)]
Merge pull request #365 from antonblanchard/less-fpga-init
Remove some FPGA style signal inits
Anton Blanchard [Tue, 7 Jun 2022 10:01:14 +0000 (20:01 +1000)]
Remove some FPGA style signal inits
These don't work on the ASIC flow, so remove them and initialise
them explicitly where required.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 7 Jun 2022 07:38:24 +0000 (17:38 +1000)]
Remove some FPGA style signal inits
These don't work on the ASIC flow, so remove them and initialise
them explicitly where required.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Joel Stanley [Tue, 7 Jun 2022 03:20:03 +0000 (12:50 +0930)]
README: Add Linux on Microwatt instructions
These instructions are similar to those at
https://ozlabs.org/~joel/microwatt/README
except they describe how to build the artifacts from scratch instead of
downloading them.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Tue, 7 Jun 2022 03:18:42 +0000 (12:48 +0930)]
README: Add uart to fusesoc instructions
The SoC defaults to using the uart16550 so provide instructions on how
to fetch that library when seetting up fusesoc.
Also remove the text about a working directory; fusesoc doesn't need
one.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Michael Neuling [Tue, 22 Mar 2022 00:55:54 +0000 (11:55 +1100)]
Merge pull request #361 from antonblanchard/alt-reset-address
Allow ALT_RESET_ADDRESS to be overridden
Anton Blanchard [Mon, 21 Mar 2022 22:35:17 +0000 (09:35 +1100)]
Allow ALT_RESET_ADDRESS to be overridden
This allows us to boot from flash for example.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling [Fri, 18 Mar 2022 07:28:34 +0000 (18:28 +1100)]
Merge pull request #360 from antonblanchard/log2ceil-issue
wishbone_bram_wrapper ram_addr_bits is 1 bit off
Anton Blanchard [Thu, 17 Mar 2022 07:03:29 +0000 (18:03 +1100)]
wishbone_bram_wrapper ram_addr_bits is 1 bit off
log2ceil() returns the number of bits required to store a value, so we
need to pass in memory_size-1, not memory_size.
Every other user of log2ceil() gets this right.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling [Tue, 15 Mar 2022 23:49:47 +0000 (10:49 +1100)]
Merge pull request #358 from antonblanchard/unused-sig
Remove unused sequential signal from Fetch1ToIcacheType
Michael Neuling [Tue, 15 Mar 2022 23:49:29 +0000 (10:49 +1100)]
Merge pull request #356 from antonblanchard/fpu-constant
fpu: Make inverse_table a constant
Michael Neuling [Tue, 15 Mar 2022 23:48:59 +0000 (10:48 +1100)]
Merge pull request #357 from antonblanchard/xics-warning
xics: Fix warning when comparing two std_ulogic_vectors
Anton Blanchard [Tue, 15 Mar 2022 07:27:48 +0000 (18:27 +1100)]
Remove unused sequential signal from Fetch1ToIcacheType
GHDL synthesis is flagging a warning about this.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 15 Mar 2022 05:04:18 +0000 (16:04 +1100)]
xics: Fix warning when comparing two std_ulogic_vectors
Use unsigned() to make it clear what we are doing.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>