bugzilla-daemon [Tue, 17 Mar 2020 00:30:54 +0000 (00:30 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 17 Mar 2020 00:24:12 +0000 (00:24 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 17 Mar 2020 00:19:34 +0000 (00:19 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Tue, 17 Mar 2020 00:05:08 +0000 (00:05 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 23:42:08 +0000 (23:42 +0000)]
Re: [libre-riscv-dev] next tasks
bugzilla-daemon [Mon, 16 Mar 2020 23:38:13 +0000 (23:38 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Mon, 16 Mar 2020 23:25:26 +0000 (23:25 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
Immanuel, Yehowshua U [Mon, 16 Mar 2020 23:16:26 +0000 (23:16 +0000)]
Re: [libre-riscv-dev] next tasks
Immanuel, Yehowshua U [Mon, 16 Mar 2020 23:12:28 +0000 (23:12 +0000)]
Re: [libre-riscv-dev] next tasks
bugzilla-daemon [Mon, 16 Mar 2020 23:06:38 +0000 (23:06 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 22:53:06 +0000 (22:53 +0000)]
Re: [libre-riscv-dev] next tasks
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 22:53:05 +0000 (22:53 +0000)]
Re: [libre-riscv-dev] next tasks
bugzilla-daemon [Mon, 16 Mar 2020 22:01:50 +0000 (22:01 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
Jacob Lifshay [Mon, 16 Mar 2020 18:51:18 +0000 (11:51 -0700)]
Re: [libre-riscv-dev] next tasks
Immanuel, Yehowshua U [Mon, 16 Mar 2020 18:30:15 +0000 (18:30 +0000)]
Re: [libre-riscv-dev] next tasks
bugzilla-daemon [Mon, 16 Mar 2020 17:25:53 +0000 (17:25 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 16:24:27 +0000 (16:24 +0000)]
Re: [libre-riscv-dev] [OT] Minecraft garbage collection
Jacob Lifshay [Mon, 16 Mar 2020 16:22:33 +0000 (09:22 -0700)]
Re: [libre-riscv-dev] [OT] Minecraft garbage collection
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 13:22:42 +0000 (13:22 +0000)]
Re: [libre-riscv-dev] [OT] Minecraft garbage collection
Staf Verhaegen [Mon, 16 Mar 2020 11:00:34 +0000 (12:00 +0100)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 10:34:05 +0000 (10:34 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
bugzilla-daemon [Mon, 16 Mar 2020 09:59:04 +0000 (09:59 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
Lauri Kasanen [Mon, 16 Mar 2020 09:27:00 +0000 (11:27 +0200)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 09:10:08 +0000 (09:10 +0000)]
Re: [libre-riscv-dev] video about open source & endurance
Staf Verhaegen [Mon, 16 Mar 2020 08:53:38 +0000 (09:53 +0100)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Jacob Lifshay [Mon, 16 Mar 2020 07:28:11 +0000 (00:28 -0700)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Lauri Kasanen [Mon, 16 Mar 2020 07:14:20 +0000 (09:14 +0200)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Jacob Lifshay [Mon, 16 Mar 2020 01:30:34 +0000 (18:30 -0700)]
Re: [libre-riscv-dev] video about open source & endurance
Immanuel, Yehowshua U [Mon, 16 Mar 2020 01:29:00 +0000 (01:29 +0000)]
Re: [libre-riscv-dev] video about open source & endurance
Immanuel, Yehowshua U [Mon, 16 Mar 2020 01:24:38 +0000 (01:24 +0000)]
Re: [libre-riscv-dev] video about open source & endurance
Immanuel, Yehowshua U [Mon, 16 Mar 2020 00:25:05 +0000 (00:25 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Jacob Lifshay [Sun, 15 Mar 2020 23:05:52 +0000 (16:05 -0700)]
[libre-riscv-dev] video about open source & endurance
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 22:32:30 +0000 (22:32 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
bugzilla-daemon [Sun, 15 Mar 2020 22:30:17 +0000 (22:30 +0000)]
[libre-riscv-dev] [Bug 259] can't set "parent bug budget"
bugzilla-daemon [Sun, 15 Mar 2020 22:27:26 +0000 (22:27 +0000)]
[libre-riscv-dev] [Bug 259] can't set "parent bug budget"
Adam Van Ymeren [Sun, 15 Mar 2020 22:23:46 +0000 (18:23 -0400)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
bugzilla-daemon [Sun, 15 Mar 2020 22:21:22 +0000 (22:21 +0000)]
[libre-riscv-dev] [Bug 259] New: can't set "parent bug budget"
Jacob Lifshay [Sun, 15 Mar 2020 22:10:38 +0000 (15:10 -0700)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Staf Verhaegen [Sun, 15 Mar 2020 22:04:32 +0000 (23:04 +0100)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
bugzilla-daemon [Sun, 15 Mar 2020 21:19:49 +0000 (21:19 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 20:05:45 +0000 (20:05 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 20:00:02 +0000 (20:00 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 19:57:52 +0000 (19:57 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
bugzilla-daemon [Sun, 15 Mar 2020 19:57:17 +0000 (19:57 +0000)]
[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 19:56:30 +0000 (19:56 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 19:52:44 +0000 (19:52 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 19:51:59 +0000 (19:51 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Jacob Lifshay [Sun, 15 Mar 2020 19:43:45 +0000 (12:43 -0700)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 19:37:07 +0000 (19:37 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 19:32:46 +0000 (19:32 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 19:25:57 +0000 (19:25 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 19:24:13 +0000 (19:24 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 19:23:53 +0000 (19:23 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 19:20:03 +0000 (19:20 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 19:16:56 +0000 (19:16 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 19:11:01 +0000 (19:11 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 19:07:09 +0000 (19:07 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
bugzilla-daemon [Sun, 15 Mar 2020 19:00:05 +0000 (19:00 +0000)]
[libre-riscv-dev] [Bug 242] OpenPOWER simulation unit tests are needed
Immanuel, Yehowshua U [Sun, 15 Mar 2020 18:26:45 +0000 (18:26 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 18:21:47 +0000 (18:21 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 18:19:54 +0000 (18:19 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
bugzilla-daemon [Sun, 15 Mar 2020 18:02:13 +0000 (18:02 +0000)]
[libre-riscv-dev] [Bug 258] New: Finish implementing support for Power in simple-soft-float
bugzilla-daemon [Sun, 15 Mar 2020 17:34:09 +0000 (17:34 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
Hendrik Boom [Sun, 15 Mar 2020 16:57:23 +0000 (12:57 -0400)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
bugzilla-daemon [Sun, 15 Mar 2020 16:17:04 +0000 (16:17 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 12:11:43 +0000 (12:11 +0000)]
Re: [libre-riscv-dev] [OT] Minecraft garbage collection
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 12:09:57 +0000 (12:09 +0000)]
[libre-riscv-dev] pearpc simulator running
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 11:22:12 +0000 (11:22 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 11:20:16 +0000 (11:20 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Jacob Lifshay [Sun, 15 Mar 2020 07:59:31 +0000 (00:59 -0700)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 07:18:54 +0000 (07:18 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Jacob Lifshay [Sun, 15 Mar 2020 06:41:37 +0000 (23:41 -0700)]
Re: [libre-riscv-dev] [OT] Minecraft garbage collection
Jacob Lifshay [Sun, 15 Mar 2020 06:13:23 +0000 (23:13 -0700)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Hendrik Boom [Sun, 15 Mar 2020 05:47:56 +0000 (01:47 -0400)]
[libre-riscv-dev] [OT] Minecraft garbage collection
Jacob Lifshay [Sun, 15 Mar 2020 05:42:55 +0000 (22:42 -0700)]
Re: [libre-riscv-dev] benefits of rust
Hendrik Boom [Sun, 15 Mar 2020 05:18:21 +0000 (01:18 -0400)]
Re: [libre-riscv-dev] benefits of rust
Hendrik Boom [Sun, 15 Mar 2020 05:10:18 +0000 (01:10 -0400)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 04:00:30 +0000 (04:00 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Jacob Lifshay [Sun, 15 Mar 2020 03:17:07 +0000 (20:17 -0700)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Jacob Lifshay [Sun, 15 Mar 2020 02:47:45 +0000 (19:47 -0700)]
[libre-riscv-dev] benefits of rust
whygee [Sat, 14 Mar 2020 18:49:41 +0000 (19:49 +0100)]
Re: [libre-riscv-dev] next tasks
Luke Kenneth Casson Leighton [Sat, 14 Mar 2020 18:28:29 +0000 (18:28 +0000)]
Re: [libre-riscv-dev] next tasks
whygee [Sat, 14 Mar 2020 18:23:08 +0000 (19:23 +0100)]
Re: [libre-riscv-dev] next tasks
Hendrik Boom [Sat, 14 Mar 2020 18:13:51 +0000 (14:13 -0400)]
Re: [libre-riscv-dev] next tasks
bugzilla-daemon [Sat, 14 Mar 2020 14:18:15 +0000 (14:18 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon [Sat, 14 Mar 2020 14:17:34 +0000 (14:17 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon [Sat, 14 Mar 2020 10:31:57 +0000 (10:31 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon [Sat, 14 Mar 2020 10:30:26 +0000 (10:30 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
whygee [Fri, 13 Mar 2020 21:48:00 +0000 (22:48 +0100)]
Re: [libre-riscv-dev] Chips Alliance started
Cole Poirier [Fri, 13 Mar 2020 21:44:43 +0000 (14:44 -0700)]
Re: [libre-riscv-dev] Chips Alliance started
whygee [Fri, 13 Mar 2020 21:28:54 +0000 (22:28 +0100)]
Re: [libre-riscv-dev] Chips Alliance started
Luke Kenneth Casson Leighton [Fri, 13 Mar 2020 20:27:13 +0000 (20:27 +0000)]
[libre-riscv-dev] Chips Alliance started
bugzilla-daemon [Fri, 13 Mar 2020 20:16:34 +0000 (20:16 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Jacob Lifshay [Fri, 13 Mar 2020 20:10:37 +0000 (13:10 -0700)]
Re: [libre-riscv-dev] changing bugzilla product name
Luke Kenneth Casson Leighton [Fri, 13 Mar 2020 19:56:34 +0000 (19:56 +0000)]
Re: [libre-riscv-dev] changing bugzilla product name
Jacob Lifshay [Fri, 13 Mar 2020 18:47:33 +0000 (11:47 -0700)]
[libre-riscv-dev] changing bugzilla product name
bugzilla-daemon [Fri, 13 Mar 2020 18:40:38 +0000 (18:40 +0000)]
[libre-riscv-dev] [Bug 257] New: Implement demo Load/Store queueing algorithm
bugzilla-daemon [Fri, 13 Mar 2020 18:37:01 +0000 (18:37 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Fri, 13 Mar 2020 18:29:13 +0000 (18:29 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon [Fri, 13 Mar 2020 18:29:13 +0000 (18:29 +0000)]
[libre-riscv-dev] [Bug 256] Enhancements to an OpenPOWER ISA-level Simulator are needed
projects / libre-riscv-dev.git / log