python: Generalize the Port.splice function.

Now that the MASTER and SLAVE roles aren't special, the splice function
needs to be able to handle arbitrarily role-d peers.

Change-Id: I22a28b7cdcb93f7f370730b7e38b0e6d3500a6a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18170
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Generalize the dot_writer to handle non Master/Slave roles.

Change-Id: I6d93c28e754c0cacacdd5e8885c45bc861135e94
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18169
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Make Port roles a more generic concept.

A recent change got rid of the strict Master => Slave port relationship
which used to be checked in python and instead left the checking up to
C++. One major downside to this approach is that it was no longer
obvious in the configuration what was supposed to be connected to what,
and it still left the arbitrary and misleading MasterPort and SlavePort
types in the Ethernet devices which could now connect with each other
symmetrically but couldn't actually connect to an arbitrary
MasterPort/SlavePort.

This change exposes the base Port and VectorPort types, and makes them
accept a "role" parameter in __init__ which used to be set directly by
their subclasses. This role can be any string, and will be used later
to check for compatiblity and to give a hint as to what can be
connected to what in the SimObject definitions.

To make the checks work with arbitrary compatible pairs, the base Port
type now has a class method called compat() which accepts a pair of
roles which will become mutually compatible, ie any port with the first
role will be allowed to connect to any port with the second role, and
vice versa. To be self compatible, the same role should be passed in
for both parameters.

To maintain compatibility, the MasterPort and SlavePort types are
retained, but now they're nothing special and could have been set up
in any arbitrary SimObject .py file. The same is true for
MasterVectorPort and SlaveVectorPort.

Also, since we can no longer assume that all edges in the dot graph of
the config should start with a port with the MASTER role and end with
a port with the SLAVE role, Ports now track an is_source property which
says whether the arrow head should be surpressed at that end of the
edge representing the connection.

Change-Id: Ifcc6faab05e437ad87cd21f0ba613b09cf21c321
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18168
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

python: fix tracing after Python 3 refactor

gem5.opt --debug-flags ExecAll

was failing with:

ImportError: No module named defines

on Python 2.

Change-Id: I06959d6e0ccb7c661c7c749af3392632dac779f3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18108
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: Enhance clone for X86KvmCPU

This changeset enables clone to work with X86KvmCPU model, which
will allow running multi-threaded applications at near hardware
speeds. Even though the application is multi-threaded, the KvmCPU
model uses one event queue, therefore, only one hardware thread
will be used, through KVM, to simulate multiple application threads.

Change-Id: I2b2a7b1edb1c56eeb9c4fa0553cd236029cd53f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18268
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix fix of replacement count

Commit 7976b561de61b7523ca9a860154ad7ba701d12a7 tried fixing
replacement update when a single location can be associated to
multiple blocks.

Although the comment of the correct action was added, the proper
validation check was forgotten. This change adds that check and
moves doing the eviction to when there is a valid block.

Change-Id: I31d8bb914ccfd1849e9d97464d70a58a62f59533
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18210
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Eliminate the ProxyThreadContext class.

Replace it with direct inheritance from the ThreadContext class in the
SimpleThread class which was the only place it was used.

Also take the opportunity to use some specialized types instead of
ints, etc., add some consts, and fix some style issues.

Change-Id: I5d2cfa87b20dc43615e33e6755c9d016564e9c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18048
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Use param to get number of processors

Although the parameter np is the same as options.num_cpus. But we should
get the number of processors from the parameters of the function.

Change-Id: I3eb02d7c75ab35410b773b06001d1b145cdccd49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18248
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix increasing replacement count

Replacements should be increased when there is any evicted
block, which does not necessarily have to be the victim.

For example, assume a superblock contains 4 blocks, and both
A and C are stored compressed (belonging to SB_1). Then F,
from SB2 needs to make room by replacing SB1. If F map to
location 2, the number of replacements should be increased,
even though 2 had no valid blocks:

 Tag      Data          Tag     Data
|SB_1|--|A|X|C|X|  --> |SB_2| |X|F|X|X|
         1 2 3 4               1 2 3 4

Change-Id: I7b3735d28a35faa8d8fa613a1555bb258da65859
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18208
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Remove blk_addr from Queue::trySatisfyFunctional

The blk_addr is pkt->getBlockAddr(), and therefore can be
acquired internally, when needed, as long as the pkt is
provided.

Change-Id: I2780445d2a0cb9e27257961efc4f438cc19550e5
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17537
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add match functions to QueueEntry

Having the caller decide the matching logic is error-prone, and
frequently ends up with the secure bit being forgotten. This
change adds matching functions to the QueueEntry to avoid this
problem.

As a side effect the signature of findPending has been changed.

Change-Id: I6e494a821c1e6e841ab103ec69632c0e1b269a08
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17530
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Add packet matching functions

Add both block and non-block-aligned packet matching functions,
so that both address and secure bits are checked when checking
whether a packet matches a request.

Change-Id: Id0069befb925d112e06f250741cb47d9dfa249cc
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17533
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move Target to QueueEntry

WriteQueueEntry's target has 100% functionality overlap with MSHR's,
therefore make it base to MSHR::Target.

Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Assert Entry inherits from QueueEntry in Queue

Queue has several assumptions regarding its template parameter,
so make sure they are fulfilled by forcing Entry to be derived
from QueueEntry.

Change-Id: I0203a62aec00c04ac89e9674d86a44a07f9f13ab
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17529
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Make DRAMCtrl::decodeAddr const

DRAMCtrl's decodeAddr does not need to modify the packet it
receives, nor should it modify the contents of the class,
and therefore both the packet and the function are made const.

Change-Id: I577f48d9a43611ba54878a9a793cb7b4fbb326f4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17540
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Allow packet to provide its own addr range

Add a getter to Packet to allow it to provide its own addr
range.

Change-Id: I2128ea3b71906502d10d9376b050a62407defd23
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17536
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: missing override specifier

Change-Id: Ied4817bcda317826303a1bb688b41823b18b489b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18128
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Teach SimpleMem to return a MemBackdoor when appropriate.

If the back door SimpleMem inherits from AbstractMem has a pointer and
is hence valid, SimpleMem will return that pointer when asked.

Change-Id: I734daba48e4ae5b4ad8ac9a108e7b12b5e82803f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17669
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem: Maintain a back door into the AbstractMem's backing store.

The backing store pointer is added to the back door when it's set,
assuming that the range isn't interleaved. If it is interleaved, then
there isn't a way to get a flat pointer to the backing store.

Depending on how the backing store is set up, it may be possible to
return a larger backdoor which applies to all interleaved memories at
the same time and to avoid problems with interleaving. I'm leaving this
as a todo.

Change-Id: I0e531c22835ec10954ab39f761b3d87666b59220
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17668
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

tests: Add tests for learning_gem5 configs

Change-Id: Ia9cbb77115c741051c871526517bb7d8124a8051
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17873
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests: Add protocol as an option to SconsFixture

Change-Id: I16e9a6169e7ad50601e460e221d6a05db1208783
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17872
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

tests: add riscv to cpu tests

Change-Id: Id8e767afbb74f79b980d8160eefc13e7f529f1c3
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16889
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix RRPV for RRIP

The RRPV values for RRIP and NRU replacment policies.
Long re-rereference interval was used instead of
distant re-rereference interval and vice-versa.
The btp value permit to choose beetwen distant and
long insertion ratio. A btp value of 0 force the
policy to always insert at a distant re-reference
interval and a btp value of 100 force the policy to
always insert at a long (intermediate) re-rereference
interval.

Change-Id: I516098f73942b769dcc31fe0edfe07c3e9c3effd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17851
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Enable PMSELR_EL0 read in PMU

Change-Id: Ic1ec1d03464a7ce42295cee8a9f4ebcd3e90def1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17948
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Plumb backdoor requests through the xbar classes.

Change-Id: Ic8f49339ab95c31d2f00edfdf23a46f1271ec3aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17593
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Teach the TLM bridges how to use gem5's new backdoor mechanism.

This change teaches the TLM bridges to translate between TLM's DMI
mechanism and gem5's backdoor mechanism.

Change-Id: I942a6cce4fb87f10e8173f4ee49b6c7b0ffa7e4a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17591
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Add sendAtomicBackdoor/recvAtomicBackdoor port methods.

These both perform atomic accesses like their non-backdoor equivalents,
and also request a backdoor corresponding to the access.

The default implementation for recvAtomicBackdoor prints a warning
(once per port instance), calls recvAtomic to do the actual access,
and leaves the backdoor pointer as nullptr. That way if an object
doesn't know how to handle or transfer requests for a back door, it
automatically replies in a safe way that ignores the back door request.

Change-Id: Ia9fbbe9996eb4b71ea62214d203aa039a05f1618
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17590
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Fix MSHR handling of cache clean requests

Previously satisfied clean requests would not snoop in-service
MSHRs. This is a problem when a clean request is also invalidating, in
which case we have to post-invalidate or post-downgrade outstanding
requests. This changes fixes this bug.

Change-Id: I31e42aa94dd3637b2818e00fbaae68c810145eaf
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17728
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

cpu: O3 switchFreeList checking VecElems instead of FloatRegs

Vector elements should be checked instead of floats since those are the
ones mapped to the vector registers.

Change-Id: I36088ab90e63720d846fcf5b43360da105b6c736
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

learning_gem5,configs: Update ruby_test

Use SimpleMemory instead of DDR3 so we can use the timing results in
tests. By using SimpleMemory, even if the DRAM timing changes the timing
of this test won't change. I expect the timing of SimpleMemory to never
change.

Change-Id: I4c75981d7b8bfc4dcca59e628e89f5a6ea4c0e36
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17871
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

learning_gem5: Fix vector port panic in SimpleCache

Change-Id: I0f3b71fdbed77690c533d9d14e774ab2cc08c053
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17870
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

configs: Fix import path error in learning_gem5 part3

Change-Id: I2c5cd22bded998bae8e7aa77e42e1b042ce1c5f5
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17869
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

configs: Add full path for learning_gem5 binaries

Change-Id: Ie48429d65e322136109a223ed404937989aae494
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17868
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

configs: Removed redudant exec-style import

garnet_synth_traffic.py imports common.Options on line 40, so exec'ing
the Options.py file again seems redundant.

It also runs Options.py as a script rather than a module, which throws
ValueError: Attempted relative import in non-package due to the recent
change to python3 imports.

Change-Id: Id729a8dfa776af0d14312e765168aff6900eb727
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17888
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Add a MemBackdoor type to track memory backdoors.

These are similar to the structures TLM's DMI mechanism uses. Instead
of having an invalidation broadcast which propogates backwards up the
port hierarchy, this mechanism tracks a set of callbacks which are
triggered when a back door is invalidated to let other holders clean
up their bookkeeping.

Change-Id: If24489258dcaee14d7b6e5b996dfb1c2636f26ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17589
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Correctly account for executed instructions in simple cpus

Change-Id: I53f34b2d9db6e4d2e03dde42a970764bb2a5e701
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17730
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: ambiguous use of abs function

std::abs doesn't accept unsigned long long, generating the error:

error: call to 'abs' is ambiguous

Use instead a compare-and-subtract idiom.

Also, Changed return type of distanceFromTrigger from unsigned int to Addr to
prevent overflow problems.

Change-Id: Ia7752c1c7a838f98e8c7ed6ade9f586f31bbcf7d
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17788
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Reverse order of write/read mem queue check

For atomic RMW instructions that go directly to memory, we want to put
them on the write queue instead of the read queue. Swap the if/else
condition to accomplish this.

Note: This is ignoring the read latency of the RMW, but these
instructions should usually be handled in caches anyway.

Change-Id: I62dbfff3a16ac470f1ebdb489abe878962b20bb6
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17828
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

tests: Add Jenkins presubmit and continuous test scripts

Note that continuous currently isn't used.

Change-Id: Ifcff88c8c4c75a9f630b97eaca22edd1681529c3
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17456
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-cache: AMPM Prefetcher fails when restoring from a checkpoint

The preriodic event triggers an assertion due to an incorrect tick value to
schedule when restoring from a checkpoint.

Change-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17732
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

misc: Removed inconsistency in O3* debug msgs

Added consistency in the DEBUG message form, to allow a better parsing.
Fixed sn/tid type parameter.
Removed some annoying newlines

Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17248
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-mips: added missing override specifier (o3)

Change-Id: Ic538825a2964fd62def672b933a83067a15bd12a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix PIF prefetcher compilation error with NULL ISA

Referencing BaseCPU is causing a compilation error when using the NULL ISA.
This patch changes the reference to a SimObject, which fixes the problem.

Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17731
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: ISB prefetcher was triggering an assertion

An assertion ignored the case when an entry of the SP table had been invalidated.

Change-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17734
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix panic in Indirect Memory prefetcher

Memory requests with a size non-power-of-two and less than 8 values were causing
a panic, but there these should be allowed and ignored by the prefetcher.

Change-Id: I86baa60058cc8a7f232d6ba5748d4c24a463c840
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17733
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt

Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Proactive Instruction Fetch Implementation

Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December).
Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM
International Symposium on Microarchitecture (pp. 152-162). ACM.

Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16968
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

dev-arm: Correct cast of template parameter

Clang with -Wconstant-conversion is _very_ restrictive on casting.
The shift operator results in an incorrect promotion.

This patch add a compile-time static cast that remove the error
when clang is used.

Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17308
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Templatize the gem5/TLM bridge SimObjects.

The C++ side is templated, and there are python versions for each
(currently two) width of bridge supported.

Change-Id: I4baa9f22d4c87629d45e9e1292eb66c65d25a655
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17234
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Delete extra code from src/systemc/tlm_bridge.

Much of the code in src/systemc/tlm_bridge has been absorbed into the
TLM/gem5 bridge SimObjects and is no longer needed and redundant with
the original version in util/.

Change-Id: I0fa7af67649987cf9f6fc5cd4783002dde2242ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17233
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Create unified gem5/TLM bridge SimObjects.

These objects expose a standard TLM initiator or target socket with
width 64, and a gem5 slave or master port. What goes in one type of
port comes out the other with the appropriate conversion applied.

Change-Id: I65e07f746d46d3db0197968b78fffc5ddaede9bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17232
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

tlm: Initial import of tlm/gem5 bridge code.

This is a slightly mangled version of the existing bridge code in
util/tlm/src/. The changes fix some small style issues, change to gem5
specific include paths, and removes the Gem5SimControl code. That code
coordinates gem5 with the external systemc kernel, and in this usage
there's no external kernel.

The code imported here compiles, but it isn't yet expected to work.

Change-Id: I9c593a52e2554534720d21cd31a03e543ad897ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17231
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Provide a utility Port TLM socket wrapper class.

This class should make it easy to attach TLM sockets into the gem5
python Port config mechanism.

Change-Id: I3548c654d56bfc852f3fc98fe6433163b14f7fe3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17230
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Added a probe to notify the address of retired instructions

A probe is added to notify the address of each retired instruction.

Change-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17632
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Remove extra cache header from AMAP

The cache header was being included in the AMAP, although not
used, which resulted in slightly longer compilation time.

Change-Id: I3654bc719c6b5f558af116addae159301602a3cf
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17711
Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Fix use of bitwise operators on booleans

Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17288
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix index generation for VecElem operands

Current operand generation is not providing VecElems with the right
vector index and element index.
The bug was covered when registers were 128 bit wide, but with SVE we
have augmented the vector register size and the bug has been exposed.

E.g. With dest = 2,

FpDestP2 = (vec_index = 0, elem_index = 4)

whereas it should be

FpDestP2 = (vec_index = 1, elem_index = 0)

Change-Id: Iad02fb477afd0d3dd3d437bf2ca4338fbd142107
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17710

dev-arm: Rename GIC maintenance interrupt from ppint to maint_int

ppint is a generic name which only reflects Arm recommendation of
assigning the maintanance interrupt to a PPI (numbered 25)

Change-Id: Ic5abb6ed50817ad2d165b5df46dd989eb195a9db
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17628
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Fix GICv3 overflow for INTID > 256

SPIs can get to a maximum number of 1023, so that an uint8_t is not capable
of representing all of them.

Change-Id: I7a2c43b41ac93eabdfcf8311681240416b954177
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17631
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)

For SGIs and PPIs:
* When ARE is 1 (only value supported in gem5) for the Security state of
an interrupt, the field for that interrupt is RES0 and an implementation
is permitted to make the field RAZ/WI in this case.

Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config: Use the corresponding HPI Caches when using the HPI cpu

The HPI cpu comes with specific cache definitions, but they
are ignored when using this cpu. This patch solves this in the same
way it is done for the O3_ARM_v7a cpu.

Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17708
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Fixed the indirect branch predictor GHR handling

The internal indirect predictor global history was not being updated
properly, resulting in higher than expected miss rates

Also added a parameter to set the size of the indirect predictor GHR

Change-Id: Ibc797816974cba6719da65122801e8919559a003
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reported-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16928
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Deleting this init() method was accidentally dropped during rebase.

Deleting this init() method was part of a change just committed, but
was accidentally dropped during a rebase.

Change-Id: I0f22778596ed11e182f3111d9999a0fef727f6cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17688
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Clean up the xbars a little.

Get rid of comments which just restate the code, get rid of redundant
"virtual" keywords, add "override"s, fix style, and get rid of
xbar::init which was empty and hiding the parent class init.

Change-Id: I8ce20abee340baa88084d142f2fb8c633ee54ba9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17592
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

base: Make AddrRangeMap able to return non-const iterators.

The erase() method only accepts regular iterators which is consistent
with the normal STL map, but the existing find() only returns const
iterators. The STL container can return either depending on if "this"
is const.

Unfortunately there isn't a great way to have only one find
implementation which returns the right type of iterator under the right
conditions. Also, it's not possible to turn a const_iterator into an
iterator, but it is possible to go the other way. This change
duplicates very short functions which return iterators, and for find
does the only thing I could find which avoids having to copy that
whole large function.

Change-Id: I2f789b5d0881feb9adff9978bd40e31731c6a688
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17588
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

configs: fix class reference in CacheConfigs

One reference was not properly updated when changing to absolute import paths

Change-Id: Idf330487d5d08d92ebb4489f16d75429f882bd7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Set/Unset dma coherent mode from python

With this patch it will be possible to automatically enable/disable the
dma-coherent property for the GenericArmPciHost autogenerated DTB.  This
has been done by adding the _dma_coherent param.

Change-Id: I1759fced74e42410462637ca77997a351314a90a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16748
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

base,python: Fix to allow multiple --debug-ignore values.

When adding multiple SimObjects to --debug-ignore, either separating the values with
a colon or adding multiple --debug-ignore flags, the previous code only ignored the
last SimObject in the list.  This changeset adds and uses new `ObjectMatch::add` and
`Logger::addIgnore` methods to make the functionality of the flag consistent with
its description.

Change-Id: Ib6967a48611ea59a211f81af2a970c4de429b1be
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17488
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

configs: Remove default kernel value from system creation

Kernel was being set using a placeholder and then assigned the
correct value. This would generate the following error if the
placeholder file did not exist:
'IOError: Can't find file <placeholder> on path'

This patch follows the same directions of commit
12eca7ac04ae1ba559bf322b5c625513929d369d and removes the default
values, forcing the user to properly configure the kernel.

Change-Id: I0eb45d12eda6b6efe9a3fe118996b640844a7b34
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Add missing fall-through defaults

Change-Id: Ie64b83d754c4719a77c7788879be71304a9b786e
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17289
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-power: Rename program counter registers

The Power ISA specification lists the Program Counter (PC) and
the Next Program Counter (NPC) registers as Current Instruction
Address (CIA) and Next Instruction Address (NIA). This applies
the ISA naming convention for these two registers.

Change-Id: I8b9094ab1c809f4dfdb4d7330c17f360adf063e9
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16603
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-power: Simplify doubleword operand types

Currently, 'sq' and 'uq' are used to represent signed and
unsigned doublewords respectively. Since all recent Power
ISA specifications list 128-bit quadwords as a valid data
type, it may be misleading to use the current terminology
in case support for such operands are added in the future.
So, to simplify this, 'sd' and 'ud' are used to represent
signed and unsigned doublewords respectively.

Change-Id: Ie7831c596fc8f9ddfdf3b652c37cfe26484ebe01
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16602
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

misc: missing override specifier

Missing specifier of overridden virtual function
declared in sim_object.hh

Removed redundant "virtual" keyword

Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim-se: Fixed initialization array size

Doubled the size of the zeroed auxiliary vector since 2 * intSize on
aarch64 > sizeof(uint64).

Change-Id: I5196b000a696e9ea3f2b5daa5d5bb071794369aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17088
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

base: Fix CircularQueue's operator-= when negative subtraction

Using operator-= when the rhs is a negative value is equivalent
to using += on -rhs. This is fixing rounding in that scenario.

Change-Id: Ia22e51f81a6805d27fd6b2115d288bb23421d00f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17528
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

base: Fix CircularQueue when diffing iterators

This patch is fixing CircularQueue iterators' subtraction, in particular
the behaviour when head and tail round multiple times.

Change-Id: Ie79ac8accd30a10cf039cf4def87675b01375d6b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17188
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: ambiguous use of getPort()

The recent introduction of getPort() creates a conflict with
the existing method used in arm MMU.

This patch rename the old getPort() in getDMAPort() according
to the returned value (DmaPort class type)

Change-Id: Ief3d83650fd6b08490522341631244be06e380ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17469
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tests: Add ignore for stdin not terminal

Change-Id: I496a9f3a0156557415d455dd2ca54c92577ca5f5
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17455
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

tests: Use full path for DownloadedProgram

Change-Id: I1dceca80a425293d64f81b06ddff499363f18bc0
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17454
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

tests: Fix race condition in download fixture

Change-Id: Idace0e9e71a484080fc581e232ce217b449085c1
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17453
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

ext,tests: Add back failing exceptions

Change-Id: Idf4ba8a2a3888787abf33d1a4ac52fcf146ce732
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17452
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

tests,ext: Add skip_cleanup implementation for TempdirFixture

Change-Id: Idc5ec9309a4ef3c0ad0c7e8b2df47294acc97ec4
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17451
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

ext,tests: Make return code based on test results

This patch also fixes a spelling mistake.

Change-Id: I8635216e512c10913a9cda54541d7e31e0d22a40
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17450
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

ext,test: Provide default terminal size

When creating the separator for printing things to the terminal (=.*) we
use an ioctl that isn't supported in some sandboxed environments. When
running on the Google jenkins server (kokoro) it errors with an IOError.

Change-Id: I148dd87cffe6e93d6723a386aecf9a9ea6c5b455
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17449
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu-kvm: Added informative error message

PerfKvmCounter::attach fails if the user doesn't have privileges to make
the perf_event_open syscall. This is the default privilege setting since
kernel 4.6. I've seen some users in the mailing list resort to running
as root; changing the perf_event_paranoid setting is an alternative.

Change-Id: I2bc6f76abb6e97bf34b408a611f64b1910f50a43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17508
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Added the STeMS prefetcher

Reference:
    Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and
    Babak Falsafi. 2009. Spatio-temporal memory streaming.
    In Proceedings of the 36th annual international symposium on
    Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80.

Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16423
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

systemc: Hook up gem5_getPort to the gem5 getPort mechanism.

Change-Id: I771607c4436f4c1ca9d355d1da52924308cfc3b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17229
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch, cpu, dev, gpu, mem, sim, python: start using getPort.

Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.

Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Switch to the new getPort mechanism to connect ports.

This retrieves ports using the getPort method, and connects them using
the bind method on the ports themselves. Any smarts as far as what type
of peers are allowed to connect or how they connect is left up to the
individual bind methods.

Change-Id: Ic640d1fce8af1bed411116e5830edc4a8a0f9d66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17039
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Move bind() and unbind() into the Port class.

These are now pure virtual methods which more specialized port
subclasses will need to implement. The SlavePort class implements them
by ignoring them and then providing parallel functions for the
MasterPort to call. The MasterPort's methods do basically what they
did before, except now bind() uses dynamic cast to check if its peer
is of the appropriate type and also to convert it into that type before
connecting to it.

Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17038
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim: Add a getPort function to SimObject.

This will retrieve a Port object from a given SimObject (which might
not be a MemObject) no matter what flavor of Port it is.

Change-Id: I636b85e9d4929a05a769e165849106bcb5f3e9c1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17037
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

util: Build m5 with -no-pie flag

Added -no-pie flag to link /util/m5 to support newer versions of GCC
that enable PIE by default. Tested for backwards compatibility with GCC
4.3, which, only warns for the unrecognized flag.

Change-Id: I4b6df593936346b9d3e2fe29a5d85dde78b7cc5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17429
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

python: Change || to && for MessageBuffers in connectPorts.

The connectPorts function currently checks if *either* of the peers in
a port connection are a MessageBuffer, and if so will ignore the
connection. This CL changes that || into a && so that *both* of the
peers need to be a Ruby types (either a MessageBuffer or Network) for
the connection to be ignored. That makes it easier to contain that
abnormal behavior to those types instead of having it apply even when
other types of port owners are involved.

Unfortunately the number of interesting Ruby types is unbounded, but
these are the types with ports as of today. This mechanism will
hopefully be replacedall together so this should be a temporary issue.

Change-Id: I140498770e5d37eb2abd3d99261d47e111f1c8ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17031
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

python: Improve how templated SimObject classes are handled.

When setting up a SimObject's Param structure, gem5 will autogenerate
a header file which attempts to declare the SimObject's C++ type. It
has had at least some level of sophistication there where it would
pull off the namespaces ahead of the class name and handle them
properly, but it didn't know how to handle templates.

This change improves that handling in two ways. First, it adds a new
magical SimObject attribute called 'cxx_template_params' which is used
to specify what the template parameters are as a list. For instance, if
your SimObject was a template which took an integer constant as its
first parameter and a type as its second, this attribute could look
like the following:

cxx_template_params = [ 'int FOO', 'class Bar' ]

Importantly, if there are any default values for these template
parameters, they should *not* be included here, they should be
specified where the class is later defined.

The second new mechanism is to add an internal CxxClass in the
SimObject.cxx_param_decl method. This class accepts the class signature
in the cxx_class attribute and the cxx_template_params and does two
things. First, it strips off namespaces like in the old implementation.
Second, it extracts and processes any template arguments attached to
the class. If these are constants (as determined by the contents of
cxx_template_params), then they are stored verbatim. If they're types,
then they're recursively expanded into a CxxClass and stored that way.
Note that these are the *values* of the template arguments, where as
cxx_template_params lists the *types* and *names* of those arguments.
In our earlier example, if cxx_class was:

cxx_class = 'CoolClasses::ClassName<12, Fruit::Apple>'

Then CxxClass would extract the namespace 'CoolClasses', the class
name 'ClassName', the argument '12', and the argument 'Fruit::Apple'.
That second argument would be expanded into a CxxClass with the
namespace 'Fruit' and the class name 'Apple'.

Importantly here, because there were no default arguments given in
cxx_template_params, all "hidden" arguments which would fall through
to their defaults need to be fully specified in cxx_class.

The CxxClass has a method called declare() which uses the information
extracted earlier to output all of the "stuff" necessary for declaring
the given class, including opening any containing namespaces and
putting template<...> ahead of the actual class declaration with the
template parameters specified.

If any of the template arguments are themselves CxxClass instances,
then they'll be recursively declared immediately before the current
class is.

An alternative solution to this problem might be to include the header
file which actually defines the cxx_class type to avoid having to
come up with a declaration. Unfortunately this doesn't work since it
can set up include loops where the SimObject C++ header file includes
the param header to get access to the Param type, but that includes
the C++ header to get access to the SimObject type.

This also makes it harder for SimObjects to refer to each other, since
they rely on the declaration in the params header files when declaring
a member pointer to that type in their own Param structures.

Change-Id: I68cfc36ddff6d789eb4cdef5178c4619ac2cc8b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17228
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

scons: fix disable_partial logic for fast binary

Partial linking should be disabled on darwin; however, the script
fails to do so when force_lto is set, which results in gem5 building
with fast option fails on macOS. This fix changes disable_partial
logic, which should be True once it's True.

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I77d2a4cc4a9bf5c92c800c004eb744bb7081c42e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16888
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

util: changed shebang on gem5img.py to python2.7

Change-Id: Id1a2112ce940bf6721609e2637d925d35e5ded8a
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17408
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: tautological comparison of byteOrder

Error:
build/X86/mem/cache/prefetch/indirect_memory.cc:56:24:
error: result of comparison of constant -1 with expression
of type 'const ByteOrder' is always false
[-Werror,-Wtautological-constant-out-of-range-compare]
    fatal_if(byteOrder == -1, "This prefetcher requires a defined ISA\n");
             ~~~~~~~~~ ^  ~~
build/X86/base/logging.hh:205:14: note: expanded from macro 'fatal_if'
        if ((cond)) {                                           \
             ^~~~
1 error generated.

Fix:
cast of constant (-1) used in comparison

Change-Id: I3deb154c2fe5b92c4ddf499176cb185c4ec7cf64
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17388
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

configs: Use absolute import paths

Use absoluate import paths to be Python 3 compatible. This also
imports absolute_import from __future__ to ensure that Python 2.7
behaves the same way as Python 3.

Change-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem: Removed circular include ref

If BasicLink.hh is modified, the style checker forces a reordering of
the includes, which results in build errors because it ends up including
Topology.hh before including its xxxParams.hh files, which include
forward declarations of the BasicLink family of classes, and so
Topology.hh throws errors that BasicLink etc. are not declared.

Change-Id: I664a0652e53f0cc61763c2190a980c655b85d397
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17270
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Added the Indirect Memory Prefetcher

Reference:
    Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas.
    2015. IMP: indirect memory prefetcher. In Proceedings of the 48th
    International Symposium on Microarchitecture (MICRO-48). ACM,
    New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807

Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16223
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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