bugzilla-daemon [Sun, 7 Jun 2020 23:02:24 +0000 (23:02 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Sun, 7 Jun 2020 22:55:38 +0000 (22:55 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 7 Jun 2020 22:48:48 +0000 (22:48 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Sun, 7 Jun 2020 22:47:59 +0000 (22:47 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Sun, 7 Jun 2020 22:45:21 +0000 (22:45 +0000)]
[libre-riscv-dev] [Bug 366] Create new buzilla product "Systemes Libres Organization"
bugzilla-daemon [Sun, 7 Jun 2020 22:39:59 +0000 (22:39 +0000)]
[libre-riscv-dev] [Bug 366] Create new buzilla product "Systemes Libres Organization"
bugzilla-daemon [Sun, 7 Jun 2020 22:39:53 +0000 (22:39 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Sun, 7 Jun 2020 22:34:24 +0000 (22:34 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 22:34:22 +0000 (22:34 +0000)]
[libre-riscv-dev] [Bug 368] Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Sun, 7 Jun 2020 22:32:17 +0000 (22:32 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 22:31:59 +0000 (22:31 +0000)]
[libre-riscv-dev] [Bug 368] New: Need one example unit test of how to run some assembly code "qemu vs simulator" rather than "qemu vs hardware"
bugzilla-daemon [Sun, 7 Jun 2020 21:39:08 +0000 (21:39 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 21:31:40 +0000 (21:31 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 21:23:25 +0000 (21:23 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 21:23:07 +0000 (21:23 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 21:18:35 +0000 (21:18 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 21:11:59 +0000 (21:11 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 20:51:52 +0000 (20:51 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 20:45:35 +0000 (20:45 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 20:42:16 +0000 (20:42 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 20:35:32 +0000 (20:35 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 7 Jun 2020 20:31:57 +0000 (20:31 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR
bugzilla-daemon [Sun, 7 Jun 2020 20:29:52 +0000 (20:29 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 20:25:20 +0000 (20:25 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR
bugzilla-daemon [Sun, 7 Jun 2020 20:21:27 +0000 (20:21 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 20:19:47 +0000 (20:19 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR
bugzilla-daemon [Sun, 7 Jun 2020 17:52:27 +0000 (17:52 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 17:41:08 +0000 (17:41 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 15:08:16 +0000 (15:08 +0000)]
[libre-riscv-dev] [Bug 360] move RS to 1st or 2nd operand in CSV files
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 15:03:39 +0000 (16:03 +0100)]
[libre-riscv-dev] daily kan-ban update 07jun2020
bugzilla-daemon [Sun, 7 Jun 2020 14:32:31 +0000 (14:32 +0000)]
[libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline
bugzilla-daemon [Sun, 7 Jun 2020 06:26:29 +0000 (06:26 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 06:11:44 +0000 (06:11 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 04:30:04 +0000 (04:30 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 03:47:26 +0000 (03:47 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 03:31:57 +0000 (03:31 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 03:23:45 +0000 (03:23 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 03:09:59 +0000 (03:09 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 03:03:20 +0000 (03:03 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 02:50:16 +0000 (02:50 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sun, 7 Jun 2020 02:36:42 +0000 (02:36 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 02:21:38 +0000 (03:21 +0100)]
Re: [libre-riscv-dev] Scoreboard Tests
bugzilla-daemon [Sun, 7 Jun 2020 02:09:30 +0000 (02:09 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 01:56:46 +0000 (01:56 +0000)]
[libre-riscv-dev] [Bug 364] CXXRTL Python Interface
bugzilla-daemon [Sun, 7 Jun 2020 01:54:22 +0000 (01:54 +0000)]
[libre-riscv-dev] [Bug 364] CXXRTL Python Interface
bugzilla-daemon [Sun, 7 Jun 2020 01:52:29 +0000 (01:52 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 01:42:35 +0000 (01:42 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 01:32:06 +0000 (01:32 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 01:22:30 +0000 (01:22 +0000)]
[libre-riscv-dev] [Bug 364] CXXRTL Python Interface
Yehowshua [Sun, 7 Jun 2020 01:07:27 +0000 (21:07 -0400)]
[libre-riscv-dev] Scoreboard Tests
bugzilla-daemon [Sun, 7 Jun 2020 01:03:56 +0000 (01:03 +0000)]
[libre-riscv-dev] [Bug 366] Create new buzilla product "Systemes Libres Organization"
bugzilla-daemon [Sun, 7 Jun 2020 00:57:20 +0000 (00:57 +0000)]
[libre-riscv-dev] [Bug 184] new mailing lists proposal for libre-soc.org
bugzilla-daemon [Sun, 7 Jun 2020 00:55:19 +0000 (00:55 +0000)]
[libre-riscv-dev] [Bug 366] Create new buzilla product "Systemes Libres Organization"
bugzilla-daemon [Sun, 7 Jun 2020 00:52:39 +0000 (00:52 +0000)]
[libre-riscv-dev] [Bug 367] New: Setup weekly 30 min organizational video call like OPF Virtual Coffee Calls
bugzilla-daemon [Sun, 7 Jun 2020 00:51:09 +0000 (00:51 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 00:50:24 +0000 (00:50 +0000)]
[libre-riscv-dev] [Bug 366] New: Create new buzilla product "Systemes Libres Organization"
bugzilla-daemon [Sun, 7 Jun 2020 00:44:51 +0000 (00:44 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 00:39:27 +0000 (00:39 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 00:38:30 +0000 (00:38 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 00:31:59 +0000 (00:31 +0000)]
[libre-riscv-dev] [Bug 184] new mailing lists proposal for libre-soc.org
bugzilla-daemon [Sun, 7 Jun 2020 00:31:50 +0000 (00:31 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 7 Jun 2020 00:29:05 +0000 (00:29 +0000)]
[libre-riscv-dev] [Bug 184] new mailing lists proposal for libre-soc.org
bugzilla-daemon [Sun, 7 Jun 2020 00:28:35 +0000 (00:28 +0000)]
[libre-riscv-dev] [Bug 364] CXXRTL Python Interface
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 00:27:02 +0000 (01:27 +0100)]
Re: [libre-riscv-dev] Successful subscription
bugzilla-daemon [Sun, 7 Jun 2020 00:25:13 +0000 (00:25 +0000)]
[libre-riscv-dev] [Bug 364] CXXRTL Python Interface
Sanjay Menon [Sun, 7 Jun 2020 00:01:40 +0000 (05:31 +0530)]
[libre-riscv-dev] Successful subscription
bugzilla-daemon [Sun, 7 Jun 2020 00:01:49 +0000 (00:01 +0000)]
[libre-riscv-dev] [Bug 364] CXXRTL Python Interface
bugzilla-daemon [Sat, 6 Jun 2020 23:59:39 +0000 (23:59 +0000)]
[libre-riscv-dev] [Bug 364] CXXRTL Python Interface
bugzilla-daemon [Sat, 6 Jun 2020 23:58:28 +0000 (23:58 +0000)]
[libre-riscv-dev] [Bug 365] ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sat, 6 Jun 2020 23:57:35 +0000 (23:57 +0000)]
[libre-riscv-dev] [Bug 365] New: ROCM/Libre-SOC GPU Opcode interoperability
bugzilla-daemon [Sat, 6 Jun 2020 23:55:56 +0000 (23:55 +0000)]
[libre-riscv-dev] [Bug 362] improvements to nmigen and yosys
bugzilla-daemon [Sat, 6 Jun 2020 23:55:16 +0000 (23:55 +0000)]
[libre-riscv-dev] [Bug 364] CXXRTL Python Interface
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 23:49:12 +0000 (00:49 +0100)]
Re: [libre-riscv-dev] FHDLTestCase
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 23:45:43 +0000 (00:45 +0100)]
Re: [libre-riscv-dev] FHDLTestCase
Yehowshua [Sat, 6 Jun 2020 23:45:29 +0000 (19:45 -0400)]
Re: [libre-riscv-dev] FHDLTestCase
bugzilla-daemon [Sat, 6 Jun 2020 23:41:50 +0000 (23:41 +0000)]
[libre-riscv-dev] [Bug 364] Python YosysCXX Interface
bugzilla-daemon [Sat, 6 Jun 2020 23:41:15 +0000 (23:41 +0000)]
[libre-riscv-dev] [Bug 364] New: Python YosysCXX Interface
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 23:34:43 +0000 (00:34 +0100)]
Re: [libre-riscv-dev] FHDLTestCase
Yehowshua [Sat, 6 Jun 2020 23:27:58 +0000 (19:27 -0400)]
Re: [libre-riscv-dev] FHDLTestCase
Yehowshua [Sat, 6 Jun 2020 23:22:33 +0000 (19:22 -0400)]
Re: [libre-riscv-dev] FHDLTestCase
bugzilla-daemon [Sat, 6 Jun 2020 23:22:21 +0000 (23:22 +0000)]
[libre-riscv-dev] [Bug 274] Investigate how BSV performs Formal Verification and what can be Applied to FPUs
bugzilla-daemon [Sat, 6 Jun 2020 23:19:37 +0000 (23:19 +0000)]
[libre-riscv-dev] [Bug 274] Investigate how BSV performs Formal Verification and what can be Applied to FPUs
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 23:15:17 +0000 (00:15 +0100)]
[libre-riscv-dev] FHDLTestCase
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 23:13:02 +0000 (00:13 +0100)]
Re: [libre-riscv-dev] Contributing to the Libre-Soc Project
bugzilla-daemon [Sat, 6 Jun 2020 23:11:24 +0000 (23:11 +0000)]
[libre-riscv-dev] [Bug 274] Investigate how BSV performs Formal Verification and what can be Applied to FPUs
Yehowshua [Sat, 6 Jun 2020 23:03:36 +0000 (19:03 -0400)]
Re: [libre-riscv-dev] Contributing to the Libre-Soc Project
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 22:48:38 +0000 (23:48 +0100)]
Re: [libre-riscv-dev] Introduction and Questions
Yehowshua [Sat, 6 Jun 2020 22:47:14 +0000 (18:47 -0400)]
Re: [libre-riscv-dev] Introduction and Questions
Sanjay Menon [Sat, 6 Jun 2020 22:29:24 +0000 (03:59 +0530)]
[libre-riscv-dev] Contributing to the Libre-Soc Project
Jeremy Singher [Fri, 15 May 2020 06:50:57 +0000 (23:50 -0700)]
[libre-riscv-dev] Introduction and Questions
bugzilla-daemon [Sat, 6 Jun 2020 22:38:35 +0000 (22:38 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sat, 6 Jun 2020 21:20:52 +0000 (21:20 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sat, 6 Jun 2020 20:53:05 +0000 (20:53 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sat, 6 Jun 2020 20:33:53 +0000 (20:33 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 13:09:38 +0000 (14:09 +0100)]
[libre-riscv-dev] daily kan-ban update 06jun2020
bugzilla-daemon [Sat, 6 Jun 2020 12:25:59 +0000 (12:25 +0000)]
[libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices
bugzilla-daemon [Sat, 6 Jun 2020 12:23:56 +0000 (12:23 +0000)]
[libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices
bugzilla-daemon [Sat, 6 Jun 2020 11:23:25 +0000 (11:23 +0000)]
[libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices
bugzilla-daemon [Sat, 6 Jun 2020 11:20:42 +0000 (11:20 +0000)]
[libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices
bugzilla-daemon [Sat, 6 Jun 2020 11:03:21 +0000 (11:03 +0000)]
[libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability
projects / libre-riscv-dev.git / log