Tobias Platen [Wed, 30 Mar 2022 19:12:55 +0000 (21:12 +0200)]
begin merge of soc.vhdl, fix Makefile
Tobias Platen [Mon, 28 Mar 2022 18:35:49 +0000 (20:35 +0200)]
add read_verilog when using external core
Tobias Platen [Sun, 27 Mar 2022 17:33:39 +0000 (19:33 +0200)]
more work on verilator backport
Tobias Platen [Sun, 27 Mar 2022 16:41:34 +0000 (18:41 +0200)]
begin verilator_trace backport
Tobias Platen [Thu, 24 Mar 2022 15:47:11 +0000 (16:47 +0100)]
try using plru_dummy.vhdl
Tobias Platen [Wed, 23 Mar 2022 18:32:09 +0000 (19:32 +0100)]
partial synthesize with EXTERNAL_CORE
Tobias Platen [Wed, 23 Mar 2022 16:15:07 +0000 (17:15 +0100)]
allow using external core
Tobias Platen [Tue, 22 Mar 2022 18:58:46 +0000 (19:58 +0100)]
Merge remote-tracking branch 'to-be-merged/merge-3d-game'
Michael Neuling [Tue, 22 Mar 2022 00:55:54 +0000 (11:55 +1100)]
Merge pull request #361 from antonblanchard/alt-reset-address
Allow ALT_RESET_ADDRESS to be overridden
Anton Blanchard [Mon, 21 Mar 2022 22:35:17 +0000 (09:35 +1100)]
Allow ALT_RESET_ADDRESS to be overridden
This allows us to boot from flash for example.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling [Fri, 18 Mar 2022 07:28:34 +0000 (18:28 +1100)]
Merge pull request #360 from antonblanchard/log2ceil-issue
wishbone_bram_wrapper ram_addr_bits is 1 bit off
Anton Blanchard [Thu, 17 Mar 2022 07:03:29 +0000 (18:03 +1100)]
wishbone_bram_wrapper ram_addr_bits is 1 bit off
log2ceil() returns the number of bits required to store a value, so we
need to pass in memory_size-1, not memory_size.
Every other user of log2ceil() gets this right.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling [Tue, 15 Mar 2022 23:49:47 +0000 (10:49 +1100)]
Merge pull request #358 from antonblanchard/unused-sig
Remove unused sequential signal from Fetch1ToIcacheType
Michael Neuling [Tue, 15 Mar 2022 23:49:29 +0000 (10:49 +1100)]
Merge pull request #356 from antonblanchard/fpu-constant
fpu: Make inverse_table a constant
Michael Neuling [Tue, 15 Mar 2022 23:48:59 +0000 (10:48 +1100)]
Merge pull request #357 from antonblanchard/xics-warning
xics: Fix warning when comparing two std_ulogic_vectors
Anton Blanchard [Tue, 15 Mar 2022 07:27:48 +0000 (18:27 +1100)]
Remove unused sequential signal from Fetch1ToIcacheType
GHDL synthesis is flagging a warning about this.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 15 Mar 2022 05:04:18 +0000 (16:04 +1100)]
xics: Fix warning when comparing two std_ulogic_vectors
Use unsigned() to make it clear what we are doing.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 15 Mar 2022 05:03:34 +0000 (16:03 +1100)]
fpu: Make inverse_table a constant
GHDL synthesis is complaining that inverse_table is never stored to.
Change it to a constant.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Jacob Lifshay [Fri, 4 Mar 2022 11:43:09 +0000 (03:43 -0800)]
add 3d game
I added a simple 3D maze game that is a pretty impressive demo of what Microwatt can do.
It's based on #347
Signed-off-by: Jacob Lifshay <programmerjake@gmail.com>
Matt Johnston [Thu, 3 Mar 2022 09:05:41 +0000 (17:05 +0800)]
Makefile: Don't force generic USE_LITEDRAM=true
That makes it easier to override a non-litedram build for testing
RAM_INIT_FILE, eg
make microwatt.dfu LITEDRAM_GHDL_ARG=-gUSE_LITEDRAM=false RAM_INIT_FILE=usb_hello/usb_hello.hex
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Mon, 7 Feb 2022 09:07:14 +0000 (17:07 +0800)]
valentyusb: Add software for liteuart console
usb_hello is a copy of hello_world but uses both consoles
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Mon, 7 Feb 2022 09:09:20 +0000 (17:09 +0800)]
valentyusb: Add USB UART to SOC and OrangeCrab
An extra uart is added at 0xc0008000 attached to valentyusb, using
the OrangeCrab's onboard USB port.
This has a liteuart interface, an identifier bit is added to syscon.
Generated from branch hw_cdc_eptri of
https://github.com/litex-hub/valentyusb
The generate script is based on valentyusb/sim/generate_verilog.py
UARTUSB: usbserial@8000 {
device_type = "serial";
compatible = "litex,liteuart";
reg = <0x8000 0x100>;
interrupts = <0x15 0x1>;
};
(requires extra kernel patches for early console at present v5.16)
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Wed, 27 Oct 2021 10:43:13 +0000 (18:43 +0800)]
Makefile: depend on soc_extra_v
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Michael Neuling [Sun, 27 Feb 2022 21:17:50 +0000 (08:17 +1100)]
Merge pull request #352 from mkj/static-urjtag
mw_debug: Add STATIC_URJTAG flag
Matt Johnston [Fri, 25 Feb 2022 09:43:28 +0000 (17:43 +0800)]
mw_debug: Add STATIC_URJTAG flag
Revert to linking dynamically by default, can statically link with
`make STATIC_URJTAG=1`
Fixes #351
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Michael Neuling [Fri, 25 Feb 2022 02:18:38 +0000 (13:18 +1100)]
Update the README Issues (#350)
We've had these for a while now:
- D/I cache
- GPR bypassing
- Supervisor state (and can boot linux)
We still need Vector/VMX/VSX (and probably some other things)
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Fri, 25 Feb 2022 00:08:57 +0000 (11:08 +1100)]
Merge pull request #349 from madscientist159/master
Extend LiteDRAM VHDL wrapper to allow more than one clock line
Raptor Engineering Development Team [Tue, 22 Feb 2022 17:49:33 +0000 (11:49 -0600)]
Extend LiteDRAM VHDL wrapper to allow more than one clock line
This is necessary for the upcoming Arctic Tern system enablement,
since Arctic Tern uses two DRAM devices and a separate clock line
is routed to each device. LiteX handles this behavior correctly,
therefore we assume other hardware exists that uses a similar
DRAM clock design.
Updates from Mikey to fix some compile issues.
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Wed, 23 Feb 2022 01:03:59 +0000 (12:03 +1100)]
Merge pull request #348 from paulusmack/reduce
Reduce LUT usage
Paul Mackerras [Tue, 19 Oct 2021 04:13:31 +0000 (15:13 +1100)]
xics: Rework the irq_gen process
At present, the loop in the irq_gen process generates a chain of
comparators and other logic to work out the source number and priority
of the most-favoured (lowest priority number) pending interrupt.
This replaces that chain with (1) logic to generate an array of bits,
one per priority, indicating whether any interrupt is pending at that
priority, (2) a priority encoder to select the most favoured priority
with an interrupt pending, (3) logic to generate an array of bits, one
per source, indicating whether an interrupt is pending at the priority
calculated in step 2, and (4) a priority encoder to work out the
lowest numbered source that has an interrupt pending at the selected
priority. This reduces LUT utilization.
The priority encoder function implemented here uses the optimized
count-leading-zeroes logic from helpers.vhdl.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 21 Feb 2022 01:06:11 +0000 (12:06 +1100)]
Use alternative count-leading-zeroes algorithm in the FPU and LSU
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sun, 20 Feb 2022 22:58:07 +0000 (09:58 +1100)]
countzero: Use alternative algorithm for higher bits
This implements an alternative count-leading-zeroes algorithm which
uses less LUTs to generate the higher-order bits (2..5) of the
result.
By doing (v | -v) rather than (v & -v), we get a value which has ones
from the MSB down to the rightmost 1 bit in v and then zeroes down to
the LSB. This means that we can generate the MSB of the result (the
index of the rightmost 1 bit in v) just by looking at bits 63 and 31
of (v | -v), assuming that v is 64 bits. Bit 4 of the result requires
looking at bits 63, 47, 31 and 15. In contrast, each bit of the
result using (v & -v), which has a single 1, requires ORing together
32 bits.
It turns out that the minimum LUT usage comes from using (v & -v) to
generate bits 0 and 1 of the result, and using (v | -v) to generate
bits 2 to 5. This saves almost 60 6-input LUTs on the Artix-7.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 11 Oct 2021 06:46:44 +0000 (17:46 +1100)]
soc: Re-do peripheral address decode to improve timing
This generates a series of io_cycle_* signals which are clean latches
and which become the 'cyc' signals of the wishbone buses going to
various peripherals (syscon, uarts, XICS, GPIO, etc.). Effectively
this is done by moving the address decoding into the slave_io_latch
process. The slave_io_type, which drives the multiplexer which
selects which wishbone to look for a response on, is reduced to just 8
values in the expectation that an 8-way multiplexer will use less
logic than one with more than 8 inputs.
With this timing is considerably better on the A7-100T.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Michael Neuling [Mon, 7 Feb 2022 22:09:22 +0000 (09:09 +1100)]
Merge pull request #346 from mkj/dmi_ecp5
Add DMI and mw_debug for ECP5
Anton Blanchard [Mon, 7 Feb 2022 06:57:08 +0000 (17:57 +1100)]
Merge pull request #343 from mikey/orange-crab-ci
ci: Add new Orange Crab build
Matt Johnston [Fri, 4 Feb 2022 07:29:40 +0000 (15:29 +0800)]
mw_debug: Add Lattice ECP5 support
"-b ecp5" will select ECP5 interface that talks to a JTAGG
primitive.
For example with a FT232H JTAG board:
./mw_debug -t 'ft2232 vid=0x0403 pid=0x6014' -s
30000000 -b ecp5 mr
ff003888 6
Connected to libftdi driver.
Found device ID: 0x41113043
00000000ff003888:
6d6f636c65570a0a ..Welcom
00000000ff003890:
63694d206f742065 e to Mic
00000000ff003898:
2120747461776f72 rowatt !
00000000ff0038a0:
0000000000000a0a ........
00000000ff0038a8:
67697320636f5320 Soc sig
00000000ff0038b0:
203a65727574616e nature:
Core: running
NIA:
c0000000000187f8
MSR:
9000000000001033
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Fri, 26 Nov 2021 02:47:07 +0000 (10:47 +0800)]
dmi_dtm_ecp5: Use ECP5 JTAGG for DMI
This uses the JTAGG primitive which is similar to BSCANE2.
The LUT4 delay approach came from Florian and Greg in
https://github.com/enjoy-digital/litex/pull/1087
Has been tested on an OrangeCrab with 48MHz sysclk
FT232H up to 30MHz (though libusb/urjtag is by far the bottleneck vs
the JTAG clock)
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Fri, 4 Feb 2022 06:40:42 +0000 (14:40 +0800)]
mw_debug: Link urjtag statically
liburjtag isn't in Debian, so usually we're pointing at a urjtag
build directory when building mw_debug
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Fri, 4 Feb 2022 04:08:07 +0000 (12:08 +0800)]
mw_debug: use isxdigit for hex arguments
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Fri, 26 Nov 2021 02:43:06 +0000 (10:43 +0800)]
mw_debug: Add -s frequency argument
Chose -s for speed, vs -f for --force
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Thu, 25 Nov 2021 06:12:13 +0000 (14:12 +0800)]
mw_debug: pass target parameters to urjtag
An example
./mw_debug -d -t 'ft2232 vid=0x0403 pid=0x6014'
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Paul Mackerras [Mon, 11 Oct 2021 06:23:08 +0000 (17:23 +1100)]
fetch1/icache1: Remove the use_previous logic
This removes logic that I added some time ago with the thought that it
would enable us to do prefetching in the icache. This logic detects
when the fetch address is an odd multiple of 4 and the next address in
sequence from the previous cycle. In that case the instruction we
want is in the output register of the icache RAM already so there is
no need to do another read or any icache tag or TLB lookup.
However, this logic adds complexity, and removing it improves timing,
so this removes it.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 4 Feb 2022 00:43:42 +0000 (11:43 +1100)]
Merge pull request #345 from antonblanchard/popcnt-go-fast
popcnt* timing improvements from Paul
Paul Mackerras [Tue, 19 Oct 2021 01:22:10 +0000 (12:22 +1100)]
core: Make popcnt* take two cycles
This moves the calculation of the result for popcnt* into the
countbits unit, renamed from countzero, so that we can take two cycles
to get the result. The motivation for this is that the popcnt*
calculation was showing up as a critical path.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Michael Neuling [Tue, 18 Jan 2022 01:41:03 +0000 (12:41 +1100)]
ci: Add new Orange Crab build
This builds the Orange Crab v0.21 + litedram image
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Tue, 18 Jan 2022 02:27:27 +0000 (13:27 +1100)]
Merge pull request #342 from mkj/orangecrab-merge
Orangecrab working with litedram
Fixed up a few simple merge conflicts in the Makefile.
Michael Neuling [Tue, 18 Jan 2022 01:03:46 +0000 (12:03 +1100)]
Merge branch 'master' into orangecrab-merge
Michael Neuling [Tue, 18 Jan 2022 00:51:54 +0000 (11:51 +1100)]
Merge pull request #341 from mkj/progtools
orangecrab programming targets
Michael Neuling [Tue, 18 Jan 2022 00:50:22 +0000 (11:50 +1100)]
Merge pull request #340 from mkj/orangecrab-ghdl-plugin
Makefile: detect when ghdl is a yosys plugin
Matt Johnston [Fri, 19 Nov 2021 05:13:15 +0000 (13:13 +0800)]
orangecrab: Fix sdcard wishbone addressing
Orangecrab missed out on:
Make wishbone addresses be in units of doublewords or words
Author: Paul Mackerras <paulus@ozlabs.org>
Date: Wed Sep 15 18:18:09 2021 +1000
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Fri, 14 Jan 2022 00:04:18 +0000 (08:04 +0800)]
orangecrab: use litesdcard
Currently not working (tested in Linux)
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Fri, 14 Jan 2022 00:08:09 +0000 (08:08 +0800)]
litesdcard: add lattice, regenerate
Modifies litescard generate script to take a clock speed.
Regenerated verilog with latest litesdcard
e52c731 ("Bump year.")
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Mon, 23 Aug 2021 02:30:40 +0000 (10:30 +0800)]
orangecrab: No BTC, LOG_LENGTH, dram NUM_LINES
Reduce litedram NUM_LINES 64->8
This allows us to meet timing. Can probably
be improved in future with better BRAM usage.
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Thu, 13 Jan 2022 08:51:57 +0000 (16:51 +0800)]
orangecrab: Use litedram
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Wed, 24 Nov 2021 08:47:16 +0000 (16:47 +0800)]
orangecrab: set HAS_SHORT_MULT
It seems free, generated as a single MULT18X18D
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Wed, 11 Aug 2021 05:11:57 +0000 (13:11 +0800)]
orangecrab: add Orange Crab r0.2 target
top-orangecrab0.2 is a copy of top-arty with various changes.
USRMCLK is added for the SPI clock
ethernet is removed
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Fri, 13 Aug 2021 02:07:15 +0000 (10:07 +0800)]
litedram: Add orangecrab-85-0.2 target
Parameters are based on
https://github.com/gregdavill/OrangeCrab-test-sw/blob/main/hw/OrangeCrab-bitstream.py
and litex-boards orangecrab.py
rtt_nom and cmd_delay are overridden for OrangeCrab, we do the same here.
Generated with litedram and litex
62abf9c ("litedram_gen: Add block_until_ready port parameter to control blocking behaviour.")
add2746a ("tools/litex_cli: Rename wb to bus.")
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Fri, 24 Sep 2021 04:24:29 +0000 (12:24 +0800)]
litedram: set Makefile -Werror
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Thu, 13 Jan 2022 23:23:35 +0000 (07:23 +0800)]
litedram: disable block_until_ready, regenerate
Recent litedram gets stuck at memtest unless block_until_ready=False.
(discussion in https://github.com/enjoy-digital/litedram/pull/292)
This change regenerates with latest litedram and litex
62abf9c ("litedram_gen: Add block_until_ready port parameter to control blocking behaviour.")
add2746a ("tools/litex_cli: Rename wb to bus.")
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Fri, 26 Nov 2021 02:33:55 +0000 (10:33 +0800)]
Makefile: add ecpprog targets
The 0x80000 offset is specific to the OrangeCrab bootloader.
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Wed, 11 Aug 2021 05:07:34 +0000 (13:07 +0800)]
Makefile: Add DFU programming
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston [Wed, 11 Aug 2021 07:17:39 +0000 (15:17 +0800)]
Makefile: detect when ghdl is a yosys plugin
oss-cad-suite builds it as a plugin, some other toolchains
have it built in.
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Anton Blanchard [Sat, 8 Jan 2022 21:08:48 +0000 (08:08 +1100)]
Merge pull request #338 from shenki/yosys-read-verilog
Makefile: Use read_verilog with yosys
Joel Stanley [Mon, 20 Dec 2021 22:32:24 +0000 (09:02 +1030)]
Makefile: Use read_verilog with yosys
Yosys changed command line behaviour following the v0.12 release. Work
around this by using read_verilog, which maintains the old behaviour.
This should work fine for current yosys and be compatible with
future releases.
See https://github.com/YosysHQ/yosys/issues/3109
Signed-off-by: Joel Stanley <joel@jms.id.au>
Michael Neuling [Mon, 25 Oct 2021 05:49:19 +0000 (16:49 +1100)]
Merge pull request #337 from paulusmack/fixes
ECP5: Adjust PLL constants so the PLL lock indication works
Paul Mackerras [Sat, 16 Oct 2021 08:24:14 +0000 (19:24 +1100)]
ECP5: Adjust PLL constants so the PLL lock indication works
At present, code (such as simple_random) which produces serial port
output during the first few milliseconds of operation produces garbled
output. The reason is that the clock has not yet stabilized and is
running slow, resulting in the bit time of the serial characters being
too long.
The ECP5 data sheet says that the phase detector should be operated
between 10 and 400 MHz. The current code operates it at 2MHz.
Consequently, the PLL lock indication doesn't work, i.e. it is always
zero. The current code works around that by inverting it, i.e. taking
the "not locked" indication to mean "locked".
Instead, we now run it at 12MHz, chosen because the common external
clock inputs on ECP5 boards are 12MHz and 48MHz. Normally this would
mean that the available system clock frequencies would be multiples of
12MHz, but this is a little inconvenient as we use 40MHz on the Orange
Crab v0.21 boards. Instead, by using the secondary clock output for
feedback, we can have any divisor of the PLL frequency as the system
clock frequency.
The ECP5 data sheet says the PLL oscillator can run at 400 to 800
MHz. Here we choose 480MHz since that allows us to generate 40MHz and
48MHz easily and is a multiple of 12MHz.
With this, the lock signal works correctly, and the inversion can be
removed.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Michael Neuling [Wed, 13 Oct 2021 06:44:47 +0000 (17:44 +1100)]
Merge pull request #336 from paulusmack/fixes
Makefile: Correct parameters for the Orange Crab 85F
Paul Mackerras [Tue, 12 Oct 2021 07:30:36 +0000 (18:30 +1100)]
Makefile: Add a target for the Orange Crab v0.21 with LFE5U-85F
The existing orange crab target is for an older board with a
LFE5UM5G-85F device. Newer orange crab boards (v0.21) have a
LFE5U-85F device in the -8 speed grade, so make a new target for them
called ORANGE-CRAB-0.21.
Also add flags to ecppack to indicate that the bitstream should be
compressed and can be loaded at 38.8MHz.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Michael Neuling [Mon, 27 Sep 2021 23:06:18 +0000 (09:06 +1000)]
Merge pull request #334 from antonblanchard/icbi-issue
Add a test for icbi and dcbz issues
Anton Blanchard [Mon, 27 Sep 2021 20:18:59 +0000 (06:18 +1000)]
Merge pull request #335 from ozbenh/misc
Misc cleanups and icache fix
Benjamin Herrenschmidt [Mon, 27 Sep 2021 12:03:18 +0000 (22:03 +1000)]
icache: req_laddr becomes req_raddr
Uses real_addr_t and only stores the real address bits
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Mon, 27 Sep 2021 11:53:52 +0000 (21:53 +1000)]
Introduce addr_to_wb() and wb_to_addr() helpers
These convert addresses to/from wishbone addresses, and use them
in parts of the caches, in order to make the code a bit more readable.
Along the way, rename some functions in the caches to make it a bit
clearer what they operate on and fix a bug in the icache STOP_RELOAD state where
the wb address wasn't properly converted.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Mon, 27 Sep 2021 11:50:57 +0000 (21:50 +1000)]
Introduce real_addr_t and addr_to_real()
This moves REAL_ADDR_BITS out of the caches and defines a real_addr_t
type for a real address, along with a addr_to_real() conversion helper.
It makes the vhdl a bit more readable
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Thu, 23 Sep 2021 05:47:52 +0000 (15:47 +1000)]
tests/misc: Add a store/dcbz test
We have a bug where an store near a dcbz can cause the dcbz to only zero
8 bytes. Add a test case for this.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 23 Sep 2021 02:23:22 +0000 (12:23 +1000)]
tests/misc: Add an icbi test
We have a bug where an icbi can cause an instruction to execute twice.
Add a test case for this.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 27 Sep 2021 03:41:37 +0000 (13:41 +1000)]
Merge pull request #333 from ozbenh/wukong
Add support for QMTech Wukong v2 board
Benjamin Herrenschmidt [Fri, 24 Sep 2021 04:24:37 +0000 (14:24 +1000)]
Regenerate litedram and liteeth
Note: There are a few patches to upstream to fix an upstream breakage
of litedram standalone generator, and fix some issues with liteeth
in the way it's used on Wukong. All these have pending pull requests.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 24 Sep 2021 04:24:37 +0000 (14:24 +1000)]
Add support for QMTech Wukong v2 board
For now only the V2 of the board (slightly different pinout)
and only the A100T variant. I also haven't added GPIOs or anything
else on the PMODs really.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 24 Sep 2021 04:24:37 +0000 (14:24 +1000)]
fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz
50Mhz clkin, 100Mhz sys_clk, as needed for Wukon v2
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 24 Sep 2021 04:24:37 +0000 (14:24 +1000)]
Add support for more spansion flash
That's the one on the Wukong v2
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Sat, 25 Sep 2021 05:15:24 +0000 (15:15 +1000)]
Merge pull request #332 from paulusmack/fixes
Bug fixes
Paul Mackerras [Sat, 25 Sep 2021 03:18:59 +0000 (13:18 +1000)]
dcache: Fix bug with dcbz closely following stores with the same tag
This fixes a bug where a dcbz can get incorrectly handled as an
ordinary 8-byte store if it arrives while the dcache state machine is
handling other stores with the same tag value (i.e. within the same
set-sized area of memory). The logic that says whether to include a
new store in the current wishbone cycle didn't take into account
whether the new store was a dcbz. This adds a "req.dcbz = '0'" factor
so that it does. This is necessary because dcbz is handled more like
a cache line refill (but writing to memory rather than reading) than
an ordinary store.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 25 Sep 2021 01:34:38 +0000 (11:34 +1000)]
icache: Fix icache invalidation
This fixes two bugs in the flash invalidation of the icache.
The first is that an instruction could get executed twice. The
i-cache RAM is 2 instructions (64 bits) wide, so one read can supply
results for 2 cycles. The fetch1 stage tells icache when the address
is equal to the address of the previous cycle plus 4, and in cases
where that is true, bit 2 of the address is 1, and the previous cycle
was a cache hit, we just use the second word of the doubleword read
from the cache RAM. However, the cache hit/miss logic also continues
to operate, so in the case where the first word hits but the second
word misses (because of an icache invalidation or a snoop occurring in
the first cycle), we supply the instruction from the data previously
read from the icache RAM but also stall fetch1 and start a cache
reload sequence, and subsequently supply the second instruction
again. This fixes the issue by inhibiting req_is_miss and stall_out
when use_previous is true.
The second bug is that if an icache invalidation occurs while
reloading a line, we continue to reload the line, and make it valid
when the reload finishes, even though some of the data may have been
read before the invalidation occurred. This adds a new state
STOP_RELOAD which we go to if an invalidation happens while we are in
CLR_TAG or WAIT_ACK state. In STOP_RELOAD state we don't request any
more reads from memory and wait for the reads we have previously
requested to be acked, and then go to IDLE state. Data returned is
still written to the icache RAM, but that doesn't matter because the
line is invalid and is never made valid.
Note that we don't have to worry about invalidations due to snooped
writes while reloading a line, because the wishbone arbiter won't
switch to another master once it has started sending our reload
requests to memory. Thus a store to memory will either happen before
any of our reads have got to memory, or after we have finished the
reload (in which case we will no longer be in WAIT_ACK state).
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 25 Sep 2021 03:26:09 +0000 (13:26 +1000)]
decode1: Conditional trap instructions don't need to be single-issue
They can generate interrupts, but that doesn't mean they have to
single-issue.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 24 Sep 2021 23:35:01 +0000 (09:35 +1000)]
Merge pull request #330 from antonblanchard/orange-crab-freq
Orange Crab is 48MHz not 50MHz, bump PLL frequency
Anton Blanchard [Fri, 24 Sep 2021 05:30:22 +0000 (15:30 +1000)]
Merge pull request #331 from ozbenh/misc
jtag tooling improvements & gitignore fix
Benjamin Herrenschmidt [Fri, 24 Sep 2021 04:23:06 +0000 (14:23 +1000)]
Add liteeth/build to gitignore
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 24 Sep 2021 04:23:06 +0000 (14:23 +1000)]
mw_debug: Default to jtag backend if unspecified
It avoids typing it all the time
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 24 Sep 2021 04:23:06 +0000 (14:23 +1000)]
mw_debug: Probe cable if unspecified
Instead of defaulting to DigilentHS1
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 24 Sep 2021 04:23:06 +0000 (14:23 +1000)]
flash-arty: Add cable argument
To select the cable config. Defaults to arty
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Fri, 24 Sep 2021 04:19:26 +0000 (14:19 +1000)]
Merge pull request #329 from paulusmack/wb-fix
Wishbone addressing fix
Anton Blanchard [Fri, 24 Sep 2021 02:43:33 +0000 (12:43 +1000)]
Orange Crab is 48MHz not 50MHz, bump PLL frequency
I'm not sure why I set the input frequency for the Orange Crab to 50MHz.
Since we easily make timing now, bump our output frequency to 48MHz as
well.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling [Thu, 16 Sep 2021 06:07:05 +0000 (16:07 +1000)]
Merge pull request #328 from paulusmack/shortmult
core: Add a short multiplier
Michael Neuling [Thu, 16 Sep 2021 05:24:36 +0000 (15:24 +1000)]
Merge pull request #327 from paulusmack/master
loadstore1 timing improvement
Paul Mackerras [Wed, 15 Sep 2021 08:18:09 +0000 (18:18 +1000)]
Make wishbone addresses be in units of doublewords or words
This makes the 64-bit wishbone buses have the address expressed in
units of doublewords (64 bits), and similarly for the 32-bit buses the
address is in units of words (32 bits). This is to comply with the
wishbone spec. Previously the addresses on the wishbone buses were in
units of bytes regardless of the bus data width, which is not correct
and caused problems with interfacing with externally-generated logic.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 11 Sep 2021 07:10:20 +0000 (17:10 +1000)]
core: Add a short multiplier
This adds an optional 16 bit x 16 bit signed multiplier and uses it
for multiply instructions that return the low 64 bits of the product
(mull[dw][o] and mulli, but not maddld) when the operands are both in
the range -2^15 .. 2^15 - 1. The "short" 16-bit multiplier produces
its result combinatorially, so a multiply that uses it executes in one
cycle. This improves the coremark result by about 4%, since coremark
does quite a lot of multiplies and they almost all have operands that
fit into 16 bits.
The presence of the short multiplier is controlled by a generic at the
execute1, SOC, core and top levels. For now, it defaults to off for
all platforms, and can be enabled using the --has_short_mult flag to
fusesoc.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 13 Sep 2021 07:25:52 +0000 (17:25 +1000)]
loadstore1: Make r1.req.addr not depend on l_in.valid
Some critical path reports showed r1.req.addr depending on l_in.valid,
which then depended ultimately on the dcache's r1.ls_valid. In fact
we can update r1.req.addr (and other fields of r1.req, except for
r1.req.valid) independently of l_in.valid as long as busy = 0.
We do also need to preserve r1.req.addr0 when l_in.valid = 0, so we
pull it out of r1.req and store it separately in r1.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Michael Neuling [Mon, 13 Sep 2021 02:11:24 +0000 (12:11 +1000)]
Merge pull request #324 from paulusmack/master
Performance and timing improvements
Paul Mackerras [Tue, 7 Sep 2021 10:38:00 +0000 (20:38 +1000)]
core: Predict not-taken conditional branches using BTC
This adds a bit to the BTC to store whether the corresponding branch
instruction was taken last time it was encountered. That lets us pass
a not-taken prediction down to decode1, which for backwards direct
branches inhibits it from redirecting fetch to the target of the
branch. This increases coremark by about 2%.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 6 Sep 2021 23:32:30 +0000 (09:32 +1000)]
xilinx-mult: Move some registers later in the data flow
This changes s0 to use the P register rather than the A/B/C input
registers, thus improving the timing of the multiplier output. The
m00, m02 and m03 multipliers now use their P registers rather than the
M registers, moving the addition they do from the second cycle to the
first.
Also, the XOR that inverts the 32 LSBs is moved before the output
register.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>