nmigen.git
5 years agobuild.dsl: Add optional name_suffix to Resource.family.
William D. Jones [Wed, 10 Jul 2019 15:29:09 +0000 (11:29 -0400)]
build.dsl: Add optional name_suffix to Resource.family.

5 years agoback.pysim: avoid malformed VCD files when a decoder uses tabs.
whitequark [Wed, 10 Jul 2019 12:54:59 +0000 (12:54 +0000)]
back.pysim: avoid malformed VCD files when a decoder uses tabs.

5 years agohdl.ir: make UnusedElaboratable a real warning.
whitequark [Wed, 10 Jul 2019 12:46:46 +0000 (12:46 +0000)]
hdl.ir: make UnusedElaboratable a real warning.

Before this commit, it was a print statement, and therefore, command
interpreter options like -Wignore did not affect it. There is no API
to access the warning filter list, so it was turned into a real
warning; and further, since Python 3.6, tracemalloc can be used
as a standard method to display traceback to allocation site instead
of the ad-hoc traceback logic that was used in Elaboratable before.

5 years agoback.rtlil: add decodings to cases when switching on a signal.
whitequark [Tue, 9 Jul 2019 19:45:15 +0000 (19:45 +0000)]
back.rtlil: add decodings to cases when switching on a signal.

Fixes #134.

5 years agoback.verilog: run proc_prune for much cleaner output.
whitequark [Tue, 9 Jul 2019 19:28:09 +0000 (19:28 +0000)]
back.verilog: run proc_prune for much cleaner output.

This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@44bcb7a1.

5 years agohdl.{ast,dsl},back.rtlil: track source locations for switch cases.
whitequark [Tue, 9 Jul 2019 19:18:02 +0000 (19:18 +0000)]
hdl.{ast,dsl},back.rtlil: track source locations for switch cases.

This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@93bc5aff.

5 years agotracer: add PyPy support to get_var_name().
Jacob Lifshay [Tue, 9 Jul 2019 07:29:01 +0000 (00:29 -0700)]
tracer: add PyPy support to get_var_name().

Fixes #141.

5 years agobuild.dsl: add Resource.family abstraction.
whitequark [Tue, 9 Jul 2019 02:44:03 +0000 (02:44 +0000)]
build.dsl: add Resource.family abstraction.

5 years agobuild.{dsl,res}: allow platform-dependent attributes using callables.
whitequark [Mon, 8 Jul 2019 11:15:04 +0000 (11:15 +0000)]
build.{dsl,res}: allow platform-dependent attributes using callables.

Fixes #132.

5 years agohdl.rec: respect modifications to signals in Record.like().
whitequark [Mon, 8 Jul 2019 10:59:15 +0000 (10:59 +0000)]
hdl.rec: respect modifications to signals in Record.like().

Fixes #126.

5 years agoback.rtlil: don't name-prefix signals connected to instance ports.
whitequark [Mon, 8 Jul 2019 10:48:07 +0000 (10:48 +0000)]
back.rtlil: don't name-prefix signals connected to instance ports.

This gives particularly pathological results on IO buffers, like:
  connect \D_OUT_0 \user_led_0_user_led_0__o

Since subfragment signals are name-prefixed because this works well
for signals propagated upwards across hierarchy, this is never
desirable for instances.

5 years agobuild.{dsl,res}: allow removing attributes from subsignals.
whitequark [Mon, 8 Jul 2019 10:41:45 +0000 (10:41 +0000)]
build.{dsl,res}: allow removing attributes from subsignals.

This is useful when most attributes in a large composite resource
are the same, but a few signals are different, and also when building
abstractions around resources.

Fixes #128.

5 years agobuild.dsl: allow assertions on subsignal widths.
whitequark [Mon, 8 Jul 2019 10:32:41 +0000 (10:32 +0000)]
build.dsl: allow assertions on subsignal widths.

This is useful when building abstractions around resources where
the pin names are user-specified.

Fixes #129.

5 years agohdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
whitequark [Mon, 8 Jul 2019 10:26:49 +0000 (10:26 +0000)]
hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.

Fixes #125.

5 years agotest: fix Travis.
whitequark [Mon, 8 Jul 2019 10:20:24 +0000 (10:20 +0000)]
test: fix Travis.

5 years agotest: generate examples to verilog as part of unit tests.
whitequark [Mon, 8 Jul 2019 10:12:15 +0000 (10:12 +0000)]
test: generate examples to verilog as part of unit tests.

This is to make sure 806a62c2 doesn't happen again.

5 years agoexamples/basic/ctr_ce: fix outdated syntax.
whitequark [Mon, 8 Jul 2019 10:00:16 +0000 (10:00 +0000)]
examples/basic/ctr_ce: fix outdated syntax.

5 years agocompat.genlib.fsm: fix after commit dac62754.
whitequark [Mon, 8 Jul 2019 10:03:20 +0000 (10:03 +0000)]
compat.genlib.fsm: fix after commit dac62754.

5 years agohdl.xfrm: don't overwrite source locations on ClockDomain signals.
whitequark [Mon, 8 Jul 2019 09:57:14 +0000 (09:57 +0000)]
hdl.xfrm: don't overwrite source locations on ClockDomain signals.

On the sample of examples/basic/*.py, there are no remaining
incorrectly inferred locations.

5 years agohdl.{dsl,mem,xfrm}: inject appropriate source locations.
whitequark [Mon, 8 Jul 2019 09:50:07 +0000 (09:50 +0000)]
hdl.{dsl,mem,xfrm}: inject appropriate source locations.

This primarily fixes the problem with source location precision in
Module (which used to trace locations from __exit__ of the context
managers, by which point everything interesting has been lost), but
also improves memory port and control inserter source locations.

On the sample of examples/basic/*.py, the only incorrectly inferred
remaining location is clk pointing to hdl/mem.py:166.

5 years agoback.rtlil: ignore empty source locations.
whitequark [Mon, 8 Jul 2019 09:33:01 +0000 (09:33 +0000)]
back.rtlil: ignore empty source locations.

This was a bug introduced during refactoring in 2492f490.

5 years agohdl.ast: use keyword-only arguments as appropriate.
whitequark [Mon, 8 Jul 2019 09:23:33 +0000 (09:23 +0000)]
hdl.ast: use keyword-only arguments as appropriate.

As a motivation/related refactor, make sure each AST node exposes
src_loc_at in the constructor.

5 years agoback.rtlil: attach source locations to switches, not processes.
whitequark [Mon, 8 Jul 2019 09:09:40 +0000 (09:09 +0000)]
back.rtlil: attach source locations to switches, not processes.

This effectively reverts and reimplements half of commit 82903e49.
I was confused and did not realize that RTLIL does, in fact, have
attributes on switches.

After this commit, processes no longer have any source locations.
This is semantically fine, as the processes we emit are purely
artificial (because of LHS grouping), but I have not checked how
downstream tooling handles this.

5 years agoback.rtlil: use a more principled approach to attributes. NFC.
whitequark [Mon, 8 Jul 2019 08:57:36 +0000 (08:57 +0000)]
back.rtlil: use a more principled approach to attributes. NFC.

This also refactors the RTLIL builder to use a more aspect-oriented
approach.

5 years agovendor.xilinx_7series: generate also binary bitfile.
Alain Péteut [Sun, 7 Jul 2019 21:36:32 +0000 (23:36 +0200)]
vendor.xilinx_7series: generate also binary bitfile.

Fixes #139.

5 years agovendor.xilinx_spartan_3_6: Add Spartan3A family support.
William D. Jones [Sun, 7 Jul 2019 20:44:48 +0000 (16:44 -0400)]
vendor.xilinx_spartan_3_6: Add Spartan3A family support.

5 years agovendor.lattice_ecp5: don't leave LUT inputs disconnected.
whitequark [Sun, 7 Jul 2019 02:30:56 +0000 (02:30 +0000)]
vendor.lattice_ecp5: don't leave LUT inputs disconnected.

This causes YosysHQ/nextpnr#301.

Fixes #136.

5 years agohdl.dsl: further clarify error message for incorrect nesting.
whitequark [Sun, 7 Jul 2019 01:03:59 +0000 (01:03 +0000)]
hdl.dsl: further clarify error message for incorrect nesting.

Fixes #133.

5 years agohdl.dsl: clarify error message for incorrect nesting.
whitequark [Sun, 7 Jul 2019 00:59:57 +0000 (00:59 +0000)]
hdl.dsl: clarify error message for incorrect nesting.

Refs #133.

5 years agohdl.dsl: gracefully handle FSM with no states.
whitequark [Sun, 7 Jul 2019 00:59:34 +0000 (00:59 +0000)]
hdl.dsl: gracefully handle FSM with no states.

5 years agobuild.plat: source a script with toolchain environment.
whitequark [Sun, 7 Jul 2019 00:41:03 +0000 (00:41 +0000)]
build.plat: source a script with toolchain environment.

Fixes #131.

5 years agobuild.run: only use os.path on the target OS.
whitequark [Sun, 7 Jul 2019 00:18:56 +0000 (00:18 +0000)]
build.run: only use os.path on the target OS.

Before this commit, BuildPlan.add_file would use os.path.normpath,
which would be the wrong thing for cross-builds.

5 years agobuild.run: make BuildProducts abstract, add LocalBuildProducts.
whitequark [Sun, 7 Jul 2019 00:07:55 +0000 (00:07 +0000)]
build.run: make BuildProducts abstract, add LocalBuildProducts.

This makes it clear that we plan to have remote builds as well.

Also, document everything in build.run.

5 years agobuild.plat, vendor.*: don't join strings passed as _opts overrides.
whitequark [Sat, 6 Jul 2019 23:09:46 +0000 (23:09 +0000)]
build.plat, vendor.*: don't join strings passed as _opts overrides.

Right now an array is expected in any _opts overrides, and if it is
actually a string (because it is passed via an environment variable,
usually), awkwardness results as each character is joined with ` `.

Fixes #130.

5 years agobuild.run: make sure BuildProducts._root is not easily accessible.
whitequark [Sat, 6 Jul 2019 18:44:25 +0000 (18:44 +0000)]
build.run: make sure BuildProducts._root is not easily accessible.

5 years agovendor.xilinx_{7series,spartan6}: Support extra VHDL files.
Staf Verhaegen [Thu, 4 Jul 2019 15:13:56 +0000 (17:13 +0200)]
vendor.xilinx_{7series,spartan6}: Support extra VHDL files.

5 years agohdl.dsl: fix src_loc_at for FSM state signal.
whitequark [Wed, 3 Jul 2019 16:34:31 +0000 (16:34 +0000)]
hdl.dsl: fix src_loc_at for FSM state signal.

5 years agoback.rtlil: emit \src attributes for processes via Switch and Assign.
whitequark [Wed, 3 Jul 2019 16:27:54 +0000 (16:27 +0000)]
back.rtlil: emit \src attributes for processes via Switch and Assign.

The locations are unfortunately not very precise, but they provide
some improvement over status quo.

5 years agohdl.ast: fix src_loc_at for Mux().
whitequark [Wed, 3 Jul 2019 15:25:14 +0000 (15:25 +0000)]
hdl.ast: fix src_loc_at for Mux().

5 years agobuild.res: detect physical conflicts earlier.
whitequark [Wed, 3 Jul 2019 15:07:44 +0000 (15:07 +0000)]
build.res: detect physical conflicts earlier.

This is useful for two reasons:
  1. nMigen can provide better error messages than the platform and
     do it earlier in the build pipeline.
  2. Many platforms handle diffpairs by only constraining the P pin;
     the N pin is completely ignored. If this is undetected,
     downstream users (human or software) can rely on this
     information assuming it is correct and introduce more errors.
     (Of course, this will not catch every mistake, but the most
     common is a copy-paste issue, and that will handle it.)

Fixes #124.

5 years agohdl.rec: thread src_loc_at to all inner Signals and Records.
whitequark [Wed, 3 Jul 2019 14:49:20 +0000 (14:49 +0000)]
hdl.rec: thread src_loc_at to all inner Signals and Records.

5 years agovendor: give names to IO buffer instances.
whitequark [Wed, 3 Jul 2019 14:43:03 +0000 (14:43 +0000)]
vendor: give names to IO buffer instances.

Fixes #123.

5 years agohdl.rec: accept Record(src_loc_at=...).
whitequark [Wed, 3 Jul 2019 14:35:48 +0000 (14:35 +0000)]
hdl.rec: accept Record(src_loc_at=...).

5 years agocompat.fhdl.specials: mark CompatMemory as Elaboratable.
whitequark [Wed, 3 Jul 2019 13:28:57 +0000 (13:28 +0000)]
compat.fhdl.specials: mark CompatMemory as Elaboratable.

This suppresses a warning that is not useful in the compat context.

5 years agocompat.fhdl.specials: use "sync" as default domain, not "sys".
whitequark [Wed, 3 Jul 2019 13:25:12 +0000 (13:25 +0000)]
compat.fhdl.specials: use "sync" as default domain, not "sys".

In compat.fhdl.module, we already default to "sync" as the default
clocked domain. Using "sys" in memories only would be inconsistent
and result in more bugs.

5 years agocompat.fhdl.specials: fix Memory.get_port() after 94e8f479.
whitequark [Wed, 3 Jul 2019 13:24:00 +0000 (13:24 +0000)]
compat.fhdl.specials: fix Memory.get_port() after 94e8f479.

This also makes sure the native ports are instantiated for correct
clock domain.

5 years agocompat.fhdl.structure: fix If/Elif/Else after 32446831.
whitequark [Wed, 3 Jul 2019 13:19:15 +0000 (13:19 +0000)]
compat.fhdl.structure: fix If/Elif/Else after 32446831.

5 years agolattice_ecp5: fix get_input
Sebastien Bourdeauducq [Wed, 3 Jul 2019 02:25:32 +0000 (10:25 +0800)]
lattice_ecp5: fix get_input

5 years agohdl.ast: recognize a Enum used as decoder and format it better.
whitequark [Tue, 2 Jul 2019 19:02:16 +0000 (19:02 +0000)]
hdl.ast: recognize a Enum used as decoder and format it better.

5 years agohdl.mem: fix naming of registers inside unnamed memories.
whitequark [Tue, 2 Jul 2019 18:37:02 +0000 (18:37 +0000)]
hdl.mem: fix naming of registers inside unnamed memories.

Before this commit, `None` would leak into the vcd file with pysim.

5 years agobuild.plat: add iter_extra_files method.
Alain Péteut [Tue, 2 Jul 2019 08:44:12 +0000 (10:44 +0200)]
build.plat: add iter_extra_files method.

* vendor.*: employ iter_extra_files.

5 years agoback.rtlil: emit \sig$next wires instead of \$next\sig. NFC.
whitequark [Tue, 2 Jul 2019 18:06:50 +0000 (18:06 +0000)]
back.rtlil: emit \sig$next wires instead of \$next\sig. NFC.

Just a bit more readable.

5 years agoback.rtlil: do not emit $next wires for comb signals.
whitequark [Tue, 2 Jul 2019 18:05:34 +0000 (18:05 +0000)]
back.rtlil: do not emit $next wires for comb signals.

According to RTLIL semantics (that was undocumented before today),
the only purpose of `sync always` is to enable inference of latches,
because there is no other way to express them in terms of RTLIL
processes without ending up with a combinatorial loop. But, nMigen
specifically avoids latches, so this is not necessary.

This change results in major improvements in Verilog readability.

See also #98.

5 years agohdl.rec: implement slicing by component names.
whitequark [Tue, 2 Jul 2019 17:44:55 +0000 (17:44 +0000)]
hdl.rec: implement slicing by component names.

Fixes #121.

5 years agohdl.rec: implement Record.like.
whitequark [Tue, 2 Jul 2019 17:35:00 +0000 (17:35 +0000)]
hdl.rec: implement Record.like.

Fixes #120.

5 years agovendor.xilinx_7series: read extra .xdc files.
Alain Péteut [Tue, 2 Jul 2019 07:47:40 +0000 (09:47 +0200)]
vendor.xilinx_7series: read extra .xdc files.

5 years agohdl.mem: use read_port(domain="comb") for asynchronous read ports.
whitequark [Mon, 1 Jul 2019 19:56:49 +0000 (19:56 +0000)]
hdl.mem: use read_port(domain="comb") for asynchronous read ports.

This avoids the absurdity of the combination of arguments that is
read_port(domain="sync", synchronous=True).

Fixes #116.

5 years agoback.rtlil: fix Array regression in 32446831.
whitequark [Mon, 1 Jul 2019 01:53:56 +0000 (01:53 +0000)]
back.rtlil: fix Array regression in 32446831.

Fixes #117.

5 years agoback.pysim: create unique ResetSynchronizer internal domains.
whitequark [Fri, 28 Jun 2019 08:34:02 +0000 (08:34 +0000)]
back.pysim: create unique ResetSynchronizer internal domains.

Commit 300d47ca introduced the same bug commit 779f3ee9 was trying to
avoid, but now only in the simulator. Since the names in simulator
don't have to make any sense, just use DUID to generate them.

5 years agoback.pysim: override ResetSynchronizer implementation.
whitequark [Fri, 28 Jun 2019 07:49:14 +0000 (07:49 +0000)]
back.pysim: override ResetSynchronizer implementation.

This was rewritten to use Yosys cells in 779f3ee9 to avoid leaking
the interior clock domain, but the simulator doesn't understand Yosys
cells. So, use the old implementation in the simulator.

5 years agolib.cdc: avoid interior clock domains in ResetSynchronizer.
whitequark [Fri, 28 Jun 2019 07:34:10 +0000 (07:34 +0000)]
lib.cdc: avoid interior clock domains in ResetSynchronizer.

Such clock domains will "leak" into the enclosing scope, which is
generally undesirable. Also, this is instructive for a platform
overriding the behavior, since it provides guidance on how to
correctly instantiate platform-specific flops.

I've considered also doing this for MultiReg(), but it is very
challenging in presence of non-reset-less CDC FFs, since Yosys'
$dffsr primitive has separate set and clear inputs, and reshuffling
the reset value for those results in quite a bit of additional logic.

(That said, it might have to be done anyway, precisely because
letting Yosys generate this additional logic might prove too much
for the toolchain to cope with, and again, platform-independent
code should provide guidance to platform-specific code.)

5 years agolib.cdc: eliminate no_retiming attributes.
whitequark [Fri, 28 Jun 2019 07:22:54 +0000 (07:22 +0000)]
lib.cdc: eliminate no_retiming attributes.

See #115 for rationale.

5 years agovendor.lattice_ice40: fix instance of negedge FF due to a typo.
whitequark [Fri, 28 Jun 2019 07:05:10 +0000 (07:05 +0000)]
vendor.lattice_ice40: fix instance of negedge FF due to a typo.

5 years agobuild.plat: fix dedent overrides.
Alain Péteut [Thu, 27 Jun 2019 18:56:37 +0000 (20:56 +0200)]
build.plat: fix dedent overrides.

5 years agoREADME: tone down the instability warning to reflect current status.
whitequark [Fri, 28 Jun 2019 05:10:29 +0000 (05:10 +0000)]
README: tone down the instability warning to reflect current status.

5 years agohdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.
whitequark [Fri, 28 Jun 2019 04:37:08 +0000 (04:37 +0000)]
hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.

This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.

5 years agohdl.ir, back.rtlil: allow specifying attributes on instances.
whitequark [Fri, 28 Jun 2019 04:14:38 +0000 (04:14 +0000)]
hdl.ir, back.rtlil: allow specifying attributes on instances.

Fixes #107.

5 years agoexamples: add concise UART example.
whitequark [Thu, 27 Jun 2019 04:51:45 +0000 (04:51 +0000)]
examples: add concise UART example.

This example uses shift registers and counters instead of an explicit
FSM, which makes it very compact in terms of generated logic, and
more concise too.

5 years agoback.pysim: fix scope screwup.
whitequark [Wed, 26 Jun 2019 05:22:09 +0000 (05:22 +0000)]
back.pysim: fix scope screwup.

5 years agocompat.fhdl.structure: fix typo.
whitequark [Tue, 25 Jun 2019 21:53:08 +0000 (21:53 +0000)]
compat.fhdl.structure: fix typo.

5 years agocompat.fhdl.structure: simplify handling of default case.
whitequark [Tue, 25 Jun 2019 21:52:03 +0000 (21:52 +0000)]
compat.fhdl.structure: simplify handling of default case.

5 years agohdl.{ast,dst}: directly represent RTLIL default case.
whitequark [Tue, 25 Jun 2019 17:53:09 +0000 (17:53 +0000)]
hdl.{ast,dst}: directly represent RTLIL default case.

This makes RTLIL mildly nicer:

 casez ({ \$5 , \$3 , \$1  })
   3'bzz1:
       \$next\o  = \$7 ;
   3'bz1z:
       \$next\o  = \$9 ;
   3'b1zz:
       \$next\o  = \$11 ;
-  3'bz:
+  default:
       { \$next\co , \$next\o  } = \$13 ;
 endcase

5 years agovendor.xilinx_{spartan6,7series}: speedgrade→speed.
whitequark [Tue, 25 Jun 2019 15:51:52 +0000 (15:51 +0000)]
vendor.xilinx_{spartan6,7series}: speedgrade→speed.

For consistency with ECP5.

5 years agovendor.lattice_ecp5: implement.
whitequark [Tue, 25 Jun 2019 15:47:53 +0000 (15:47 +0000)]
vendor.lattice_ecp5: implement.

Note that because of issues with Yosys and nextpnr, it is not yet
possible to use either SDR or DDR I/O.

5 years agoREADME: update nMigen libs paragraph
Sebastien Bourdeauducq [Mon, 24 Jun 2019 02:05:25 +0000 (10:05 +0800)]
README: update nMigen libs paragraph

5 years agoREADME: add clarification about HLS
Sebastien Bourdeauducq [Mon, 24 Jun 2019 02:00:31 +0000 (10:00 +0800)]
README: add clarification about HLS

5 years agovendor.lattice_ice40: use different --package for 4k devices.
whitequark [Wed, 19 Jun 2019 06:09:08 +0000 (06:09 +0000)]
vendor.lattice_ice40: use different --package for 4k devices.

5 years agovendor.xilinx_7series: fix IOB packing.
Jean-François Nguyen [Mon, 17 Jun 2019 18:01:26 +0000 (20:01 +0200)]
vendor.xilinx_7series: fix IOB packing.

5 years agovendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly.
whitequark [Sat, 15 Jun 2019 16:07:40 +0000 (16:07 +0000)]
vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly.

Do this to make sure all buffers, tristate/differential or not, are
instantiated the exact same way, and are subject to the same set of
toolchain bugs, if any.

5 years agovendor.xilinx_{7series,spartan6}: cleanup. NFC.
whitequark [Sat, 15 Jun 2019 16:01:37 +0000 (16:01 +0000)]
vendor.xilinx_{7series,spartan6}: cleanup. NFC.

Eliminate some intermediate signals if they are not necessary.
Do not even return i, o, or t if the pin does not have them.

5 years agovendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly.
whitequark [Sat, 15 Jun 2019 15:55:10 +0000 (15:55 +0000)]
vendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly.

Before this commit, in some cases there will be an inverter, which is
not allowed on an FDCE with IOB attribute set to true, as it will
interfere with packing.

5 years agobuild.plat: dedent overrides.
Alain Péteut [Sun, 16 Jun 2019 12:06:39 +0000 (14:06 +0200)]
build.plat: dedent overrides.

5 years agovendor.lattice_ice40: never place an inverter on global buffer output.
whitequark [Fri, 14 Jun 2019 20:44:02 +0000 (20:44 +0000)]
vendor.lattice_ice40: never place an inverter on global buffer output.

This would make `pin.i` not a global network anymore, which is likely
undesirable if an explicit Attrs(GLOBAL=1) is specified.

5 years agovendor.xilinx_7series: implement inverters.
Jean-François Nguyen [Thu, 13 Jun 2019 12:33:24 +0000 (14:33 +0200)]
vendor.xilinx_7series: implement inverters.

5 years agovendor.xilinx_spartan6: implement DDR I/O buffers and inverters.
Jean-François Nguyen [Wed, 12 Jun 2019 14:56:05 +0000 (16:56 +0200)]
vendor.xilinx_spartan6: implement DDR I/O buffers and inverters.

5 years agocompat.fhdl.structure: fix Case().makedefault().
whitequark [Thu, 13 Jun 2019 03:54:46 +0000 (03:54 +0000)]
compat.fhdl.structure: fix Case().makedefault().

Fixes #100.

5 years agocompat.fhdl.structure: always order default case as the very last.
whitequark [Thu, 13 Jun 2019 03:52:04 +0000 (03:52 +0000)]
compat.fhdl.structure: always order default case as the very last.

5 years agohdl.ast: tighten assertion in Switch().
whitequark [Thu, 13 Jun 2019 03:56:49 +0000 (03:56 +0000)]
hdl.ast: tighten assertion in Switch().

5 years agoSimplify code by using Signal.like(name_suffix="..") appropriately.
whitequark [Wed, 12 Jun 2019 22:28:45 +0000 (22:28 +0000)]
Simplify code by using Signal.like(name_suffix="..") appropriately.

5 years agohdl.ast: add name_suffix=".." option to Signal.like().
whitequark [Wed, 12 Jun 2019 22:21:23 +0000 (22:21 +0000)]
hdl.ast: add name_suffix=".." option to Signal.like().

This simplifies creation of related signals with nice names during
metaprogramming, e.g.

  def make_ff(m, sig):
      sig_ff = Signal.like(sig, name_suffix="_ff")
      m.d.sync += sig_ff.eq(sig)
      return sig_ff

5 years agovendor.xilinx_7series: implement DDR I/O buffers.
Jean-François Nguyen [Tue, 11 Jun 2019 17:57:55 +0000 (19:57 +0200)]
vendor.xilinx_7series: implement DDR I/O buffers.

5 years agovendor.lattice_ice40: fix typo.
whitequark [Wed, 12 Jun 2019 17:38:14 +0000 (17:38 +0000)]
vendor.lattice_ice40: fix typo.

5 years agobuild.{dsl,res,plat}: add PinsN and DiffPairsN.
whitequark [Wed, 12 Jun 2019 14:42:39 +0000 (14:42 +0000)]
build.{dsl,res,plat}: add PinsN and DiffPairsN.

5 years agohdl.ast: implement values with custom lowering.
whitequark [Tue, 11 Jun 2019 07:01:44 +0000 (07:01 +0000)]
hdl.ast: implement values with custom lowering.

5 years agoback.pysim: check for a clock being added twice.
whitequark [Tue, 11 Jun 2019 03:54:22 +0000 (03:54 +0000)]
back.pysim: check for a clock being added twice.

This commit adds a best-effort error for a common mistake of adding
a clock driving the same domain twice, such as a result of
a copy-paste error.

Fixes #27.

5 years agoback.rtlil: mask memory init values.
whitequark [Tue, 11 Jun 2019 03:43:09 +0000 (03:43 +0000)]
back.rtlil: mask memory init values.

This handles both init values that are too wide, which happens if
their magnitude is too high, or if they're negative.

Fixes #96.

5 years agohdl.mem: coerce memory init values to integers.
whitequark [Tue, 11 Jun 2019 03:38:44 +0000 (03:38 +0000)]
hdl.mem: coerce memory init values to integers.

The coercion is carefully chosen to accept (other than normal ints)
instances of e.g. np.int64, but reject instances of e.g. float.
See https://stackoverflow.com/a/48940855/254415 for details.

Fixes #93.

5 years agolib.cdc: fix typo.
Simon Kirkby [Sun, 9 Jun 2019 10:24:01 +0000 (18:24 +0800)]
lib.cdc: fix typo.

5 years agovendor.xilinx_spartan6: implement.
Jean-François Nguyen [Thu, 6 Jun 2019 22:48:51 +0000 (00:48 +0200)]
vendor.xilinx_spartan6: implement.

5 years agovendor.xilinx_7series: fix typos.
Jean-François Nguyen [Thu, 6 Jun 2019 22:54:52 +0000 (00:54 +0200)]
vendor.xilinx_7series: fix typos.