dev-arm: Make CNTFRQ a GenericTimer parameter

This register should be in theory initialized by the highest
priviledged software. We do this in gem5 to avoid KVM
complications (the gem5 firmware won't run at highest EL)

JIRA: https://gem5.atlassian.net/browse/GEM5-611

Change-Id: I62d368105af48584f2fe9671de7c70b484b40c12
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29612
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Update release notes

Change-Id: I3851a3780aae283d4dba5ab5afa20a4a02bc8e6d
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29067
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Fixed null-pointer arithmetic error

Doing arithmetic on a null pointer is undefined behavior in C/C++. Clang
compilers complain when this occurs. As this MACRO is used twice, and
does nothing important, it has been removed in favor of a more simple
solution. A comment has been added explaining the MACRO's removal.

Change-Id: I42d9356179ee0fa5cb20f827af34bb11780ad1a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29534
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute,misc: Removed unused 'vaddr' capture

Clang compilers return a `error: lambda capture 'vaddr' is not used`
error when compiling HSAIL_X86/gem5.opt. This unused lambda capture has
therefore been removed.

Change-Id: I2a7c58174a9ef83435099ab4daf84c762f017dd4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29533
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

mem-ruby,misc: Fixed clang template def error

Without this fix `error: call to function 'operator<<' that is neither
visible in the template definition nor found by argument-dependent
loopup` is thrown  when compiling HSAIL_X86 using a clang compiler (at
`base/cprintf_formats.hhi:139`).

This error is due to a "<<" operator in a template declared prior to its
definition in the code. The operator is used in
`base/cprintf_formats.hh`, included in `base/cprintf.hh`, and defined in
`mem/ruby/common/BoolVec.hh`. Therefore, for clang to compile without
error, `mem/ruby/common/BoolVec.hh` must be included before
`base/cprintf.hh` when generating the
`mem/ruby/protocol/RegionBuffer_Controller.cc` in
`mem/slicc/symbols/StateMachine.py`.

Due to the gem5 style-checker, an overly-verbose solution was required
to permit this patch to be committed to the codebase.

Change-Id: Ie0ae4053e4adc8c4e918e4a714035637925ca104
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29532
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

python,test: Fixed boot test in python3 by removing map

In Python3 `map(lambda c: c.createThreads(), self.cpu)` does not
execute `c.createThreads()`. This has been replaced with a for-loop
which does work. Without this fix, the boot tests do not run in python3.

Change-Id: I50d6c85ec4435ee04e248ea8bc4a3b4cc17c88fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29456
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

scons: "no-defautled-function-deleted" flag moved to only clang8+

It has been onserved that clang does not function with the
"-Wno-defaulted-function-deleted" for versions below clang8.

Change-Id: I6e6d1476350ae2b46b4de971fe3456697b39e43c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29454
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm,misc: Add M5_CLASS_VAR_USED to faultTick

Clang compilers returned an error that faultTick was unused. Adding
M5_CLASS_VAR_USED resolves this.

Change-Id: I97657b45997d2f1c7416b973cd9c02ae2d92b725
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29453
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv,misc: Added M5_VAR_USED to MiscRegNames

Clang compilers return an error about MiscRegNames being unused.
M5_VAR_USED fixes this.

Change-Id: I515c5d1e8837020b674de49039c0525f896b7e37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29452
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons,python: Update makeTheGPUISA to Python3

This function was causing an error to occur when trying to compile HSAIL
and GCN in a Python3 environment. It has now been upgraded to work in
both Python2 and Python3.

Change-Id: If8d6ee1e08c47d5a36182afc10cf86a8e905bda0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29410
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Include eventq_impl.hh in scheduler.hh.

This ensures that we also get the inline definitions of some of the
methods defined in the EventQueue class. In certain circumstances gem5
won't link properly otherwise.

Change-Id: Ie0dfef207a165095bdfe1199cd1f690cebc4cbbf
Issue-on: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-597
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29397
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Disable some warnings in clang.

The defaulted-function-deleted warning triggers in generated code which
would be very tricky to address.

The c99-designator refers to using an array index to specify which
element of an array is being initialized. This makes the code more
clear and is supported by both g++ and clang++. Designated initializers
for structures are being introduced in C++20, but there is no word I
could find on arrays. This warning option seems to only exist in clang
versions 10 and up, so we can only use it on those versions.

Change-Id: I8fb858e643814638c552a49336db2672be8e43c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29396
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

Revert "systemc: Fix clang9 linker error"

This reverts commit 80a263698323852b1951d8d71ca0d599dff7ef3c.

Change-Id: I24c69d1a5a54ac8b8d5713314f6e91e5a6263c26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29395
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,python: Upgrading testlib to function with Python2

Change-Id: I9926b1507e9069ae8564c31bdd377b2b916462a2
Issue-on: https://gem5.atlassian.net/browse/GEM5-395
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29088
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Fix clang9 linker error

Likely a compiler bug, but if this function is allowed to be inlined,
clang9 throws a linker error. Fix this error by making sure the function
isn't inlined.

Change-Id: I4bfade889796915e7bb4b224eafa6e72d4ec59da
Issue-on: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-597
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29394
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fixed spacing issue in ARM_MOESI_hammer

Change-Id: I5e38d1fb0b3c61ae40d26db21b8d20cc3199b391
Jira: https://gem5.atlassian.net/browse/GEM5-594
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29393
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fixed issue building ARM_MESI_Three_Level

Change-Id: I1ef200cd282e189d142a5902b6ddbd33119c4173
Jira: https://gem5.atlassian.net/browse/GEM5-594
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29352
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Remove GCN3 as a build target

This target currently doesn't compile, so remove it from the list of
supported ISAs for the gem5-20 release. We can add this target back
after the compilation errors have been fixed.

Change-Id: I2b121824fcfee59b62d7d24600ddd0eece884c6b
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29392
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Fixed HSAIL_X86 compilation errors

HSAIL_X86 fail to compile. This patch enables compilation.

Issue-on: https://gem5.atlassian.net/browse/GEM5-556

Change-Id: I663e529622ed90254eaf8be01e23991ed8271b5b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29293
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Update memory tests to be compatible with python3

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I9bb7444c62e6b29e9c91dbf30320a38718f08b8c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29353
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Change m5's tick mechanism of rounding non intergral ticks

This commit changes m5's tick rounding mechanism from python's round()
to python's ceil() function.

Currently, non intergral ticks are rounded by round() function in python.
In python2, this function rounds values >= 0.5 to 1. However, in python3,
0.5 is rounded to 0. This causes the function to return 0 ticks for
non-zero second values, which doesn't make sense, and also causes
several tests to fail.

ceil() function is now used to round up the tick values. This makes more
sense as non-zero second values won't be rounded to zero in any cases.

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I14c43e38e8c678f77baf13407f7eeff4b86f1014
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29372
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Added M5_CLASS_VAR_USED to m_id in OutputUnit

Clang 9 throws an error that 'm_id' is unused (encountered when
compiling X86.fast). M5_CLASS_VAR_USED has been added to avoid this
error.

Change-Id: I722edd1429a074ff484b5ebbdc431af0089561b5
Issue-on: https://gem5.atlassian.net/browse/GEM5-560
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29304
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc,sim: Tagged API methods in sim/simobject.hh

Change-Id: I1d4f5b67828e3bef64d781831cec4b25d6fcb6b9
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28407
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc,base,stats: Tagged API methods in base/stats/group.hh

Change-Id: I61693884d719025f3b1f385793c7a71de0937e79
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28390
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Added src/doxygen/html to .gitignore

Previously `src/doxygen` was ignored, but `src/doxygen` contains some
"source" for creating the doxygen html. Therefore this .gitignore entry
has been removed and replaced with one that only ignores the generated
`src/doxygen/html`.

Change-Id: I5add9fe839a00ad9d216d2082beda637ad0ea87d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28389
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc,sim: Tagged API methods and variables in eventq.hh

Change-Id: I76018d4aa08f9bd42a152ec7e0222a0385d3b895
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28388
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc,sim: Tagged API methods in sim/serialize.hh

Within this some light refactoring has been carried out to avoid
accessing member variable directly and removing some unused/unneeded
ones from the codebase.

Change-Id: I458494f6466628b213816c81f6a8ce42fb91dc3f
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27989
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Tagged API methods in sim/drain.hh

Change-Id: Id584d0be027048064d5f650ae0f2ea5a7f075a47
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27988
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Revert LTO and partial linking for gcc >=8.1

This reverts commit f41abbdb5cf5c67233f3d730885d43517969afda,
"scons: Enable LTO and partial linking with gcc >= 8.1."

LTO and partial linking does not work on GCC 9.3 on Ubuntu 20.04 when
compiling gem5.fast. This error was exposed via the following command:

```
docker run -u $UID:$GID --volume $(pwd):/gem5 -w /gem5 --rm \
gcr.io/gem5-test/ubuntu-20.04_all-dependencies:latest scons \
build/MIPS/gem5.fast
```

The following error was received:

```
usr/bin/ld: cannot find lib.fo.partial.lto.o: No such file or directory
/usr/bin/ld: error: could not unlink output file
collect2: error: ld returned 1 exit status
scons: *** [build/MIPS/mem/ruby/system/lib.fo.partial] Error 1
```

Issue-on: https://gem5.atlassian.net/browse/GEM5-555
          https://gem5.atlassian.net/browse/GEM5-557
Change-Id: Id9e7fc81aec9f94524acc92c05aabdf96bd284cd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29272
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc,sim: Fixed std::array bracket compiler error

For versions of Clang before 6.0, Clang returns an error if and
std::array initialization is not encompassed in two sets of
encompassing braces. This is a known compiler bug:
https://bugs.llvm.org/show_bug.cgi?id=21629.

As we support Clang 3.9 onwards, we are required to include these
redundant braces to ensure compilation. They do not produce any
ill-effects when using later clang compilers or with any GCC compiler
gem5 presently supports.

Change-Id: Ia512a9b9f583b1cfa28f9fc4c24f6e202e46b4cb
Issue-on: https://gem5.atlassian.net/browse/GEM5-563
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29294
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Updates for python3

Change-Id: Iab2f83716ea2cb19f06282f037314f2db843327a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29047
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

misc: Update Garnet_standalone build opts

Previously, this used the ALPHA ISA which has been removed.

According to the documentation on the website
(https://www.gem5.org/documentation/general_docs/ruby/
garnet_synthetic_traffic/), using null ISA with no CPUs should be safe.

Change-Id: I7fc55df7217887d21f4832f33b8cbb2de3498253
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29087
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Stop setting the physical address in finalizePhysical.

The physical address has already been set (it's read earlier in the
function), and so doesn't need to be set again. Reading the virtual
address can cause an assert if the virtual address had never been set in
the first place, for example when an access comes from KVM which might
give you an access to complete which is based on a physical address
only.

Change-Id: Ic46a40b1a94235538b5bd53065e5019273b3d3f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29172
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Added 'python3-config' to the config list

Previously scons looked for 'python-config' and 'python2-config'. This
caused an error in Python3-exclusive environments. With only python3
installed, 'python3-config' is now an option. With this setup,
'python2-config' is used by default, unless overridden by the user
via the scons command line.

Change-Id: I11186328b0eb0825cc53c3889b31a5345a7f40d1
Issue-on: https://gem5.atlassian.net/browse/GEM5-275
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28648
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Update style file->open for python3

Change-Id: Ibcce194b1905f0e7f29aa91fd0ff881ba879ad51
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29068
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

misc: Add Arm contributions to gem5-20 RELEASE-NOTES.md

* Arm architectural extensions
* Arm TFA support
* DRAM changes

Change-Id: I434c501ee8413c8cd64af25c2c18eabf45e3ee77
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28908
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Set a physical address for local accesses.

This avoids problems when other parts of the simulator blindly try to
retrieve the physical address.

Change-Id: Ia13a2b85b9f919e1e81a6a0f67d10858e98244e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28987
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Fixes for mremap

Remapping memory was trying to map old pages to the same new page and
calling MemState mapRegion unnecessarily. Properly increment the new
page address and remove the redundant mapRegion as remapRegion covers
its functionality.

JIRA: https://gem5.atlassian.net/browse/GEM5-475
Change-Id: Ie360755cfe488b09cbd87cd0ce525b11ac446b51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28948
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Get gem5 to build with Clang 8

Added missing overrides:
- src/mem/token_port.hh
- src/sim/power/mathexpr_powermodel.hh

Remove Unused static constants:
- src/arch/x86/process.cc

Related Issue: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-534

Change-Id: Icc725e2522dcee919e299f4ea7a9f1773f5dfa4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28947
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added missing optional dependencies to 18.04 Docker

Change-Id: Ibc43664f99ce9fbd28d14352243fb17b7754289b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28892
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added python-six as a dependency in 18.04 docker

Previously the docker utilized Python-Pip. This is an intermediate
dependency we don't need. We can install the Python-six module directly
via the APT framework.

Change-Id: I30e3e1cdca802ca19422140f39af7dc9dc166ed7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28891
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Removed python3 Dockerfile

This was previously used to test gem5 being compiled and run in a
Python3 environment. This is redundant with the introduction of
"util/dockerfiles/ubuntu-20.04_all-dependencies", which uses python3
exclusively.

Change-Id: Ie837da338c3985ba92aff84144948a23fd6ece3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28890
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added Dockerfile for Ubuntu 20.04

This Dockerfile creates an image which simulates an Ubuntu 20.04
environment. Unlike the Ubuntu 18.04 Dockerfile, this does not use
Python2. It uses exclusively Python3. Ubuntu 20.04 has Python3 installed
by default. The image this Dockerfile creates can be obtained from
"gcr.io/gem5-test/ubuntu-20.04_all-dependencies". To pull:

docker pull gcr.io/gem5-test/ubuntu-20.04_all-dependencies

Change-Id: I73b51028e0d6a3198aa6e7b1906d20ed6eb6c815
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28889
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Update python-config flags for python3.8

Starting in python 3.8 the python3-config utility requires the --embed
flag to output -lpython3.8. Without this flag, gem5 won't link to the
python library.

More details: https://bugs.python.org/issue36721
https://github.com/python/cpython/pull/13500

Change-Id: Id9c63577dcd2defa7ae62cc32e042c4a245e7082
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28687
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Add readCommandWithReturn helper

In this way it will be possible to reliably catch any error
in the command execution which is not raising an exception
to Popen.

Change-Id: I4dc15648423f9bb8e8a470d97291dbd065c48eba
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28847
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv,tests: small update to make gem5.fast compile

This small change is meant to enable gem5.fast compilation
for riscv. Also, the riscv tests based on gem5.fast
work now and are removed from .testignore.

Change-Id: Id9c96d8e4682a74ec1d77a66eae53d6f9b64d302
Issue-On: https://gem5.atlassian.net/browse/GEM5-526
Issue-On: https://gem5.atlassian.net/browse/GEM5-527
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28893
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Defer deletion of respQueue.front() in DRAMCtrl

The front() of respQueue was being deleted before the last usuage of
dram_pkt (which points to the same object) causing random crashes.

Change-Id: I89862d10599dc0d1a50717dac8ed9298b4d74a3d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28808
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updated resources bucket url to version 20

This will fix this v20.0.0.0 of gem5 to the v20 gem5 resources bucket
subdirectory.

Change-Id: I0c1f1a2c28c18e684bcb009d1650f9e9d2950a93
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28708
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updated version to 20.0.0.0

Change-Id: I5ba4a6e728b2daccea898685d3c27b0f7c7a02cd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28707
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: MESI_Two_Level missing function compilation fix

The recent commit dd6cd33 removed the Ruby Sequencer function
invalidateSC in favour of doing this implicitely via
evictionCallback. The protocol MESI_Two_Level still contains one
explicit call to this function, however, this is now superflous
as forward_eviction_to_cpu is called in the same transition. This
patch removes the remaining calls to invalidateSC.

JIRA: https://gem5.atlassian.net/browse/GEM5-499

Change-Id: If51d8bebf6aa39d20789639aab0d262d5173ca59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28747
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: MOESI_CMP_directory sync fix

The recent commit dd6cd33 modified the behaviour of the the Ruby
sequencer to handle load linked requests as loads rather than
stores. This caused the regression test
realview-simple-timing-dual-ruby-ARM-x86_64-opt
to become stuck when booting Linux. This patch fixes the issue by
adding a missing forward_eviction_to_cpu action to the state
transition(OM, Fwd_GETX, IM).

Change-Id: I8f253c5709488b07ddc5143a15eda406e31f3cc6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28787
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base,sim: allow m5writeFile with stdout/stderr.

If m5writeFile opens stdout/stderr, no file is registered in
OutputDirectory and thus we don't want to search for it on close.

In order to write multiple times to stdout/stderr in a reasonable way,
we also want to prevent seeking. Thus, don't seek if the offset is 0, in
which case this would be a noop anyway (we just opened the file without
append).

Finally, it is helpful for debugging if the stream is flushed on every
write.

Change-Id: I102f82dcd2c63420b6f3fe55d67f03c62349e69d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28727
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Remove old boot files

Most of these "rcS" scripts are only useful for specific disk images
that have long been lost to the gem5 community. This commit deletes all
of these scripts. It keeps the generally useful hack_back_cktp script
and the bbench scripts that work with the android images that are still
available.

In the future, these remaning scripts should be moved to the gem5
resources repository.

Issue-on: https://gem5.atlassian.net/browse/GEM5-350
Change-Id: Iba99e70fde7f656e968b4ecd95663275bd38fd6e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28507
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher

A recent change (https://gem5-review.googlesource.com/c/
public/gem5/+/27949) updated the ruby prefetcher name,
which breaks the use of old name in some SLICC files.
This change makes sure that the new name is used at all
places.

Issue-On: https://gem5.atlassian.net/browse/GEM5-498
Change-Id: Ic667b61eac13dc7c267cee7dce3aa970f7ae9a8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28667
Reviewed-by: Timothy Hayes <timothy.hayes@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Manually convert float to int when using %x

This is required by python3.5 which is not allowing a
floating point value to be printed in hex and will trigger
a TypeError assertion:

TypeError: %X format: an integer is required, not float

Change-Id: I2033366751924579cc87e7fccda8fdb33a31412d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28607
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Make cpt_upgraders python3 compatible

It won't be possible to build gem5 in a python3 only environment
otherwise since the cpt_upgrader.py script is automatically run at the
end of compilation

Change-Id: Iea4217e5cd64ca44b99aa0db5dabfdced7aeb3ea
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28587
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Port git hooks to python3

This involves changing:
* git-commit
* git-pre-commit
* style verifiers

JIRA: https://gem5.atlassian.net/browse/GEM5-473

Change-Id: I7bd0b54469f942bf927c8be1fd94d12f67594d48
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28588
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: MESI_Three_level prefetcher page crossing

This patch allows MESI_Three_level using the Ruby prefetcher to
safely cross page boundaries by determining if an address is bad
and cannot be mapped to a memory controller.

Change-Id: I675a13dfa6deb5b6a9f986ced5a3130436db911d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28048
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: MESI_Three_level prefetcher support

Add support for the Ruby stride prefetcher to MESI_Three_Level.

Change-Id: Id68935e2a7d3ccd0e22a59f43a15f167410632a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27715
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: MESI_Three_Level LL/SC improvements

This patch fixes the MESI_Three_Level protocols so that it correctly
informers the Ruby sequencer when a line eviction occurs. Furthermore,
the patch allows the protocol to recognize the 'Store_Conditional'
RubyRequestType and shortcuts this operation if the monitored line
has been cleared from the address monitor. This prevents certain
livelock behaviour in which a line could ping-pong between competing
cores.

The patch establishes a new C/C++ preprocessor definition which allows
the Sequencer to send the 'Store_Conditional' RubyRequestType to
MESI_Three_Level instead of 'ST'. This is a temporary measure until
the other protocols explicitely recognize 'Store_Conditional'.

Change-Id: I27ae041ab0e015a4f54f20df666f9c4873c7583d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28328
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: LL/SC fixes

The implementation for load-linked/store-conditional did not work
correctly for multi-core simulations. Since load-links were treated as
stores, it was not possible for a line to have multiple readers which
often resulted in livelock when using these instructions to implemented
mutexes. This improved implementation treats load-linked instructions
similarly to loads but locks the line after a copy has been fetched
locally. Writes to a monitored address ensure the 'linked' property is
blown away and any subsequent store-conditional will fail.

Change-Id: I19bd74459e26732c92c8b594901936e6439fb073
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27103
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add support for multiple call types in the m5 utility.

Using mechanisms added in previous CLs, this change modifies the m5
utility so that it can use any of the back ends enabled and implemented
by each variant, defaulting to one particular implementation if not is
selected explicitly.

On x86, the default mechanism is the magic address. All other variants
default to the magic instruction since they don't have a well
established address to use or even in most cases an implementation to
use.

The ability to override the particular magic address the utility wants
to use (necessary on variants such as aarch64) will be added in a future
CL.

Change-Id: I5fc414740e30759e7dde719cddcc8d5d41f8cc74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27242
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: added news on RISC-V to RELEASE-NOTES.md.

Change-Id: I9b60cd2f533e6d4ce677e8a9b7bb5a5698e51c61
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28448
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: be prepared for CSR changes during PT walk.

If the address space is changed (by writing to SATP), it can happen that
a page table walk is in progress. Previously, this failed if the ASID
changed, because we then used the wrong ASID for the lookup.

This commit makes sure that we don't access CSRs after the beginning of
the walk by loading SATP, STATUS, and PRV at the beginning.

Change-Id: I8c184c7ae7dd44d78e881bb5ec8d430dd480849c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28447
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: fix MESI_Three_Level erroneous transition

The MESI_Three_Level protocol includes a transition in its L1
definition to invalidate an SM state but this transition does
not notify the L0 cache. The unintended side effect of this
allows stale values to be read by the L0 cache. This can cause
incorrect behaviour when executing LL/SC based mutexes. This
patch ensures that all invalidates to SM states are exposed to
the L0 cache.

Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28047
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Update tests to save output on failure

The previous commit which tried to do this, did not work with parallel
execution. In this case, the fixtures that were modified were in the
child process and the parent process's fixtures were never updated.
Instead of modifying the object, use the information passed in from the
testlib.

See 4c28149ffa5d09e6fe14952dcaf8df5d0cd8f328
Previous review:
https://gem5-review.googlesource.com/c/public/gem5/+/17451

Change-Id: Ib4c06c5e3f82994199d6f0c1fa69452e93444d75
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19529
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Fix tmpfiles in testlib

Previously, the testlib would generate and not clean up 100s of
temporary files in /tmp. This puts all of the tempfiles in the same
directory to make sure they are cleaned up on a successful test.

Change-Id: If4dcd93ab4b5df556c046753266a71365d1388c1
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19528
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Build the marshal binary in a bare minimum environment

This change adds an additional bare minimum environment that includes
python only and changes the marshal binary to compile using it.

Change-Id: Id5d1ee6899796d746d8dc1a004cfe4795f040c55
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28428
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: update linux boot tests

This change updates the config scripts used by linux boot
tests to make them compatible with change that deprecated
LinuxX86System

JIRA: https://gem5.atlassian.net/browse/GEM5-440

Change-Id: I04beff2915c03a2c3a774351edbba60d7ff26867
Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28427
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Use AssociativeSet in Stride prefetcher

Avoid replicating associative set functionality in Stride prefetcher's
pc tables.

The indexing policy used previously had some peculiarities, so both
the extractTag and extractSet have been made virtual so that previous
behavior could be kept.

Change-Id: I19a86cb3c4b40031fef427d5f7eed9d5c5673a44
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24603
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Use SatCounter in Stride prefetcher

There is no need to reimplement saturating counter functionality.

Change-Id: Ie7753089873f41a378ab88fd5f095302c3428797
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24542
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Cleanup of SBOOE prefetcher

Made the latencyBuffer a CircularQueue.

Improved encapsulation of the Sandbox struct.

Fixed score() to follow function declaration guidelines.

Removed redundant fatal error checking for score threshold.

Change-Id: I1904884e96f103c67930abafc28b75796aadc406
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24541
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Use CircularQueue in PIF prefetcher

Use CircularQueue for PIF's history buffer, and change the indexing
storage to a CQ iterator.

Change-Id: I75bbb75a6be41bd063f662baedbd4c9de33644de
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24540
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Use CircularQueue for the STeMS's RMOB

Replace rmobHead functionality with a CircularQueue. As a side
effect, RMOB entry's valid bit was removed.

Change-Id: If0b39cfe15de1e47dde0689a0ebc46b623ec1e55
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24539
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix DCPT with CircularQueue

This patch fixes the following bugs:

- Previously when deltaPointer was 0 or 1, getting the last or penultimate deltas
  would be wrong for non-pow2 deltas.size(). For example, if the last added delta
  was to position 0, the previous should be in position 19, if deltas.size() = 20.
  However, 0-1=4294967295, and 4294967295%20=15.

- When searching for the previous late and penultimate, the oldest entry was being
  skipped.

Change-Id: Id800b60b77531ac4c2920bb90c15cc8cebb137a9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24538
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Don't assert on branch target addresses

We should assume a branch target can be any address.

JIRA: https://gem5.atlassian.net/browse/GEM5-483

Change-Id: I6f6da1f9260d6e8978536967dc7fcf1808965db2
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Signed-off-by: Howard Wang <Howard.Wang@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28347
Reviewed-by: Trivikram Reddy <tvreddy@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added RELEASE-NOTES.md

These release notes will enable users to keep track of the main changes
between gem5 versions. The RELEASE-NOTES.md should also notify the user
of any API changes they should be aware of when using this release of
gem5.

Notes on major changes should be apended to the end of the list as
they are added to the repo.

Change-Id: If75748306a8086b2abbe2f912dbb2ec9f1a6895f
Issue-on: https://gem5.atlassian.net/browse/GEM5-439
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27807
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Fix compareVersions for python 3.

When the internal utility function make_version_list sees a string, it
tries to convert it into a list using the map() function. In python 3,
that returns an iterator. The following call to zip() will consume those
iterators, and then the following calls to len() will die because they
don't work on map iterators.

This is only a problem if all the common components of the version lists
are equal, and the comparison needs to then check if one of the lists
was equal to the other but with more components. When versions are
equal, for instance when compiling with the oldest supported version of
gcc (4.8.0) this error surfaces and breaks our scons build.

A simple fix is to just wrap the call to map() with list() to convert
the iterator to a flat list, making the other logic work as before.

Change-Id: If9dc5cd7fff70c21229ac3dd9a017edeccd26148
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28309
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix priority of multi compressor

The priority queue comparator orders such that false gives the
entry a higher priority. Therefore, if it is desired to make
the entry with lowest decompression latency have higher priority,
the comparison must be inverted.

Can be tested with:
  MultiCompressor(compressors=[
    PerfectCompressor(decompression_latency=1),
    PerfectCompressor(decompression_latency=2)])

Where it is expected that compressor0 (the one with decomp lat
of 1) is always chosen.

Change-Id: I44acbf5f51c6e47efdd2a16fba9596935cf2eb69
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28367
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Token port implementation

Adds a TokenPort which uses tokens for flow control rather than the
standard retry mechanism in gem5. The port is intended to be used
for flow control where speculatively sending packets is not possible.
For example, GPU instructions require this to send memory requests
to the cache coalescer.

Change-Id: Id0d55ab65b7c773e97752b8514a780cdf7d88707
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27428
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Add build opts for GCN3 GPU ISA

Change-Id: I5f2662fe72d876b7bf816b0353aaefb85fc6c1c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28130
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: add option to set the timeouts for the TCPs and SQCs

Change-Id: Icff2bd0237ddcc0d21db17208df8e53ff6f43e86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28129
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-hsa: Add HSA device and HSA packet processor

This change adds support for HSA devices, which are
DMA devices that have an HSA packet processor (HSAPP).

An HSA packet processor model is also included. The
HSAPP is a DMA device that matains AQL packet queues
and handles extraction of AQL packets, scheduling
of AQL queues, and initiates kernel launch for HSA
devices.

Because these devices directly interact with low-level
software and aid in the implementation of the HSA ABI
we also include some headers from the ROCm runtime:
the hsa.h and kfd_ioctl.h headers. These aid with
support ROCm for the HSA devices and drivers.

Change-Id: I24305e0337edc6fa555d436697b4e607a1e097d5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28128
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Add files for arch gcn3 (GPU machine ISA)

Decoder: gpu_decoder.hh and decoder.cc:
    The decoder is defined in these files. The decoder
    is implemented as a lookup table of function pointers
    where each decode function will decode to a unique
    ISA instruction, or do some sub-decoding to infer
    the next decode function to call.

    The format for each OP encoding is defined in the
    header file.

Registers:
    registers.[hh|cc] define the special registers and
    operand selector values, which are used to map
    operands to registers/special values. many
    convenience functions are also provides to determine
    the source/type of an operand, for example vector
    vs. scalar, register operand vs. constant, etc.

GPU ISA:
    Some special GPU ISA state is maintained in gpu_isa.hh
    and isa.cc. This class is used to hold some special
    registers and values that can be used as operands
    by ISA instructions. Eventually more ISA-specific
    state should be moved here, and out of the WF class.

Vector Operands:
    The operands for GCN3 instructions are defined in
    operand.hh. This file defines both scalar and
    vector operands wth GCN3 specific semantics. The
    vector operand class is desgned around the generic
    vec_reg.hh that is already present in gem5.

Instructions:
    The GCN3 instructions are defined and implemented
    throughout gpu_static_inst.[hh|cc], instructions.[hh|cc],
    op_encodings.[hh|cc], and inst_util.hh. GCN3 instructions
    all fall under one of the OP encoding types; for example
    scalar memory operands are of the type SMEM, vector
    ALU instructions can be VOP3, VOP2, etc. The base code
    common to all instructions of a certain OP encoding type
    is implemented in the OP encodings files, which includes
    operand information, disassembly methods, encoding type,
    etc.

    Each individual ISA isntruction is implemented as
    a class object in instructions.[hh|cc] and are derived
    from one of the OP encoding types. The instructions.cc
    file is primarily for the execute() methods of each
    individual instruction, and the header file provides
    the class definition and a few instruction specific
    API calls.

    Note that these instruction classes were auto-generated
    but not using the gem5 ISA description language. A
    custom ISA description was used and that cannot be released
    publicly, therefore we are providing them already in C++.

Change-Id: I14d2a02d6b87109f41341c8f50a69a2cca9f3d14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28127
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Inheritance fixes in varargs

Change-Id: I3c6027223893363df098d1990a4ad3d07c2ff5ff
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28250
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Avoid const from member due to &Message::operator=(...)

Change-Id: I172f48ce8ee4a3870165309342dadc2ac39ded9a
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28249
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix access modifier in Arm*ProcessBits class

Change-Id: Ie983abc94dd9e62bbec3f584b70b0d04d6e8305d
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28248
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Disable unsupported -Wl,--as-needed in MacOS

Change-Id: Id6f8199b818217c4fcf4b80efdb7cc9e1d14e32b
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28173
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix inconsistency in variable name

Change-Id: I091a2d0cc8bfa7b8d98c4f508d175868d0fd7249
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28172
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Removed the unused parameter m_id from VirtualChannel

Change-Id: Ie6f8db9b1cb0d0e0ca694c631c6662413fd833c1
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28171
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix function signature inconsistencies in semihosting

Change-Id: Icb1aa30cb67b676d49681f68e1d62b3af409e26b
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28170
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Fix mismatch between #ifndef and #define in varargs.hh

Change-Id: I558b6c3c69a5003a77cc95b414e620715c3dbbae
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28169
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm, mem-ruby, sim: Add missing overrides

Change-Id: I5ab18960bd61953e68777746426adb657818f825
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28168
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Downgrade constexpr causing build errors to const

Change-Id: Idf5ae62603b6181d44aaaef91b774fa7b26eb718
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28167
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add an option to suppress the return value in invokeSimcall.

Sometimes when using the GuestABI mechanism, gem5 wants to know that a
function was called and with what arguments to do its own processing,
but doesn't want to return its own value since it will still let the
simulated system execute its own function. There are also situations
where gem5 wants to return a value, but not through the normal
mechanism. That happens when, for instance, a gem5 op is triggered by a
memory access, and that access is what should return the value, not a
particular fixed register.

This option is a template parameter rather than a function argument so
that if it's not going to be used, no "Return" type needs to be defined
since it's not present at all in the chain of functions invokeSimcall
expands to.

This will also make it easier to reuse generic ABIs in those situations
without having to make custom wrappers.

Change-Id: I969e78495c8f4e73f4de1a3dfb4d74c9b30f5af5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28288
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Use the protobuf version to choose between ByteSize(Long).

Older versions of protobuf are apparently still what's provided with
some current versions of some distributions. To avoid breaking the build
on those distributions and to avoid an annoying deprecation warning on
newer systems, check GOOGLE_PROTOBUF_VERSION to choose which to use.

According to the CHANGES.txt file here:

https://github.com/protocolbuffers/protobuf/blob/master/CHANGES.txt

The new ByteSizeLong function was introduced in version 3.1.0 in 2016.

Change-Id: I7f8eeda144bf9556d17d7a0a741996f3137b48b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28287
Reviewed-by: Tommaso Marinelli <tommarin@ucm.es>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-power: Addition of PowerDomains

PowerDomains group multiple objects together to regulate their power
state. There are 2 types of objects in a PowerDomain: leaders and
followers. The power state of a PowerDomain is the most performant
power state of any of the leaders. The power state of the followers is
determined by the power state of the PowerDomain they belong to: they
need to be in a power state which is more or equally performant to the
power state of the PowerDomain.

Leaders can be ClockedObjects or other PowerDomains. Followers can
only be ClockedObjects. PowerDomains can be be nested but a
PowerDomain can only be a leader of another PowerDomain, NOT a
follower. PowerDomains are not present in the hierarchy by default,
the user needs to create and configure them in the configuration file.

The user can add an hierachy by setting the led_by parameter. gem5
will then create leaders and followers for each domain and calculate
the allowed power states for the domain.

Objects in a PowerDomain need to have at least the ON state in the
possible_states.

An example of a powerDomain config is:

pd = PowerDomain()
cpu0 = BaseCPU()
cpu1 = BaseCPU()
shared_cache = BaseCache()
cache.power_state.led_by = pd
pd.led_by = [cpu0, cpu1]

This will create a PowerDomain, where the CPUs determine their own
power states and the shared cache (via the PowerDomain) follows those
power states (when possible).

Change-Id: I4c4cd01f06d45476c6e0fb2afeb778613733e2ff
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28051
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-power: Specify the states a PowerState object can be in

This commit adds the concept of possible power states to the
PowerState SimObject. This is a list of the power states a specific
object can be in. Before transitioning to a power state, a PowerState
object will first check if the requested power states is actually an
allowed state. The user can restricted the power states a
ClockedObject can go to during configuration. In addition, this change
sets the power states, a CPU can be in.

Change-Id: Ida414a87554a14f09767a272b54b5d19bfc8e911
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28050
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-power: Creation of PowerState class

This commit does not make any functional changes but just rearranges
the existing code with regard to the power states. Previously, all
code regarding power states was in the ClockedObjects. However, it
seems more logical and cleaner to move this code into a separate
class, called PowerState. The PowerState is a now SimObject. Every
ClockedObject has a PowerState but this patch also allows for objects
with PowerState which are not ClockedObjects.

Change-Id: Id2db86dc14f140dc9d0912a8a7de237b9df9120d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28049
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Change fs_power.py to use absolute paths for stats

fs_power.py is an example script that demonstrates how power models
can be used with gem5. Previously, the formulas used to calculate the
dynamic and static power of the cores and the L2 cache were using
stats in equations as determined by their path relative to the
SimObject where the power model is attached to or full paths. This CL
changes these formulas to refer to the stats only by their full paths.

Change-Id: I91ea16c88c6a884fce90fd4cd2dfabcba4a1326c
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27893
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>