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Andrew Waterman [Mon, 23 Aug 2010 05:13:51 +0000 (22:13 -0700)]
[xcc,sim] added fused multiply-add and its cousins
Andrew Waterman [Mon, 23 Aug 2010 04:25:59 +0000 (21:25 -0700)]
[xcc,sim] Eliminated slori instruction
the "li" macro in RISC-V assembly isn't as efficient anymore for 64b
constants, and "la" doesn't work for 64b addresses with ".set noat".
But it's worth it to remove an ugly instruction.
Andrew Waterman [Thu, 19 Aug 2010 01:24:55 +0000 (18:24 -0700)]
[pk,fesvr] improved proxykernel build system
Now uses a modified MCPPBS. Add --host=riscv to configure path.
Front-end server now just searches PATH for riscv-pk, so just install the pk
to somewhere in your path.
Andrew Waterman [Wed, 18 Aug 2010 21:34:42 +0000 (14:34 -0700)]
[sim] integrated SoftFloat-3 with ISA sim; removed SoftFloat-2b
Andrew Waterman [Wed, 18 Aug 2010 00:46:52 +0000 (17:46 -0700)]
[sim] specialized softfloat for riscv
Andrew Waterman [Wed, 18 Aug 2010 00:34:14 +0000 (17:34 -0700)]
[sim] added riscv folder to softfloat
Andrew Waterman [Wed, 18 Aug 2010 00:10:28 +0000 (17:10 -0700)]
[sim] added SoftFloat-3 source
Andrew Waterman [Tue, 10 Aug 2010 03:51:44 +0000 (20:51 -0700)]
[xcc,sim] implement FP using softfloat
The intersection of the Hauser FP and MIPS FP is implemented.
Andrew Waterman [Tue, 10 Aug 2010 00:04:30 +0000 (17:04 -0700)]
[sim] removed unused elf loader
Andrew Waterman [Mon, 9 Aug 2010 23:59:14 +0000 (16:59 -0700)]
[sim] added softfloat
Andrew Waterman [Fri, 6 Aug 2010 00:59:34 +0000 (17:59 -0700)]
[sim,xcc] Added first few Hauser FP insns (sign-injection)
Also updated FPmove test case to test negation and moving between FP regs
Andrew Waterman [Thu, 5 Aug 2010 03:28:47 +0000 (20:28 -0700)]
[sim] Bug fixes in shifts, plus a new test case
Andrew Waterman [Thu, 5 Aug 2010 01:31:04 +0000 (18:31 -0700)]
[xcc] Removed ctc1, cfc1 instructions; added fp move test case
Andrew Waterman [Thu, 5 Aug 2010 00:04:24 +0000 (17:04 -0700)]
[xcc,pk,sim] Added first part of FP support
In particular, FP loads, stores, and moves now work.
Andrew Waterman [Wed, 4 Aug 2010 04:09:14 +0000 (21:09 -0700)]
[sim,xcc] removed sll32/srl32/sra32 opcodes
These instructions handled static shift amounts >= 32. Since we have
a 6-bit shift amount field, these opcodes are no longer necessary.
Andrew Waterman [Wed, 4 Aug 2010 03:48:02 +0000 (20:48 -0700)]
[pk,sim,xcc] Renamed instructions to RISC-V spec
All word-sized arithmetic operations are now postfixed with 'w',
and all double-word-sized arithmetic operations are no longer
prefixed with 'd'. mtc0/mfc0 are removed and replaced with
mfpcr/mtpcr/mwfpcr/mwtpcr.
Andrew Waterman [Thu, 29 Jul 2010 05:36:04 +0000 (22:36 -0700)]
[gcc] generate code for complex branches
Andrew Waterman [Thu, 29 Jul 2010 02:08:04 +0000 (19:08 -0700)]
[sim,xcc] Changed instruction format to RISC-V
Massive changes to gcc, binutils to support new instruction encoding.
Simulator reflects these changes.
Yunsup Lee [Fri, 23 Jul 2010 01:38:01 +0000 (18:38 -0700)]
[sim] various fixes to get the sim work with the fesvr
Andrew Waterman [Thu, 22 Jul 2010 06:30:28 +0000 (23:30 -0700)]
[pk,sim] removed cop0 console i/o support
Andrew Waterman [Thu, 22 Jul 2010 03:12:09 +0000 (20:12 -0700)]
[pk,sim] first cut of appserver communication link
Andrew Waterman [Tue, 20 Jul 2010 05:58:42 +0000 (22:58 -0700)]
[pk,sim] added temporary "exit" functionality
Andrew Waterman [Mon, 19 Jul 2010 01:28:05 +0000 (18:28 -0700)]
Reorganized directory structure
Moved cross-compiler to /xcc/ rather than /
Added ISA sim in /sim/
Added Proxy Kernel in /pk/ (to be cleaned up)
Added opcode map to /opcodes/ (ditto)
Added documentation to /doc/
projects / riscv-isa-sim.git / log