mesa: Add support for inverted s/w conditional rendering

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

i965/vec4: Add a pass to reduce swizzles.

total instructions in shared programs: 4344280 -> 4288033 (-1.29%)
instructions in affected programs:     397468 -> 341221 (-14.15%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

vc4: Plumb the texture index from TGSI through to the sampler uniforms.

This commit and the last one fix ARB_fragment_program/sparse-samplers and
6 other tests.

vc4: Avoid a null-deref if a sampler index isn't used.

Part of fixing ARB_fragment_program/sparse-samplers

mesa: fix NULL pointer deref bug in _mesa_drawbuffers()

This is a follow-on fix to commit 39b40ad144.  Fixes a crash if the
user calls glDrawBuffers(0, NULL).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82814
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

r600g: Fix missing SET_TEXTURE_OFFSETS

SB needs a bit of special handling to handle
instructions without obvious side effects, to
avoid it deleting them.

Fixes failing non-const ARB_gpu_shader5
textureOffsets piglits with sb enabled.

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

gallium/target: Add needed mesautil lib to haiku-softpipe

Acked-by: Brian Paul <brianp@vmware.com>

gallium/aux: Fill in Haiku get process name code

Acked-by: Brian Paul <brianp@vmware.com>

haiku/swrast: Add missing src include search path for missing util/macros.h

Acked-by: Brian Paul <brianp@vmware.com>

docs: Update status of ARB_conditional_render_inverted

Done for: nvc0, softpipe and llvmpipe

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>

llvmpipe/softpipe: enable ARB_conditional_render_inverted

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>

nvc0: Handle ARB_conditional_render_inverted and enable it

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>

mesa/st: Support ARB_conditional_render_inverted modes

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>

gallium: Add and handle PIPE_CAP_CONDITIONAL_RENDER_INVERTED

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>

mesa: add ARB_conditional_render_inverted flags

Also add an extension bit so we can safely enable

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>

glapi: add GL_ARB_conditional_render_inverted

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>

ilo: fix PIPE_CAP_VIDEO_MEMORY

I changed Emil's patch in f921131a5cebc233749a86cdd44b409c0cecc4ef to report
raw values in the winsys, but forgot to convert the values to megabytes in the
pipe driver.

ilo: enable HiZ in more cases on GEN6

With layer offsetting killed, we no longer need to restrict HiZ to
non-mipmapped and non-arary depth buffers.

ilo: remove layer offsetting

Follow i965 to kill layer offsetting for GEN6.

ilo: migrate to ilo_layout

Embed an ilo_layout in ilo_texture, and remove now duplicated members.

ilo: add new resource layout code

Based on the old code, the new layout code describes the layout with the new,
well-documented, ilo_layout.  It also gains new features such as MCS support
and extended ARYSPC_LOD0 that i965 comes up with (see
6345a94a9b134b1321b3b290bacde228b12af415).

gallium/radeon: Do not use u_upload_mgr for buffer downloads

Instead create a staging texture with pipe_buffer_create and
PIPE_USAGE_STAGING.

u_upload_mgr sets the usage of its staging buffer to PIPE_USAGE_STREAM.
But since 150ac07b855b5c5f879bf6ce9ca421ccd1a6c938 CPU -> GPU streaming buffers
are created in VRAM. Therefore the staging texture (in VRAM) does not offer any
performance improvements for buffer downloads.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

r600g: copy IA_MULTI_VGT_PARAM programming from radeonsi for Cayman

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: bump PRIMGROUP_SIZE for some cases

Recommended by hw people.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: set PARTIAL_VS_WAVE(0) when appropriate

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: set IA_MULTI_VGT_PARAM on SI the same as on CIK (v2)

Nothing's changed for CIK here.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: simplify si_num_banks function

This makes it easier to use.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: use r600_draw_rectangle from r600g

Rectangles are easier than triangles for the rasterizer.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: save scissor state and sample mask for u_blitter

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: don't set CB_SHADER_MASK=1 if there are no color outputs

This hack isn't needed anymore because of the previous u_blitter commit.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/u_blitter: don't use an empty fragment shader if there's a colorbuffer

This is custom code used by some drivers.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium/util: handle PIPE_BUFFER in util_pipe_tex_to_tgsi_tex

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

rbug: only add textures to the list

rbug-gui cannot display buffers, so it's pointless to add them.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

rbug: fix a crash in sampler_view_destroy caused by incorrect context

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

rbug: send the actual number of layers to the client

This sends the correct value for array textures.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

rbug: implement streamout context functions

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

rbug: fix crash in set_vertex_buffers

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

rbug: remove contexts from the list properly

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

ilo: fold drm_intel_get_aperture_sizes() within probe_winsys()

... and store the value in intel_winsys_info/ilo_dev_info.

Suggested-by: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
olv: check for errors and report raw values

i965/cfg: Add a foreach_block_and_inst_safe macro.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/cfg: Add a foreach_inst_in_block_safe macro.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/cfg: Add a foreach_block_safe macro.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Pass a cfg pointer to generate_{code,assembly}.

The loop over all instructions is now two-fold, over all of the blocks
and all of the instructions in each block.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Add and use foreach_block macro.

Use this as an opportunity to rename 'block_num' to 'num'. block->num is
clear, and block->block_num has always been redundant.

i965/cfg: Embed link in bblock_t for main block list.

The next patch adds a foreach_block (block, cfg) macro, which works
better if it provides a direct bblock_t pointer, rather than a
bblock_link pointer that you have to use to find the actual block.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/fs: Optimize gl_FrontFacing calculation on Gen4/5.

Doesn't use fewer instructions, but it does avoid writing the flag
register and if we want to switch the representation of true for Gen4/5
in the future, we can just delete the AND instruction.

i965/fs: Optimize gl_FrontFacing calculation on Gen6+.

total instructions in shared programs: 4288650 -> 4282838 (-0.14%)
instructions in affected programs:     595018 -> 589206 (-0.98%)

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Use ~0 to represent true on Gen >= 6.

total instructions in shared programs: 4292303 -> 4288650 (-0.09%)
instructions in affected programs:     299670 -> 296017 (-1.22%)

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965/fs: Optimize emit_bool_to_cond_code for logical exprs.

AND, OR, and XOR can generate the conditional code directly.

total instructions in shared programs: 4293335 -> 4292303 (-0.02%)
instructions in affected programs:     121408 -> 120376 (-0.85%)

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Use UniformBooleanTrue value for boolean literal true.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

glsl: Use UniformBooleanTrue value for uniform initializers.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

mesa: Upload boolean uniforms using UniformBooleanTrue.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Remove dead call to _mesa_associate_uniform_storage().

Dead since the call to _mesa_generate_parameters_list_for_uniforms
was removed in commit 12751ef2. So this was why all of that code that
was supposed to fix up the value of a uniform bool to wasn't happening.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

mapi: Inline shared-glapi/tests/Makefile.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

mapi: Inline glapi/tests/Makefile.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

mapi: Inline glapi/Makefile.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

mapi: Inline es2api/Makefile.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

mapi: Inline es1api/Makefile.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

mapi: Inline shared-glapi/Makefile.

build: Let install-lib-links.mk handle .la files in subdirectories.

The next patches are going to combine some of the mapi subdirectories'
Makefiles into a single Makefile, giving better build parallelism.

lib_LTLIBRARIES will be set to something like

   lib_LTLIBRARIES = shared-glapi/libglapi.la es2api/libGLESv2.la

and the current code in install-lib-links.mk simply prepends .libs/ and
replaces the .la in order to create the filenames that it needs to ln/cp
into the LIBDIR. This doesn't work when the .la file is actually in a
subdirectory.

This patch fixes this and puts .libs/ in the right place.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

i965: Enable instruction compaction on Gen8+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add support for compacting 3-src instructions on Gen8.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add support for compacting 1- and 2-src instructions on Gen8.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen8: Add 3-src instruction compaction tables.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen8: Add instruction compaction tables.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Update JIP/UIP compaction code to operate on bytes.

JIP/UIP were previously in units of compacted instructions. On Gen8
they're in units of bytes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Reverse condition ordering to let us support other gens.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/disasm: Add CSEL.

mesa: fix copy and paste errors in glBindVertexBuffers

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Fredrik Höglund <fredrik@kde.org>

nv50/ir: (trivial) initialize pointer to silence warning

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>

vc4: Add support for swizzling of texture colors.

Fixes swapped colors on the copypix demo and some piglit tests like
pbo-teximage-tiling .

vc4: Fix handling of non-XYZW swizzles in color outputs.

The SWIZZLE_1 of the winsys destination was dereffing off the end of the
array, which surprisingly often worked out (since nobody reads the
rendered value anyway, so whatever junk was referenced in the QIR didn't
matter), but shader dumping would sometimes segfault.

vc4: Extract the swizzle handling from vertex fetch.

I want to reuse this elsewhere, and NONE debug output hasn't been useful
so I don't miss it being as detailed as it was before.

vc4: Add support for color masking.

This gets fbo-colormask-formats working for core formats, which increases
my confidence in some of the swizzle and blend handling.

vc4: Add a helper for QOP_R4_UNPACK_[ABCD].

vc4: Don't forget to set up the offset for render targets.

This almost fixes fbo-generatemipmap rendering, except that the 1x1 level
isn't getting rendered.

vc4: Fix multi-level texture setup.

We weren't accounting for the level 0 offset in the texture setup (so it
only worked if it happened to be a single-level texture), and doing so
required that we get the level 0 offset page aligned so that the offset
bits don't get interpreted as the texture format and such.

vc4: Fix viewport handling in the uniforms upload.

I had the right viewports in vc4_emit.c, but grabbed the wrong values in
the uniform setup, so primitives would claim to be in the wrong parts of
the screen.  (The vc4_emit.c state looks like it just decides how big the
clipping guardband is).

This gets fbo-viewport closer to working (which still has the problem that
the HW is always guard-band clipping), and fixes inverted FBO rendering in
general.

docs/relnotes: document GLX_MESA_query_renderer

clover: Refuse to build a program if there are kernel objects attached to it.

Fixes piglit cl-api-build-program.

Tested-by: EdB <edb+mesa@sigluy.net>

clover/util: Pass initial count value to ref_counter constructor.

And mark the ref_count() method as const.

Tested-by: EdB <edb+mesa@sigluy.net>

clover/util: Implement minimalist reference to clover::ref_counter object.

Tested-by: EdB <edb+mesa@sigluy.net>

clover: clGetProgramInfo support for OpenCL 1.2.

[ Francisco Jerez: Rework using fold() for conciseness. ]

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: EdB <edb+mesa@sigluy.net>

nouveau: don't keep stale pointer to free'd data

If ->sys is non-null, we might decide that it's where the data is
stored.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

egl: don't exit process on initialization failure

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

mesa: fix compressed_subtexture_error_check() return value

The function should return GLboolean, not GLenum.
If we detect invalid compressed pixel storage parameters, we should
return GL_TRUE, not GL_FALSE so that the function is no-op'd.
An update to the piglit s3tc-errors test will check this.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: move _mesa_compressed_texture_pixel_storage_error_check()

to pixelstore.c, add const qualifier to the 'packing' parameter.
Add comments.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: minor improvements to _mesa_compute_compressed_pixelstore()

Replace the gl_texture_image parameter with mesa_format since we only
used the image's format.

Add some comments.

Reviewed-by: Matt Turner <mattst88@gmail.com>

util: whitespace and formatting fixes in u_math.h

Trivial.

nouveau: make sure to invalidate any vbo state as well

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

i965/gen6: Force ALL_SLICES_AT_EACH_LOD for separate stencil/hiz

For gen6 we will use the ALL_SLICES_AT_EACH_LOD miptree layout for
separate stencil/hiz. This is needed because gen6 hiz and separate
stencil only support a single miplevel. When accessing the other LODs,
we will program a tile aligned offset for the bo.

PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK]
to [DevSNB]:
 "The separate stencil buffer does not support mip mapping, thus the
  storage for LODs other than LOD 0 is not needed."

We still allocate storage for the other stencil mip-levels within a
single texture, but each mip-level will use non-mip-array spacing.

PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer
 "[DevSNB]: The hierarchical depth buffer does not support the LOD
  field, it is assumed by hardware to be zero. A separate
  hierarachical depth buffer is required for each LOD used, and the
  corresponding buffer’s state delivered to hardware each time a new
  depth buffer state with modified LOD is delivered."

We allocate storage for the other hiz mip-levels within a single
texture, but each mip-level will use non-mip-array spacing.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6: Stencil/hiz needs an offset for LOD > 0

Since gen6 separate stencil & hiz only supports LOD0, we need to
program an offset to the LOD when emitting the separate stencil/hiz.

v3:
 * Use new array_layout enum

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6: Force tile alignment for each stencil/hiz LOD

Gen6 doesn't support multiple miplevels for hiz and stencil.

Therefore, we must point to the LOD directly during rendering.

But, we also have removed the tile offsets from normal depth surfaces,
so we need to align each LOD to a tile boundary for hiz and stencil.

v3:
 * Use new array_layout enum

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Support array_layout == ALL_SLICES_AT_EACH_LOD for multiple LODs

Previously array_layout ALL_SLICES_AT_EACH_LOD was only used for array
spacing lod0 on gen7+ and therefore was only used with a single mip
level.

gen6 separate stencil & hiz only support LOD0, so we need to allocate
the miptree similar to gen7+ array spacing lod0, except we also need
space for multiple mip levels. (Since OpenGL stencil and depth support
multiple LODs.)

The miptree is allocated with tightly packed array slice spacing, but
we still also pack the miplevels into the region similar to a normal
multi mip level packing.

A 2D Array texture with 2 slices and multiple LODs would look somewhat
like this:

+----------+
|          |
|          |
+----------+
|          |
|          |
+----------+
+---+ +-+
|   | +-+
+---+ +-+
|   | :
+---+

v3:
 * Use new array_layout enum
 * ASCII art!

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LOD

gen6 does not support multiple miplevels with separate
stencil/hiz. Therefore we need to layout its miptree with no mipmap
spacing between the slices of each miplevel.

v3:
 * Use new array_layout enum

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Change mipmap array_spacing_lod0 to array_layout (enum)

We will want to setup gen6 separate stencil and hiz miptrees in a
layout that is similar to array_spacing_lod0. This is needed because
gen6 hiz and stencil only support a single mip-level.

In both use cases (gen7+ LOD0 spacing & gen6 separate stencil/hiz),
the array slices will be packed at each LOD without reserving extra
space for LODs within each array slice.

So, we generalize the name of this field and add comments to indicate
the old and new uses.

Motivation for the gen6 change comes from the PRM:

PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK]
to [DevSNB]:
 "The separate stencil buffer does not support mip mapping, thus the
  storage for LODs other than LOD 0 is not needed."

PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer
 "[DevSNB]: The hierarchical depth buffer does not support the LOD
  field, it is assumed by hardware to be zero. A separate
  hierarachical depth buffer is required for each LOD used, and the
  corresponding buffer’s state delivered to hardware each time a new
  depth buffer state with modified LOD is delivered."

v2:
 * Rename array_spacing_lod0 to non_mip_arrays
v3:
 * Instead, replace array_spacing_lod0 with array_layout enum

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface

(bf25ee2 for gen6)

Previously we would always find the 2D sub-surface of interest,
and then program the surface to this location. Now we always
program the 3DSTATE_DEPTH_BUFFER at the start of the surface.
To select the lod/slice, we utilize the lod & minimum array
element fields.

We also must disable brw_workaround_depthstencil_alignment for
gen >= 6. Now the hardware will handle alignment when rendering
to additional slices/LODs.

v3:
 * Set depth_mt bo RELOC offset to 0, as was done in bf25ee2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56127
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6 fbo: make unmatched depth/stencil configs return unsupported

(f3c886b for gen6)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6 blorp depth: calculate base surface width/height

(e3a49e1 for gen6)

This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6 depth surface: calculate minimum array element being rendered

(a23cfb8 for gen6)

In layered rendering this will be 0. Otherwise it will be the
selected slice.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>