Eddie Hung [Wed, 27 Nov 2019 20:35:25 +0000 (12:35 -0800)]
Revert "Fold loop"
This reverts commit
da51492dbcc9f19a4808ef18e8ae1222bc55b118.
Eddie Hung [Wed, 27 Nov 2019 18:17:10 +0000 (10:17 -0800)]
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 17:10:34 +0000 (09:10 -0800)]
ean call after abc{,9}
Eddie Hung [Wed, 27 Nov 2019 16:19:13 +0000 (08:19 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 16:18:41 +0000 (08:18 -0800)]
Do not replace constants with same wire
Eddie Hung [Wed, 27 Nov 2019 16:00:22 +0000 (08:00 -0800)]
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
Clifford Wolf [Wed, 27 Nov 2019 10:25:23 +0000 (11:25 +0100)]
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
memory_collect: Copy attr from RTLIL::Memory to cell
Clifford Wolf [Wed, 27 Nov 2019 10:23:16 +0000 (11:23 +0100)]
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix
opt_share: Fix handling of fine cells.
Eddie Hung [Wed, 27 Nov 2019 09:04:29 +0000 (01:04 -0800)]
Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve
write_xaiger improvements
Eddie Hung [Wed, 27 Nov 2019 09:03:33 +0000 (01:03 -0800)]
Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 09:02:21 +0000 (01:02 -0800)]
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 09:02:16 +0000 (01:02 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 09:01:24 +0000 (01:01 -0800)]
Cleanup
Eddie Hung [Wed, 27 Nov 2019 08:51:39 +0000 (00:51 -0800)]
Check for nullptr
Eddie Hung [Wed, 27 Nov 2019 08:50:25 +0000 (00:50 -0800)]
Stray log_dump
Eddie Hung [Wed, 27 Nov 2019 08:48:22 +0000 (00:48 -0800)]
Revert "submod to bitty rather bussy, for bussy wires used as input and output"
This reverts commit
cba3073026711e7683c46ba091c56a5c5a041a45.
Eddie Hung [Wed, 27 Nov 2019 07:39:14 +0000 (23:39 -0800)]
Promote output wires in sigmap so that can be detected
Eddie Hung [Wed, 27 Nov 2019 07:38:49 +0000 (23:38 -0800)]
Fix wire width
Eddie Hung [Tue, 26 Nov 2019 19:57:26 +0000 (11:57 -0800)]
Fix submod -hidden
Eddie Hung [Tue, 26 Nov 2019 19:35:15 +0000 (11:35 -0800)]
Add -hidden option to submod
Eddie Hung [Wed, 27 Nov 2019 07:08:14 +0000 (23:08 -0800)]
No need for -abc9
Marcin Kościelnicki [Tue, 26 Nov 2019 23:46:21 +0000 (00:46 +0100)]
opt_share: Fix handling of fine cells.
Fixes #1525.
Eddie Hung [Wed, 27 Nov 2019 06:59:05 +0000 (22:59 -0800)]
latch -> box
Eddie Hung [Wed, 27 Nov 2019 06:56:53 +0000 (22:56 -0800)]
Merge branch 'master' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 06:51:16 +0000 (22:51 -0800)]
Add citation
Eddie Hung [Wed, 27 Nov 2019 05:26:53 +0000 (21:26 -0800)]
Check for either sign or zero extension for postAdd packing
Eddie Hung [Wed, 27 Nov 2019 06:41:35 +0000 (22:41 -0800)]
Remove notes
Eddie Hung [Mon, 25 Nov 2019 23:43:37 +0000 (15:43 -0800)]
Fold loop
Eddie Hung [Mon, 25 Nov 2019 23:42:07 +0000 (15:42 -0800)]
Do not sigmap keep bits inside write_xaiger
Eddie Hung [Wed, 27 Nov 2019 03:03:02 +0000 (19:03 -0800)]
xaiger: do not promote output wires
Eddie Hung [Wed, 27 Nov 2019 05:26:30 +0000 (21:26 -0800)]
Add testcase derived from fastfir_dynamictaps benchmark
Eddie Hung [Wed, 27 Nov 2019 03:03:02 +0000 (19:03 -0800)]
xaiger: do not promote output wires
Eddie Hung [Tue, 26 Nov 2019 22:51:39 +0000 (14:51 -0800)]
Move 'clean' from map_luts to finalize
Eddie Hung [Tue, 26 Nov 2019 19:57:26 +0000 (11:57 -0800)]
Fix submod -hidden
Eddie Hung [Tue, 26 Nov 2019 19:35:32 +0000 (11:35 -0800)]
clkpart to use 'submod -hidden'
Eddie Hung [Tue, 26 Nov 2019 19:35:15 +0000 (11:35 -0800)]
Add -hidden option to submod
Eddie Hung [Tue, 26 Nov 2019 19:12:58 +0000 (11:12 -0800)]
Update docs with bullet points
Marcin Kościelnicki [Tue, 26 Nov 2019 04:04:28 +0000 (05:04 +0100)]
xilinx: Add simulation models for IOBUF and OBUFT.
Eddie Hung [Tue, 26 Nov 2019 00:07:47 +0000 (16:07 -0800)]
Move \init from source wire to submod if output port
Eddie Hung [Tue, 26 Nov 2019 00:07:35 +0000 (16:07 -0800)]
Add testcase where \init is copied
Eddie Hung [Mon, 25 Nov 2019 23:43:37 +0000 (15:43 -0800)]
Fold loop
Eddie Hung [Mon, 25 Nov 2019 23:42:07 +0000 (15:42 -0800)]
Do not sigmap keep bits inside write_xaiger
Eddie Hung [Mon, 25 Nov 2019 20:04:11 +0000 (12:04 -0800)]
clkpart to analyse async flops too
Eddie Hung [Mon, 25 Nov 2019 20:59:34 +0000 (12:59 -0800)]
Fix debug
Eddie Hung [Mon, 25 Nov 2019 20:42:09 +0000 (12:42 -0800)]
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Mon, 25 Nov 2019 20:36:13 +0000 (12:36 -0800)]
Special abc9_clock wire to contain only clock signal
Eddie Hung [Mon, 25 Nov 2019 20:35:57 +0000 (12:35 -0800)]
abc9 to contain time call
Eddie Hung [Mon, 25 Nov 2019 20:35:38 +0000 (12:35 -0800)]
abc9 to no longer to clock partitioning, operate on whole modules only
Eddie Hung [Mon, 25 Nov 2019 20:04:11 +0000 (12:04 -0800)]
clkpart to analyse async flops too
Marcin Kościelnicki [Sun, 24 Nov 2019 15:05:45 +0000 (16:05 +0100)]
clkbufmap: Add support for inverters in clock path.
Marcin Kościelnicki [Sun, 24 Nov 2019 13:17:46 +0000 (14:17 +0100)]
xilinx: Use INV instead of LUT1 when applicable
Eddie Hung [Sat, 23 Nov 2019 18:29:03 +0000 (10:29 -0800)]
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 18:28:46 +0000 (10:28 -0800)]
More oopsies
Eddie Hung [Sat, 23 Nov 2019 18:26:55 +0000 (10:26 -0800)]
Conditioning abc9 on POs not accurate due to cells
Eddie Hung [Sat, 23 Nov 2019 18:18:22 +0000 (10:18 -0800)]
For abc9, run clkpart before ff_map and after abc9
Eddie Hung [Sat, 23 Nov 2019 18:18:06 +0000 (10:18 -0800)]
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 18:17:31 +0000 (10:17 -0800)]
Print ".en=" only if there is an enable signal
Eddie Hung [Sat, 23 Nov 2019 18:16:56 +0000 (10:16 -0800)]
Escape IdStrings
Eddie Hung [Sat, 23 Nov 2019 18:01:09 +0000 (10:01 -0800)]
More sane naming of submod
Eddie Hung [Sat, 23 Nov 2019 17:52:17 +0000 (09:52 -0800)]
Add -set_attr option, -unpart to take attr name
Eddie Hung [Sat, 23 Nov 2019 16:39:19 +0000 (08:39 -0800)]
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 16:38:48 +0000 (08:38 -0800)]
Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 16:22:03 +0000 (08:22 -0800)]
Merge pull request #1505 from YosysHQ/eddie/xaig_dff_adff
xaig_dff to support async flops $_DFF_[NP][NP][01]_
Eddie Hung [Sat, 23 Nov 2019 07:29:10 +0000 (23:29 -0800)]
Do not use log_signal() for empty SigSpec to prevent "{ }"
Eddie Hung [Sat, 23 Nov 2019 07:16:15 +0000 (23:16 -0800)]
Call submod once, more meaningful submod names, ignore largest domain
Eddie Hung [Sat, 23 Nov 2019 07:01:18 +0000 (23:01 -0800)]
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 06:45:40 +0000 (22:45 -0800)]
Merge pull request #1520 from pietrmar/fix-1463
coolrunner2: remove spurious log_pop() call, fixes #1463
Eddie Hung [Sat, 23 Nov 2019 06:28:35 +0000 (22:28 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 06:22:56 +0000 (22:22 -0800)]
Remove redundant flatten
Martin Pietryka [Sat, 23 Nov 2019 05:18:23 +0000 (06:18 +0100)]
coolrunner2: remove spurious log_pop() call, fixes #1463
This was causing a segmentation fault because there is no accompanying
log_push() call so header_count.size() became -1.
Signed-off-by: Martin Pietryka <martin@pietryka.at>
Eddie Hung [Sat, 23 Nov 2019 04:53:58 +0000 (20:53 -0800)]
submod to bitty rather bussy, for bussy wires used as input and output
Eddie Hung [Sat, 23 Nov 2019 04:53:48 +0000 (20:53 -0800)]
Stray dump
Eddie Hung [Sat, 23 Nov 2019 01:25:53 +0000 (17:25 -0800)]
Move clkpart into passes/hierarchy
Eddie Hung [Sat, 23 Nov 2019 01:24:45 +0000 (17:24 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 01:23:51 +0000 (17:23 -0800)]
Constant driven signals are also an input to submodules
Eddie Hung [Sat, 23 Nov 2019 01:23:34 +0000 (17:23 -0800)]
Add another test with constant driver
Eddie Hung [Sat, 23 Nov 2019 01:04:33 +0000 (17:04 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 01:03:30 +0000 (17:03 -0800)]
Oops
Eddie Hung [Sat, 23 Nov 2019 01:00:35 +0000 (17:00 -0800)]
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 01:00:11 +0000 (17:00 -0800)]
Only action if there is more than one clock domain
Eddie Hung [Sat, 23 Nov 2019 00:58:08 +0000 (16:58 -0800)]
Replace TODO
Eddie Hung [Sat, 23 Nov 2019 00:52:55 +0000 (16:52 -0800)]
Add testcase for signal used as part input part output
Eddie Hung [Sat, 23 Nov 2019 00:52:17 +0000 (16:52 -0800)]
write_xaiger back to working with whole modules only
Eddie Hung [Sat, 23 Nov 2019 00:50:56 +0000 (16:50 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 00:50:09 +0000 (16:50 -0800)]
Cleanup spacing
Eddie Hung [Sat, 23 Nov 2019 00:46:26 +0000 (16:46 -0800)]
sigmap(wire) should inherit port_output status of POs
Eddie Hung [Sat, 23 Nov 2019 00:41:05 +0000 (16:41 -0800)]
Add testcase
Eddie Hung [Fri, 22 Nov 2019 23:41:48 +0000 (15:41 -0800)]
Merge branch 'eddie/clkpart' into xaig_dff
Eddie Hung [Fri, 22 Nov 2019 23:41:34 +0000 (15:41 -0800)]
Brackets
Eddie Hung [Fri, 22 Nov 2019 23:41:23 +0000 (15:41 -0800)]
Entry in Makefile.inc
Eddie Hung [Fri, 22 Nov 2019 23:38:48 +0000 (15:38 -0800)]
Merge branch 'eddie/clkpart' into xaig_dff
Eddie Hung [Fri, 22 Nov 2019 23:35:08 +0000 (15:35 -0800)]
Add to CHANGELOG
Eddie Hung [Fri, 22 Nov 2019 23:33:51 +0000 (15:33 -0800)]
New 'clkpart' to {,un}partition design according to clock/enable
Eddie Hung [Fri, 22 Nov 2019 23:13:18 +0000 (15:13 -0800)]
Merge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung [Fri, 22 Nov 2019 21:24:28 +0000 (13:24 -0800)]
Revert "write_xaiger to not use module POs but only write outputs if driven"
This reverts commit
0ab1e496dc601f8e9d5efbcc5b2be7cf6b2d9673.
Eddie Hung [Fri, 22 Nov 2019 20:37:57 +0000 (12:37 -0800)]
Missing endmodule
Clifford Wolf [Fri, 22 Nov 2019 17:11:58 +0000 (18:11 +0100)]
Merge pull request #1517 from YosysHQ/clifford/optmem
Add "opt_mem" pass
Clifford Wolf [Fri, 22 Nov 2019 17:10:34 +0000 (18:10 +0100)]
Merge pull request #1515 from YosysHQ/clifford/svastuff
Add Verific/SVA support for "always" and "nexttime" properties
Clifford Wolf [Fri, 22 Nov 2019 15:58:49 +0000 (16:58 +0100)]
Add "opt_mem" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 22 Nov 2019 15:11:56 +0000 (16:11 +0100)]
Add Verific support for SVA nexttime properties
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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