litex.git
9 years agoupdate lm32 with "Switch to -fPIC" changes.
Florent Kermarrec [Tue, 28 Jul 2015 09:11:11 +0000 (11:11 +0200)]
update lm32 with "Switch to -fPIC" changes.

9 years agoUpdate libbase/linker-sdram.ld with -fPIC support.
whitequark [Sun, 26 Jul 2015 13:15:02 +0000 (16:15 +0300)]
Update libbase/linker-sdram.ld with -fPIC support.

9 years agoSwitch to -fPIC.
whitequark [Sun, 26 Jul 2015 13:06:48 +0000 (16:06 +0300)]
Switch to -fPIC.

Using -fPIC for everything allows to link the MiSoC static libraries
both into static images such as the BIOS as well as
into shared libraries.

9 years agoRemove useless includes pulled in by libunwind.
whitequark [Sun, 26 Jul 2015 10:12:23 +0000 (13:12 +0300)]
Remove useless includes pulled in by libunwind.

These aren't used by libunwind in any configuration and
should be also removed in upstream.

9 years agoAdd libunwind.
whitequark [Sun, 26 Jul 2015 09:59:18 +0000 (12:59 +0300)]
Add libunwind.

9 years agoAdd a stub getenv() implementation.
whitequark [Sun, 26 Jul 2015 09:55:52 +0000 (12:55 +0300)]
Add a stub getenv() implementation.

This is not strictly necessary to build libunwind (it can
be built with -DNDEBUG), but it will be handy while it is
debugged.

It can be removed afterwards.

9 years agoAdd a stub pthread header.
whitequark [Sun, 26 Jul 2015 09:54:40 +0000 (12:54 +0300)]
Add a stub pthread header.

The header implements only the pthread rwlock interface, which
never actually locks.

This is necessary to build libunwind.

9 years agoAdd headers for the dynamic linker interface.
whitequark [Sun, 26 Jul 2015 09:53:18 +0000 (12:53 +0300)]
Add headers for the dynamic linker interface.

These are required for libunwind to discover
the exception frame headers.

9 years agoAdd a stub C++ standard library.
whitequark [Sun, 26 Jul 2015 09:49:02 +0000 (12:49 +0300)]
Add a stub C++ standard library.

This is necessary to build libunwind.

9 years agoAdd basic inttypes.h.
whitequark [Sun, 26 Jul 2015 09:44:13 +0000 (12:44 +0300)]
Add basic inttypes.h.

This is taken from glibc. Only PRI* definitions are imported;
functions are not.

9 years agoMark abort() as __attribute__((noreturn)).
whitequark [Sun, 26 Jul 2015 09:43:22 +0000 (12:43 +0300)]
Mark abort() as __attribute__((noreturn)).

9 years agoAdd support for fprintf(stderr, ...).
whitequark [Sun, 26 Jul 2015 09:42:53 +0000 (12:42 +0300)]
Add support for fprintf(stderr, ...).

9 years agoDon't use clang for anything except or1k.
whitequark [Sun, 26 Jul 2015 07:00:58 +0000 (10:00 +0300)]
Don't use clang for anything except or1k.

9 years agocommon.mak: Pass -fexceptions to clang and clang++.
whitequark [Sun, 26 Jul 2015 00:30:21 +0000 (03:30 +0300)]
common.mak: Pass -fexceptions to clang and clang++.

This results in generation of .eh_frame sections. These sections
can be discarded during final linking, or included if exception
handling is desired. For exception handling to work, all sources
must be built with -fexceptions.

9 years agocommon.mak: use clang/clang++ to compile C/C++ sources.
whitequark [Sun, 26 Jul 2015 00:28:37 +0000 (03:28 +0300)]
common.mak: use clang/clang++ to compile C/C++ sources.

Note that -integrated-as is not active by default on OR1K,
so we're still shelling out to binutils to assemble.
It is not yet possible to build everything using -integrated-as.

9 years agocommon.mak: remove RANLIB.
whitequark [Sun, 26 Jul 2015 00:20:23 +0000 (03:20 +0300)]
common.mak: remove RANLIB.

`ranlib` is not necessary on any system we can possibly build for,
as it is superseded by `ar s` for the last ten years or so (at least).
Thus, change ar invocations to `ar crs`, also removing a `l` flag
that is ignored by binutils.

9 years agocommon.mak: remove AS.
whitequark [Sat, 25 Jul 2015 23:46:03 +0000 (02:46 +0300)]
common.mak: remove AS.

$(AS) was never used: $(assemble) invokes the C compiler instead.
In case of LLVM, this will allow us to consistently use the LLVM
internal assembler for both inline assembly in C and assembly
sources; so, avoid ever invoking binutils as explicitly.

9 years agomisoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq...
Florent Kermarrec [Fri, 24 Jul 2015 22:21:59 +0000 (00:21 +0200)]
misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq.

An optimal solution for both sync and async mode is not easy to implement, it would requires moving CDC out of UART module and handling in the PHY with AsyncFIFO or minimal depth.
For now use the solution that works for both cases. We'll try to optimize that if we have performance issues.

9 years agomisoclib: integrate mxcrg.py in mlabs_video target, remove others directory
Florent Kermarrec [Fri, 24 Jul 2015 21:10:19 +0000 (23:10 +0200)]
misoclib: integrate mxcrg.py in mlabs_video target, remove others directory

we should also get rid of mxcrg.v (similar to what is done on papilio or pipstrello)

9 years agomisoclib/com/uart: replace revered Migen FIFO function with specific _get_uart_fifo...
Florent Kermarrec [Fri, 24 Jul 2015 11:57:57 +0000 (13:57 +0200)]
misoclib/com/uart: replace revered Migen FIFO function with specific _get_uart_fifo function for our use case.

9 years agolitepcie/frontend/dma: group loop index and count in loop_status register (avoid...
Florent Kermarrec [Fri, 24 Jul 2015 11:52:57 +0000 (13:52 +0200)]
litepcie/frontend/dma: group loop index and count in loop_status register (avoid 2 register reads)

9 years agomisoclib/com/uart: cleanup and add irq condition parameters
Florent Kermarrec [Fri, 24 Jul 2015 09:03:40 +0000 (11:03 +0200)]
misoclib/com/uart: cleanup and add irq condition parameters
- reintroduce RX/TX split (ease comprehension)
- use FIFO wrapper function from Migen.
- add tx_irq_condition and rx_irq_condition

9 years agolitepcie/frontend/dma: add loop counter (useful to detect missed interrupts)
Florent Kermarrec [Wed, 22 Jul 2015 20:55:11 +0000 (22:55 +0200)]
litepcie/frontend/dma: add loop counter (useful to detect missed interrupts)

9 years agolitepcie: use data instead of dat in dma_layout (allow use of migen.actorlib.packet...
Florent Kermarrec [Wed, 22 Jul 2015 19:44:53 +0000 (21:44 +0200)]
litepcie: use data instead of dat in dma_layout (allow use of migen.actorlib.packet modules on dma dataflow)

9 years agolitepcie: use optional platform.misoc_path to add litepcie phy wrapper verilog files
Florent Kermarrec [Wed, 22 Jul 2015 12:13:41 +0000 (14:13 +0200)]
litepcie: use optional platform.misoc_path to add litepcie phy wrapper verilog files

We should eventually try to use python package_data or data_file for that.

9 years agouart: remove option to refill HW from uart_write
Sebastien Bourdeauducq [Sun, 19 Jul 2015 21:41:38 +0000 (23:41 +0200)]
uart: remove option to refill HW from uart_write

9 years agouart: support async phys
Robert Jordens [Sun, 19 Jul 2015 07:23:35 +0000 (01:23 -0600)]
uart: support async phys

9 years agouart.c: rx overflow fix and tx simplification
Robert Jordens [Sun, 19 Jul 2015 07:23:34 +0000 (01:23 -0600)]
uart.c: rx overflow fix and tx simplification

* fixes the clearing of the rx ringbuffer on rx-overflow
* removes tx_level and tx_cts by restricting the ringbuffer
  to at least one slot empty
* agnostic of the details of the tx irq: works for uarts that
  generate tx interrupts on !tx-full or on tx-empty.
* only rx_produce and tx_consume need to be volatile

9 years agobios: add romboot
Florent Kermarrec [Tue, 14 Jul 2015 15:33:24 +0000 (17:33 +0200)]
bios: add romboot

When firmware is small enough, it can be interesting to run code from an embedded blockram memory (faster and not impacted by memory controller activity).
It can also be a fallback option in case boot from flash failed.
To use this, define ROM_BOOT_ADDRESS and initialize the blockram with the firmware data.

9 years agomake.py: use sys.path.insert(0...) to allow external designs to have specific targets...
Florent Kermarrec [Mon, 13 Jul 2015 15:00:03 +0000 (17:00 +0200)]
make.py: use sys.path.insert(0...) to allow external designs to have specific targets derived from a base target

9 years agomisoclib/video/dvisampler: add fifo_depth parameter
Florent Kermarrec [Mon, 13 Jul 2015 09:03:33 +0000 (11:03 +0200)]
misoclib/video/dvisampler: add fifo_depth parameter

9 years agowishbone2lasmi: fix "READ_DATA" state
Florent Kermarrec [Tue, 7 Jul 2015 13:45:06 +0000 (15:45 +0200)]
wishbone2lasmi: fix "READ_DATA" state

9 years agotools/flterm.py: fix kernel-adr support
Florent Kermarrec [Tue, 7 Jul 2015 12:58:49 +0000 (14:58 +0200)]
tools/flterm.py: fix kernel-adr support

9 years agoliteeth/core: add with_icmp parameter
Florent Kermarrec [Mon, 6 Jul 2015 19:23:19 +0000 (21:23 +0200)]
liteeth/core: add with_icmp parameter

9 years agouse sets for leave_out
Florent Kermarrec [Sun, 5 Jul 2015 20:49:23 +0000 (22:49 +0200)]
use sets for leave_out

9 years agoliteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce ressource usage...
Florent Kermarrec [Sun, 5 Jul 2015 20:45:53 +0000 (22:45 +0200)]
liteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce ressource usage with MII phy)

9 years agoliteeth: small logic optimizations on mac (eases timings on spartan6)
Florent Kermarrec [Sun, 5 Jul 2015 10:31:52 +0000 (12:31 +0200)]
liteeth: small logic optimizations on mac (eases timings on spartan6)

9 years agosoftware/bios: call eth_mode only if we have an ethernet mac (we don't need to call...
Florent Kermarrec [Sat, 4 Jul 2015 19:04:23 +0000 (21:04 +0200)]
software/bios: call eth_mode only if we have an ethernet mac (we don't need to call it when we have a hardware UDP/IP stack)

9 years agobios: show memtest command in help
Yann Sionneau [Thu, 2 Jul 2015 15:19:55 +0000 (17:19 +0200)]
bios: show memtest command in help

9 years agosoc: support constants without value
Sebastien Bourdeauducq [Sun, 28 Jun 2015 19:35:37 +0000 (21:35 +0200)]
soc: support constants without value

9 years agolibcompiler-rt: add fixdfdi
Sebastien Bourdeauducq [Sat, 27 Jun 2015 21:51:09 +0000 (23:51 +0200)]
libcompiler-rt: add fixdfdi

9 years agoflterm.py: use serial_for_url
Joe Britton [Fri, 26 Jun 2015 09:40:18 +0000 (11:40 +0200)]
flterm.py: use serial_for_url

9 years agolitesata/example_designs: fix core generation (RAID introduced some changes on the...
Florent Kermarrec [Thu, 25 Jun 2015 22:20:58 +0000 (00:20 +0200)]
litesata/example_designs: fix core generation (RAID introduced some changes on the PHY)

9 years agoMerge pull request #14 from olofk/misc_fixes
enjoy-digital [Thu, 25 Jun 2015 21:59:42 +0000 (23:59 +0200)]
Merge pull request #14 from olofk/misc_fixes

Misc fixes

9 years agolitesata/test: Add missing dependency on scrambler in bist_tb
Olof Kindgren [Thu, 25 Jun 2015 23:16:35 +0000 (01:16 +0200)]
litesata/test: Add missing dependency on scrambler in bist_tb

9 years agolitesata/example_designs: Add missing clock in phy instantiation
Olof Kindgren [Thu, 25 Jun 2015 23:15:34 +0000 (01:15 +0200)]
litesata/example_designs: Add missing clock in phy instantiation

9 years agoliteeth/example_designs: use new Keep SynthesisDirective
Florent Kermarrec [Tue, 23 Jun 2015 14:15:28 +0000 (16:15 +0200)]
liteeth/example_designs: use new Keep SynthesisDirective

9 years agosoftware/bios/sdram: flush dcache and l2 in memtest (otherwise we are partially testi...
Florent Kermarrec [Tue, 23 Jun 2015 07:01:34 +0000 (09:01 +0200)]
software/bios/sdram: flush dcache and l2 in memtest (otherwise we are partially testing the cache)

9 years agopipistrello: run at 83+1/3 MHz, cleanup CRG
Robert Jordens [Tue, 23 Jun 2015 00:48:31 +0000 (18:48 -0600)]
pipistrello: run at 83+1/3 MHz, cleanup CRG

9 years agoliteeth/software: fix wishbone bridge
Florent Kermarrec [Mon, 22 Jun 2015 22:53:31 +0000 (00:53 +0200)]
liteeth/software: fix wishbone bridge

9 years agoliteeth/example_designs: add false path between clock domains (speed up implementatio...
Florent Kermarrec [Mon, 22 Jun 2015 22:37:31 +0000 (00:37 +0200)]
liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection

9 years agoliteeth/core/arp: fix table timer (wait_timer adaptation issue)
Florent Kermarrec [Mon, 22 Jun 2015 22:25:26 +0000 (00:25 +0200)]
liteeth/core/arp: fix table timer (wait_timer adaptation issue)

9 years agoliteeth/core/arp: fix missing MAC address in ARP reply
Florent Kermarrec [Mon, 22 Jun 2015 21:15:00 +0000 (23:15 +0200)]
liteeth/core/arp: fix missing MAC address in ARP reply

9 years agosoftware/libbase/system: fix flush_l2_cache
Florent Kermarrec [Fri, 19 Jun 2015 07:00:14 +0000 (09:00 +0200)]
software/libbase/system: fix flush_l2_cache

9 years agosoc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function...
Florent Kermarrec [Fri, 19 Jun 2015 06:39:37 +0000 (08:39 +0200)]
soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined

9 years agoindentation
Sebastien Bourdeauducq [Wed, 17 Jun 2015 14:32:17 +0000 (08:32 -0600)]
indentation

9 years agosoc/sdram: add capability to share L2 cache in multi-CPU SoCs
Florent Kermarrec [Wed, 17 Jun 2015 12:52:30 +0000 (14:52 +0200)]
soc/sdram: add capability to share L2 cache in multi-CPU SoCs

9 years agosdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon
Florent Kermarrec [Tue, 16 Jun 2015 17:06:24 +0000 (19:06 +0200)]
sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon

9 years agolitesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)
Florent Kermarrec [Wed, 10 Jun 2015 10:15:59 +0000 (12:15 +0200)]
litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)

9 years agolitesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization
Florent Kermarrec [Wed, 10 Jun 2015 10:14:48 +0000 (12:14 +0200)]
litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization

self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.

9 years agosdram: use new Migen Converter in Minicon frontend and small cleanup
Florent Kermarrec [Tue, 2 Jun 2015 17:35:00 +0000 (19:35 +0200)]
sdram: use new Migen Converter in Minicon frontend and small cleanup

9 years agosdram/phy: fix simphy memory usage
Florent Kermarrec [Tue, 2 Jun 2015 17:33:09 +0000 (19:33 +0200)]
sdram/phy: fix simphy memory usage

9 years agosdram: refactor minicon and fix issues with DDRx memories
Florent Kermarrec [Fri, 29 May 2015 10:26:34 +0000 (12:26 +0200)]
sdram: refactor minicon and fix issues with DDRx memories

- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals

9 years agospiflash: now using 64k sectors
Yann Sionneau [Fri, 15 May 2015 09:03:02 +0000 (11:03 +0200)]
spiflash: now using 64k sectors

9 years agospiflash: cleanup unnecessary parenthesis
Yann Sionneau [Fri, 15 May 2015 09:02:16 +0000 (11:02 +0200)]
spiflash: cleanup unnecessary parenthesis

9 years agolitesata: more doc fixes
Sebastien Bourdeauducq [Tue, 26 May 2015 06:13:13 +0000 (14:13 +0800)]
litesata: more doc fixes

9 years agoMerge branch 'master' of https://github.com/m-labs/misoc
Sebastien Bourdeauducq [Tue, 26 May 2015 05:57:26 +0000 (13:57 +0800)]
Merge branch 'master' of https://github.com/m-labs/misoc

Conflicts:
misoclib/mem/litesata/doc/source/docs/frontend/index.rst

9 years agolitesata: doc fixes
Sebastien Bourdeauducq [Tue, 26 May 2015 05:54:31 +0000 (13:54 +0800)]
litesata: doc fixes

9 years agoliteata: fix spelling & mistakes in doc
Florent Kermarrec [Tue, 26 May 2015 05:37:09 +0000 (07:37 +0200)]
liteata: fix spelling & mistakes in doc

9 years agolitesata: rework frontend doc and add striping, mirroring
Florent Kermarrec [Mon, 25 May 2015 12:04:37 +0000 (14:04 +0200)]
litesata: rework frontend doc and add striping, mirroring

9 years agolitesata: add mirroring
Florent Kermarrec [Mon, 25 May 2015 12:03:14 +0000 (14:03 +0200)]
litesata: add mirroring

9 years agolitesata/examples_designs: add striping
Florent Kermarrec [Mon, 25 May 2015 11:57:27 +0000 (13:57 +0200)]
litesata/examples_designs: add striping

9 years agolitesata/core/link: move buffer on CONTInserter (seems better for timings when set...
Florent Kermarrec [Mon, 25 May 2015 11:55:15 +0000 (13:55 +0200)]
litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink)

9 years agoliteusb/core/packet: fix missing ,
Florent Kermarrec [Mon, 25 May 2015 11:53:02 +0000 (13:53 +0200)]
liteusb/core/packet: fix missing ,

9 years agolitesata: add striping module for use of multiple HDDs.
Florent Kermarrec [Sat, 23 May 2015 12:12:20 +0000 (14:12 +0200)]
litesata: add striping module for use of multiple HDDs.

9 years agolitesata: do some cleanup and prepare for RAID
Florent Kermarrec [Sat, 23 May 2015 12:08:56 +0000 (14:08 +0200)]
litesata: do some cleanup and prepare for RAID

9 years agocores: replace Timeout with new WaitTimer
Florent Kermarrec [Tue, 12 May 2015 13:49:20 +0000 (15:49 +0200)]
cores: replace Timeout with new WaitTimer

9 years agouart: rename wishbone to bridge
Florent Kermarrec [Sat, 9 May 2015 14:24:28 +0000 (16:24 +0200)]
uart: rename wishbone to bridge

9 years agouart: remove litescope dependency for UARTWishboneBridge and remove frontend
Florent Kermarrec [Sat, 9 May 2015 13:48:54 +0000 (15:48 +0200)]
uart: remove litescope dependency for UARTWishboneBridge and remove frontend

9 years agoliteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)
Florent Kermarrec [Thu, 7 May 2015 18:03:55 +0000 (20:03 +0200)]
liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)

9 years agoliteusb/phy/ft245: rename "ftdi" clock domain to "usb"
Florent Kermarrec [Thu, 7 May 2015 18:03:12 +0000 (20:03 +0200)]
liteusb/phy/ft245: rename "ftdi" clock domain to "usb"

9 years agolitesata: fix packets figure in frontend doc
Florent Kermarrec [Thu, 7 May 2015 09:06:05 +0000 (11:06 +0200)]
litesata: fix packets figure in frontend doc

9 years agoREADME: add note about submodules
Sebastien Bourdeauducq [Thu, 7 May 2015 08:29:30 +0000 (16:29 +0800)]
README: add note about submodules

9 years agolitesata: add doc for frontend
Florent Kermarrec [Wed, 6 May 2015 01:51:02 +0000 (03:51 +0200)]
litesata: add doc for frontend

9 years agolitesata: cleanup README/doc
Florent Kermarrec [Wed, 6 May 2015 00:02:22 +0000 (02:02 +0200)]
litesata: cleanup README/doc

9 years agolitesata: use (some) settings from vivado 2015.1, try to follow all ug476 recommendat...
Florent Kermarrec [Tue, 5 May 2015 23:33:02 +0000 (01:33 +0200)]
litesata: use (some) settings from vivado 2015.1, try to follow all ug476 recommendations to initialize GTX (...), remove automatic reset on top.

Works fine @ 3Gbps, still not working @6.0Gbps

9 years agospiflash: fix miso bitbang with large DQ
Sebastien Bourdeauducq [Tue, 5 May 2015 16:05:25 +0000 (00:05 +0800)]
spiflash: fix miso bitbang with large DQ

9 years agosoc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment...
Florent Kermarrec [Mon, 4 May 2015 10:28:49 +0000 (12:28 +0200)]
soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment...

9 years agomisoclib/cpu: merge git.py in identifier
Florent Kermarrec [Sat, 2 May 2015 16:42:33 +0000 (18:42 +0200)]
misoclib/cpu: merge git.py in identifier

9 years agoliteusb: add simple example design with wishbone bridge and software to control it
Florent Kermarrec [Sat, 2 May 2015 15:39:22 +0000 (17:39 +0200)]
liteusb: add simple example design with wishbone bridge and software to control it

9 years agorename shadow_address to shadow_base (more appropriate) and use | instead of + (as...
Florent Kermarrec [Sat, 2 May 2015 14:57:32 +0000 (16:57 +0200)]
rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)

9 years agoliteeth/core/mac: minor cleanup
Florent Kermarrec [Sat, 2 May 2015 14:48:57 +0000 (16:48 +0200)]
liteeth/core/mac: minor cleanup

9 years agoliteusb/frontend/wishbone: use new packetized mode (allow grouping response in a...
Florent Kermarrec [Sat, 2 May 2015 14:15:58 +0000 (16:15 +0200)]
liteusb/frontend/wishbone: use new packetized mode (allow grouping response in a single packet)

9 years agolitescope/frontend/wishbone: add support for packetized mode
Florent Kermarrec [Sat, 2 May 2015 14:15:08 +0000 (16:15 +0200)]
litescope/frontend/wishbone: add support for packetized mode

9 years agoliteusb/software/wishbone: optimize writes/reads (send a single packet for a command)
Florent Kermarrec [Sat, 2 May 2015 13:25:40 +0000 (15:25 +0200)]
liteusb/software/wishbone: optimize writes/reads (send a single packet for a command)

9 years agodo more test with last changes fix small issues
Florent Kermarrec [Sat, 2 May 2015 12:26:19 +0000 (14:26 +0200)]
do more test with last changes fix small issues

9 years agoliteeth: move mac to core
Florent Kermarrec [Sat, 2 May 2015 10:55:51 +0000 (12:55 +0200)]
liteeth: move mac to core

9 years agocores: avoid having too much directories when possible (for simple cores or cores...
Florent Kermarrec [Sat, 2 May 2015 09:14:55 +0000 (11:14 +0200)]
cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)

9 years agouse similar names for wishbone bridges and move wishbone drivers to [core]/software
Florent Kermarrec [Sat, 2 May 2015 08:24:56 +0000 (10:24 +0200)]
use similar names for wishbone bridges and move wishbone drivers to [core]/software

9 years agotargets/pipistrello: add flash sizes
Zach Smith [Fri, 1 May 2015 18:41:37 +0000 (14:41 -0400)]
targets/pipistrello: add flash sizes