lkcl [Thu, 25 Mar 2021 21:42:20 +0000 (21:42 +0000)]
lkcl [Thu, 25 Mar 2021 21:40:07 +0000 (21:40 +0000)]
lkcl [Thu, 25 Mar 2021 21:39:35 +0000 (21:39 +0000)]
lkcl [Thu, 25 Mar 2021 21:37:56 +0000 (21:37 +0000)]
lkcl [Thu, 25 Mar 2021 21:36:55 +0000 (21:36 +0000)]
lkcl [Thu, 25 Mar 2021 21:32:18 +0000 (21:32 +0000)]
lkcl [Thu, 25 Mar 2021 21:23:04 +0000 (21:23 +0000)]
lkcl [Thu, 25 Mar 2021 21:21:09 +0000 (21:21 +0000)]
lkcl [Thu, 25 Mar 2021 21:20:47 +0000 (21:20 +0000)]
lkcl [Thu, 25 Mar 2021 21:13:04 +0000 (21:13 +0000)]
rwilbur [Thu, 25 Mar 2021 20:37:08 +0000 (20:37 +0000)]
programmerjake [Thu, 25 Mar 2021 18:57:54 +0000 (18:57 +0000)]
add cc
programmerjake [Thu, 25 Mar 2021 18:56:27 +0000 (18:56 +0000)]
fix typos
lkcl [Thu, 25 Mar 2021 18:51:02 +0000 (18:51 +0000)]
addw@fa2f8cb1790dfac204f803a3bfd8edda6ef3edc6 [Thu, 25 Mar 2021 16:52:20 +0000 (16:52 +0000)]
Note on open source status of LibreSOC work
addw@fa2f8cb1790dfac204f803a3bfd8edda6ef3edc6 [Thu, 25 Mar 2021 16:31:59 +0000 (16:31 +0000)]
lkcl [Thu, 25 Mar 2021 15:21:21 +0000 (15:21 +0000)]
lkcl [Thu, 25 Mar 2021 15:10:57 +0000 (15:10 +0000)]
lkcl [Thu, 25 Mar 2021 15:08:21 +0000 (15:08 +0000)]
lkcl [Thu, 25 Mar 2021 15:05:17 +0000 (15:05 +0000)]
lkcl [Thu, 25 Mar 2021 14:55:06 +0000 (14:55 +0000)]
lkcl [Thu, 25 Mar 2021 14:43:46 +0000 (14:43 +0000)]
lkcl [Thu, 25 Mar 2021 14:34:00 +0000 (14:34 +0000)]
Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 17:02:38 +0000 (17:02 +0000)]
add test html comment
lkcl [Sun, 21 Mar 2021 21:55:03 +0000 (21:55 +0000)]
lkcl [Sun, 21 Mar 2021 21:52:34 +0000 (21:52 +0000)]
lkcl [Sun, 21 Mar 2021 21:50:52 +0000 (21:50 +0000)]
lkcl [Sun, 21 Mar 2021 21:45:19 +0000 (21:45 +0000)]
lkcl [Sun, 21 Mar 2021 21:35:16 +0000 (21:35 +0000)]
lkcl [Sun, 21 Mar 2021 20:54:22 +0000 (20:54 +0000)]
lkcl [Sun, 21 Mar 2021 20:41:24 +0000 (20:41 +0000)]
lkcl [Sun, 21 Mar 2021 18:55:04 +0000 (18:55 +0000)]
lkcl [Sat, 20 Mar 2021 13:46:01 +0000 (13:46 +0000)]
lkcl [Sat, 20 Mar 2021 13:16:40 +0000 (13:16 +0000)]
lkcl [Sat, 20 Mar 2021 13:14:33 +0000 (13:14 +0000)]
lkcl [Sat, 20 Mar 2021 13:05:22 +0000 (13:05 +0000)]
lkcl [Sat, 20 Mar 2021 09:56:58 +0000 (09:56 +0000)]
lkcl [Sat, 20 Mar 2021 09:39:37 +0000 (09:39 +0000)]
lkcl [Sat, 20 Mar 2021 09:36:38 +0000 (09:36 +0000)]
lkcl [Sat, 20 Mar 2021 09:35:21 +0000 (09:35 +0000)]
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 18:36:33 +0000 (18:36 +0000)]
make dz consistent in SVP64
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 16:26:45 +0000 (16:26 +0000)]
destination zeroing higher priority than source zeroing
lkcl [Fri, 19 Mar 2021 13:30:47 +0000 (13:30 +0000)]
R Veera Kumar [Thu, 18 Mar 2021 23:18:54 +0000 (04:48 +0530)]
Update Name and RFP project
addw@fa2f8cb1790dfac204f803a3bfd8edda6ef3edc6 [Thu, 18 Mar 2021 14:46:50 +0000 (14:46 +0000)]
Collection of information about non openpower machines
Alain D D Williams [Thu, 18 Mar 2021 14:44:58 +0000 (14:44 +0000)]
Add a new section on non openpower machines
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 12:36:46 +0000 (12:36 +0000)]
update microwatt sv_decode.vhdl prototype with new sv_out2 column
lkcl [Thu, 18 Mar 2021 12:18:30 +0000 (12:18 +0000)]
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 12:15:22 +0000 (12:15 +0000)]
add cross-reference to bug #619 to make sure consistency is not lost
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 11:56:17 +0000 (11:56 +0000)]
argh really do not like adding autogenerated files
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 11:39:28 +0000 (11:39 +0000)]
add extra (fake) out2 column to RM SVP64 CSV output
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 11:21:22 +0000 (11:21 +0000)]
exclude setvl from SVP64 ReMap
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 11:21:05 +0000 (11:21 +0000)]
add option to create microwatt-formatted VHDL
lkcl [Wed, 17 Mar 2021 20:54:28 +0000 (20:54 +0000)]
lkcl [Wed, 17 Mar 2021 20:50:11 +0000 (20:50 +0000)]
lkcl [Wed, 17 Mar 2021 15:25:21 +0000 (15:25 +0000)]
lkcl [Wed, 17 Mar 2021 14:33:02 +0000 (14:33 +0000)]
lkcl [Wed, 17 Mar 2021 13:23:14 +0000 (13:23 +0000)]
rwilbur [Tue, 16 Mar 2021 22:48:24 +0000 (22:48 +0000)]
rwilbur [Tue, 16 Mar 2021 21:17:19 +0000 (21:17 +0000)]
rwilbur [Tue, 16 Mar 2021 21:08:33 +0000 (21:08 +0000)]
rwilbur [Tue, 16 Mar 2021 21:05:52 +0000 (21:05 +0000)]
rwilbur [Tue, 16 Mar 2021 20:52:07 +0000 (20:52 +0000)]
rwilbur [Tue, 16 Mar 2021 20:51:17 +0000 (20:51 +0000)]
rwilbur [Tue, 16 Mar 2021 20:45:16 +0000 (20:45 +0000)]
rwilbur [Tue, 16 Mar 2021 20:32:36 +0000 (20:32 +0000)]
rwilbur [Tue, 16 Mar 2021 20:31:56 +0000 (20:31 +0000)]
rwilbur [Tue, 16 Mar 2021 20:09:40 +0000 (20:09 +0000)]
rwilbur [Tue, 16 Mar 2021 19:55:14 +0000 (19:55 +0000)]
rwilbur [Tue, 16 Mar 2021 18:44:45 +0000 (18:44 +0000)]
lkcl [Tue, 16 Mar 2021 15:45:22 +0000 (15:45 +0000)]
lkcl [Tue, 16 Mar 2021 15:41:17 +0000 (15:41 +0000)]
lkcl [Tue, 16 Mar 2021 15:32:08 +0000 (15:32 +0000)]
lkcl [Tue, 16 Mar 2021 15:28:22 +0000 (15:28 +0000)]
lkcl [Tue, 16 Mar 2021 13:32:41 +0000 (13:32 +0000)]
lkcl [Tue, 16 Mar 2021 13:25:04 +0000 (13:25 +0000)]
lkcl [Tue, 16 Mar 2021 13:19:36 +0000 (13:19 +0000)]
lkcl [Tue, 16 Mar 2021 10:29:28 +0000 (10:29 +0000)]
lkcl [Tue, 16 Mar 2021 10:28:14 +0000 (10:28 +0000)]
lkcl [Tue, 16 Mar 2021 10:25:47 +0000 (10:25 +0000)]
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 16:08:39 +0000 (16:08 +0000)]
corrections to setvl from debugging
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 13:57:24 +0000 (13:57 +0000)]
expand SVi to 8 bits
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 12:19:28 +0000 (12:19 +0000)]
sigh have to remove spaces from pseudocode
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 12:08:34 +0000 (12:08 +0000)]
add simplev to isa pseudocode
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 11:35:56 +0000 (11:35 +0000)]
add Rc=1 version of setvl
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 11:35:17 +0000 (11:35 +0000)]
replace OPCD with PO (Primary Opcode)
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 11:34:14 +0000 (11:34 +0000)]
add first version setvl pseudocode
R Veera Kumar [Sat, 13 Mar 2021 02:08:21 +0000 (07:38 +0530)]
Update: Add completed project, remove from working.
Jacob Lifshay [Fri, 12 Mar 2021 21:57:01 +0000 (13:57 -0800)]
add minor_22.csv
with thanks for lkcl helping out over irc
lkcl [Fri, 12 Mar 2021 19:01:52 +0000 (19:01 +0000)]
addw@fa2f8cb1790dfac204f803a3bfd8edda6ef3edc6 [Fri, 12 Mar 2021 17:26:38 +0000 (17:26 +0000)]
Briefly say what ispc is
lkcl [Fri, 12 Mar 2021 16:55:05 +0000 (16:55 +0000)]
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 11:43:37 +0000 (11:43 +0000)]
stw/std/std/stb must be SRC-RA and SRC-RS
lkcl [Thu, 11 Mar 2021 21:47:56 +0000 (21:47 +0000)]
lkcl [Wed, 10 Mar 2021 23:29:32 +0000 (23:29 +0000)]
lkcl [Wed, 10 Mar 2021 23:26:56 +0000 (23:26 +0000)]
lkcl [Wed, 10 Mar 2021 18:13:40 +0000 (18:13 +0000)]
lkcl [Wed, 10 Mar 2021 18:11:23 +0000 (18:11 +0000)]
lkcl [Wed, 10 Mar 2021 18:10:50 +0000 (18:10 +0000)]
lkcl [Wed, 10 Mar 2021 16:39:33 +0000 (16:39 +0000)]
projects / libreriscv.git / log