util: Delete some Alpha related files from the m5 utility.

Change-Id: I5d751996d09459e79427851e80a4826e18f9db27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25459
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

util: Delete authors lists from files in util.

Change-Id: I2a165d3130c1464a73823046e4c7b03ba0355459
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25457
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

tests: Delete some test files which are specific to Alpha.

Change-Id: Idbffab70abdbb59817c6e002e26b8cb0fa96a4e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25458
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Remove mention of ALPHA from the README.

Change-Id: Ic0faf22e5ed94cf7e7591175a808c4696de29e25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25462
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Remove arch-alpha from the MAINTAINERS file.

This architecture no longer exists in gem5, and so doesn't need a
maintainer.

Change-Id: I41cfba1e60d24fd4016953addfb7933993bce98b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25461
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

scons: Remove mention of ALPHA from the SConstruct.

I've arbitrarily chosen to make ARM the default ISA for now, since I
think it's the best supported ISA with X86 somewhere a little behind
it. As a compromise, I change all mention of ALPHA (or even ALPHA_SE!)
in comments to be X86 instead, so it gets some attention too.

Change-Id: I1d8edc7925ca2d94f11b26e2c0b9314216e9b97d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25463
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Delete authors lists from shared include files.

Change-Id: I65d3d2e8df9799d9d3dc61734265a62b4dc9d67f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25456
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system: Delete authors lists from system source files.

Change-Id: I899bd4d04ad1cbf5ab32d57df88e2a146d2e2e4e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25455
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Delete authors lists from test files.

Change-Id: Id3628d34adccf8cc1044195b7209f3b01f061c93
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25454
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Delete authors lists from x86 files.

Change-Id: I7f842105e2c506664fd62d5f671f90db59e42c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25453
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Delete authors lists from sparc files.

Change-Id: Iac3f9bb546121c73e6e73a0377d2a917c40df5f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25452
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

riscv: Delete authors lists from riscv files.

Change-Id: I94135c8f0e1baee741d6470cb80b4da5e5f8e673
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25451
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Delete the authors lists from the power ISA.

Change-Id: Ib661723a9fcc09dd6e1e68a7c38a99e6d404dc46
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25450
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Delete authors lists from mips files.

Change-Id: I56c054c64fe3d1e39ed5d315b8ac78de2e993dc5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25449
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

hsail: Delete the author list from gpu_isa.hh.

Change-Id: I9c90fef4420286dbda7157d8961b4cf3c79a7c27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25448
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Delete authors lists from the arm files.

Change-Id: I6e9f5b70faebe5d279bff303c42f59a00a7845ec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25447
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Delete authors lists from the null arch files.

Change-Id: Ief42708d8961a5c33db5e8a603ee8fff8df8b198
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25446
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Delete authors lists from generic arch files.

Change-Id: I831a0f1876845f37ab12a2448e898719e74a0b55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25445
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

dev,mips: Delete a large binary file from src/dev/mips.

This file doesn't seem to actually get referred to by anything in gem5,
and additionally MIPS FS mode has a ways to go before it can be used.
If this file is really necessary for running MIPS, it can be retrieved
from the history in the future.

Change-Id: I3a86fc928a4be1c9159f0fafb986dfb06d09bb7b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25404
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Delete authors lists from files in sim.

Change-Id: I09a6117772c092157bf83701cf853145bb88ccf8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25411
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Delete authors lists from systemc files.

Change-Id: I6c6219732029d5a9db1d317c130086cf2d16a272
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25410
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Delete the authors list from files in src/dev.

Change-Id: I0907a6f1ada3038305c2d83a350a8d435ac657ba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25403
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Be more verbose on load/store construction

This is achieved by using keyword arguments to improve readibility.
Some of the building helpers are using native types and can be annoying
for a reader to understand what those sequences of number and boolean
mean. It is also easier in this way to commit mistakes.

Change-Id: I63081d09a1f621550c5b6522b8107f349939b21d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24044
Tested-by: kokoro <noreply+kokoro@google.com>

base: Use a int to store fgetc return value

The stdio fgetc returns the character read as an unsigned char cast to
an int.
The reason why it gets casted from unsigned char to int is because EOF
is defined as a negative value (usually -1).

At the moment in the atomicio.test we store the int in a char.

However the C standard states that the sign of a char is implementation
specific. This makes the test non portable: an architecture/ABI which
which is considering a char as a unsigned char won't compile since a
unsigned value will always be != -1 (EOF).

This is the error message you would get on a aarch64 host /w gcc/5.4.0

build/ARM/base/atomicio.test.cc:121:48:
error: comparison is always true due to limited range of data type
[-Werror=type-limits]

Change-Id: I120e44b5204d98e643f19b8dd6fa2762342a6e64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25384
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Delete authors lists from the cpu directory.

Change-Id: Icfba8e23b5f6820a6ddefe1a50abbe5f8825b7b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25444
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem: Delete authors lists from mem files.

Change-Id: I439d64d01950463747446a8177086eb276b8db55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25443
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

python: Delete authors lists from the python directory.

Change-Id: Ia147b90016f56a8ddd0c77b15746f74f50aba7e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25408
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

misc: Delete authors lists from proto.

Change-Id: I3ec4f28c82de2f006518ca276f761813d08d7977
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25407
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

learning-gem5: Delete authors lists from learning_gem5.

Change-Id: I42b6241057dab661aeaad695d48f62f70f163832
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25406
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

misc: Delete authors lists from documentation related files.

Change-Id: I6cd78336687c2516a90dba7c56154b03a709f791
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25405
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

cpu: Mark ExecContext::tcBase() as const

Change-Id: Ia3965c05a1b00e0a9738ddbccb4dc0b651f78e5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24523
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Delete authors lists from top level .md files.

Change-Id: Iefa9d6bd3ce0212bb3eb6101a73aeca737df2c1a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25417
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

config: Delete authors lists from config files.

Change-Id: I049f2e97ad00d76341c2aeeaa02279862a8a4d71
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25416
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

base: Delete authors lists from files in base.

Change-Id: I73020efd522489ee152af890ab5e03449bc0a900
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25415
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

gpu-compute: Delete authors lists from gpu-compute files.

Change-Id: I72318eb885f9517de325ea9a9af263f36613bf6e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25414
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

kern: Delete authors lists from files in kern.

Change-Id: Ic82d0172b61b5b84241edf1112148d7383aade97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25413
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

scons: Remove authors from the main SConsctruct/SConscript files.

Change-Id: I48987ea4d829e722caf16126dd82f2c580e7836a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25412
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

tests: Delete authors lists from the unittest directory.

Change-Id: Id4c7f5ddb932e427cb42d0698b1a048377d027c2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25409
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

alpha: Delete the alpha arch files.

Change-Id: If8f930c77e5f97156b42f68b3f8a538c8f8bf94c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24652
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Delete alpha loader components.

Change-Id: I228ff95af3fea04f8fb96486d5130abe1ab0228f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24651
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

dev: Delete alpha devices.

Change-Id: Idc41e83d94d39e8e45044a64b22b39cb395947c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24650
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

sim: Remove mention of alpha.

Change-Id: Iec6b9284383d380885955438c3693b0d2efc497e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24649
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

cpu: Remove alpha specialized code.

Change-Id: I770132af2f11ed232a100ab8bef942f17789ef36
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24648
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Remove mentions of alpha from the configs.

Change-Id: I09117b52c0c87679eaa72dbb79545dd1e77732b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24647
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

system: Delete alpha files from system.

Change-Id: I42b8ea34fb64b6dc7bdf3c09310011cfd989a7d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24646
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

scons: Delete the ALPHA default build configuration.

Change-Id: Ifbc0b6dd9b85e5a00ab11f16b2703b4ae946207e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24645
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updated git-commit-msg.py to print rejected commit

A rejected commit is now printed to stdout. This adds an additional
level of security if the ".git/COMMIT_EDITMSG" is deleted/overwritten.

Jira: https://gem5.atlassian.net/browse/GEM5-321
Change-Id: I87d463f7c40024d68bf78705f0d02fcea9f0eeeb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25343
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons,arch: Remove simple scalar compatibility.

This was primarily in Alpha where disassmbly output could be compatible
(default off, probably not usd in a long time), and floating point
could be compatible (default on). A small bit had crept into x86 from
long ago which is also removed.

Change-Id: Ibb68b63787f370259bd1613b393e0b057c007704
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25012
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Don't checkpoint the SystemCounter's "_period" value.

This value is just a cached inverse of _freq and can be recalculated
easily once the checkpoint is restored. The actual value of _period
actually depends on the global resolution of time (ie how much time a
Tick represents), and so saving the value of _period is also not
technically correct, even though in practice that will very rarely
cause a problem.

Change-Id: I21e63ba25ac4e189417905e532981f3d80723f19
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24390
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: "Correct" the spelling of flavor.

In US English, flavor is spelled flavor, not flavour. The choice of
US spelling is arbitrary but consistent with gem5's history and the
rest of the code base.

Also fix a couple small style issues.

Change-Id: I307f8458fec5918a6fc34f938a4c12955d4d0565
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25010
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,cpu: Make the CPU's ISA parameter type BaseISA.

This is mostly only a superficial change since the isa parameter is
then dynamic cast to the ISA specific version inside the various
consumers, currently the SimpleThread, O3CPU and Decoder classes. If
those aren't being used, for instance in the fast model CPUs, then you
can use a different ISA implementation without any type clashes.

Change-Id: I2226ef60f9a471ae51b8bfce8683033f7854197a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25009
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Add failure node to JUnit xml file

"failure" is a child of the testcase node:

https://llg.cubic.org/docs/junit/

It allows xml parsers to understand which testcase failed the run.
Otherwise CI frameworks like jenkins wouldn't be able to classify every
single testcase. Prior to this patch testlib was using
testsuites.failures and testsuite.failures only. These are simply
reporting the number of failures.

Change-Id: I0d498eca029c3232f2a588b153b6b6829b789394
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25083
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

misc: Updated CONTRIBUTING.md to discuss releases and hotfixes

A new section in CONTRIBUTING.md has been added to discuss the
proceedure for how releases are carried out, as well as hotfixes.

Jira: https://gem5.atlassian.net/browse/GEM5-297
Change-Id: I49e7d6e41e8a6d5387c839eb26263e86dd52c294
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24843
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updated CONTRIBUTING.md to discuss WIP changes

Previously CONTRIBUTING.md discused private changes, but contributors
cannot submit private changes to Gerrit under the current configuration.
This has therefore been removed and replaced with an explanation of how
to submit a WIP (Work In Progress) changes to Gerrit. WIP changes are
permitted.

Change-Id: I9e1acbdaf4a9b5c433c0704ba9faf325a6b48c6a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24805
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updated CONTRIBUTING.md for master-as-stable setup

Jira: https://gem5.atlassian.net/browse/GEM5-284
Change-Id: I28c4d658a2e9c3bf11879a7b73e16d167c97398f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24804
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Removed old contribution guidelines regarding branches

This is old, outdated information. It has largely been replaced by:
https://gem5-review.googlesource.com/c/public/gem5/+/24263

Change-Id: I2f232cd1b3133f94434f4f12b1206dabaf339899
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24803
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Eliminate the now unused GENERIC_IPR request flag.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Id3aaffa4fa88032fd209c5c3b6f67283a6af1c48
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23187
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Muhammad Sarmad Saeed <mssaeed@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch: Get rid of the generic mmapped IPR mechanism.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I4ab6f80581eee39e90fb91c672eca8e1a8fd9046
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23186
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arm: Call pseudoInst directly from the mmapped IPR handlers.

The amount of plumbing necessary for the generic IPR mechanism out
weighs its value, considering it's only used for the m5ops.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I0efcf43904d5f779bef5ad127dd8d39fff41ac39
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23185
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,misc: update TESTING.md documentation

* Documentation was assuming only tests in tests/test-progs were run.
This is not true anymore since we are running linux-boot for arm
which doesn't have a directory inside test-progs and because it
is now possible to explicitly specify the bin directory
(--bin-path)

Change-Id: I4cbb02fa1c88839be45302ea64e07792e1fc81f5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24526
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Fix an error about an unrecognized compiler.

join was being passed a series of strings to join as separate
arguments like os.path.join, but it expects to get them as members of a
single sequence.

Change-Id: Id88ce4e9c5400f256a1af6351b4a964af0036b72
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25203
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Fix squares of stats

If a sample V, which has a square(V) = V * V, was seen N times, then
its sum of squares is given by N * square(V).

Change-Id: Ie3fe0e4afe6e79ba4c8a5a56532f9346f79b4029
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25184
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Use a const auto & in a range based for loop.

clang 11 complains otherwise which breaks the build, and this way
is less verbose and more efficient since it doesn't require copying
a vector of strings for each element of the loop.

Change-Id: I005fa5fdf19ddba2114e98413e3609b0a91c1ec5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25226
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

riscv: Cast to float explicitly when comparing a float to an int.

clang 11 complains that the int value is not represented exactly
otherwise which breaks the build. With this case the comparison is
still the same, but since it's explicit the compiler doesn't warn about
it.

Change-Id: I1d9ffc77e778517d9c6a985ae7aa6c4f1d5b57a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25225
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Fix how a bitfield is extracted in some SVE instructions.

These instructions were extracting a bitfield by masking it, but then
didn't shift the bit into the correct position. They were then
comparing it with 1, which clang 11 correctly complained would always
be false. That warning became an error which broke the build.

This fixes that problem by switching that line and the few surrounding
lines to use the bits() function which removes the need to manually
mask or shift values. That makes it less likely for there to be a
mistake, and also makes it more obvious which bits are being accessed.

Change-Id: I692214f898e90dc7d5de460d1da2ef6aefda4fb8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25224
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Add a bunch of missing override specifiers.

Missing override on methods which are overriding virtual methods causes
warnings/errors on certain compilers.

Change-Id: I16f565fa07bfcb399a0209cd87f1f9729cd89b2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25223
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache,mem-ruby: Move WeightedLRU RP

Move the WeightedLRUReplacementPolicy to the replacement policies folder.

Change-Id: I9902faefb6de33343bb65f994be70bd9e1dd4e14
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22445
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests: hello_se using host tag

This patch is rewriting hello_se to distinguish between statically and
dynamically linked hello worlds.

Change-Id: I03c1add1d1ca568d150f4bacd89b2838a6d27035
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24528
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

tests: Add --host tag

A host tag has been added to take into consideration the host ISA which
is running gem5 (default is X86).
There might be regressions which are supposed to be run on a particular
host machine only. This could be the case of dynamically linked
regressions which require dynamic linker/loader + shared libraries of
the same ISA as the target.

Change-Id: I4c4044a4f1b8899f443856340df302df7c1aaf8e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24527
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Using VExpress_GEM5_V1 as a default for Options.py

This is replacing deprecated VExpress_EMM for scripts using Options.py,
like fs.py.

Change-Id: I2ba01b248bb9baf49e1f2217d623f3b9bc8a35f9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25183
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: LDTRSW was not marked as unpriviledged

Change-Id: If0f2b835e40ef011eba884b1dcd81f14531fd1ce
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24043
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

systemc: gem5_to_tlm: treat non-rw as ignorable command

Treat all kinds of non read/write requests in gem5_to_tlm bridge as ignorable
commands.

Change-Id: I5236e1b31f9a57470dc666d01cbe96249f48ed5d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25163
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,sim: Replace setuidFunc with ignoreFunc.

The setuidFunc just ignores the call and warns about it, and that's
what ignoreFunc already does.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I7655863ed6fe200ff3ac087be3218d49c3c43061
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23194
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Convert most of the common syscalls to use the guest ABI.

A couple tricky instances were left alone for now, specifically one
place where the size of the argument is specified explicitly (the
default ABI always leaves off the size), and two places where the
arguments are variadic which is not yet supported.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I2ec19bea77d329de3575e17e9f7209f4fd871aa6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23193
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Use the Guest ABI mechanism in writeFunc.

This change only modifies the writeFunc since it's easy to test using
the hello world test programs.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ia4a7bacdb9938d9fbe4093fc6958904d6c423360
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23192
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Switch SyscallDescABI in for SyscallDesc.

This lets system calls accept arguments by putting them in their
signatures.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ieb32b8b5592d894e493466717613ff16e2a03768
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23191
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a transitional syscall ABI which defers to Process.

This change adds a transitional ABI which just falls back to the
existing Process syscall arg getters. It should be phased out once each
ISA implements its own actual ABI.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ic40bd924989f91de70bbce59fda888b79bbbfca4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23190
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Simplify the SyscallDesc tables.

By using braced initializer lists and dropping the default
unimplementedFunc implementation function, the SyscallDesc tables
become a lot less crowded, and it's now very obvious which syscalls
are implemented just by quickly visually scanning the table.

This will also make it a lot easier to change the underlying type
stored in the table without having to adjust all of the instances
within them.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I7821de74812e1c02ca4550fc9c46cc2188cf1bd0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23189
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Handle m5 op accesses directly in the mmapped IPR handlers.

The common handlers only handle the m5ops, and it takes more plumbing
to get to them than to just handle the m5ops directly from x86.

Also, centralizing the call to PseudoInst::pseudoInst prevents
specializing the ABI per-ISA.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ife9cf0d61ac87605ddc9cf9c84feebb8b23cc33a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23184
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a function for decoding the field(s) of an m5op address.

These have at one time included both a func and subfunc, although the
subfunc was unused and is now excluded.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ic35ced7a012aa72af5454768f3cbd11b431b061a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23183
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Marjan Fariborz <mfariborz@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

x86: Use the m5 op range in the system.

Don't hard code a range into the TLB.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I0ead4353672ccf6e3e51ddbb4676be3a09f1136a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23182
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch,sim: Use _m5opRange in System::allocPhysPages.

This removes the hardcoded assumption that the m5 ops live at the
address they use in x86.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ia551d7cf5b08f926c7756541c92a2af9bb73b88a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23181
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a typetraits style mechanism to test for VarArgs.

This family of types can be cumbersome to check for when building
ABI rules. This struct template makes that a little easier.

Change-Id: Ic3a1b8424f8ca04564f8228365371b357f33276c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23750
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch-arm: Implement ARMv8.3-JSConv

This commit implements Armv8 javascript float point convertion instructions
VJVCT and FJCVTZS.

Change-Id: I1b24839daef775bbb1eb9da5f32c4bb3843e0b28
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25023
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: This commit adds Pointer Authentication feature.

+ ArmISA.py: Enabling the feature adding  QARMA algorithm as default.
+ faults.cc/faults.hh: Add PACTrapFault
+ includes/insts.isa: Adding new isa files.
+ aarch64.isa: Add decode part for PAC instructions
+ pauth.isa: Isa for PAC instructions
+ misc64.isa: PAC instructions templates
+ miscregs.cc/hh/types: New Registers for PAC Key low/high.
+ types.hh: Modification of system registers that were incomplete
            for ARMv8
+ utility.hh: Add isSecureEL2 enabled. The function is there but will
              always return false for now.
+ pauth_helpers.hh/cc: Implementation of auxiliar functions and derivates.
+ qarma.hh/cc: This functions follow ARMv8 reference pseudo code
              implementing QARMA block cipher algorithms.

Change-Id: I3095a1279204206d9a816a4fb7fc176c18f9680b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25024
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Move old quick regressions back into their original set

realview64-simple-atomic and realview64-simple-timing had been moved
to the long list by:

https://gem5-review.googlesource.com/c/public/gem5/+/22686

in order to reduce computation time.
Since the timeout has been increased on kokoro we can safely put them
back where they were

Change-Id: Ib86f02b8ef493f450509b9f826a80faaec9ef579
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25025
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Make it possible for a GuestABI to init its Position based on a TC.

It may be necessary to initialize the GuestABI Position type based on
the current state of the thread, for instance by reading the current
stack pointer.

This change makes it possible (but not mandantory) for an ABI to supply
a constructor for Position which accepts a ThreadContext * which it can
use to intiialize itself.

Change-Id: I5609b185f746368c5f9eb2a04074dcafa088f925
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23749
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Ensure unset vec reg bits are zero/false.

These bits won't be overwritten with values from IRIS, and so we should
make sure they're cleared and don't have old values or junk.

Change-Id: Ib81780ab523f00d6a4d31841d68a3d83924982a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24327
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Implement flattened int reg reading and writing.

Because the fast models (or at least the one we've looked at) give
access to the integer registers mostly based on the current view of
those registers, it does its own flattening and prevents accessing most
of the raw storage locations without this extra level of mapping. To
store to the flattened locations, we need to unflatten the indexes and
in one case shift the mode so that we get the right values.

Some registers which have irrelevant values for fast model (the "PC"
which is actually diverted elsewhere, the zero register, microcode
registers, and the "dummy" register), and those are left out of the
mapping so that they return 0 and blow up gem5 when someone attempts to
set them.

Change-Id: Ia2d315d5ca4c8a65b17ad52beff3a366ca8b3d46
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23791
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: make MicroUopSetPCCPSR SerializeAfter

Updating CPSR needs to be SerializeAfter to ensure that all following
instructions are executed with the new CPSR. Otherwise, for example,
the following instructions will access the banked registers from the
previous mode.

The missing IsSerializeAfter had the consequence that the instruction
rfe (return from exception) did not work correctly with the DerivO3CPU
model.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-303

Change-Id: I999623c0fc92cfcd4c3550b9cb34e8564a92e3e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24943
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
(cherry picked from commit 0d665d4f9893320db4f3b5f7014a6e10c3420b69)
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25013
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

cpu: Make getIsaPtr return a BaseISA pointer.

This isolates the architecture specific ISA types a little bit, and
means that ThreadContexts don't *have* to find an architecture specific
class to return, even if they don't naturally have one lying around.

Change-Id: Ide10b5d945ec6076947b2ccdea87c86e96e40857
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25008
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch: Introduce a base class for ISA classes.

These don't have anything in them at the moment since making some ISA
methods virtual and not inlined will likely add overhead, specifically
the ones for flattening registers. Some code may need to be rearranged
to minimize that overhead before the ISA objects can be truly put
behind a generic interface.

Change-Id: Ie36a771e977535a7996fdff701ce202bb95c8c58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25007
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

arm: Use static_cast to get access the ARM specific ISA functions.

Change-Id: I8d237fa60c0fc17c97ed351afd0fa3c623262f0d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25006
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: AArch64 reg access HCR_EL2.E2H filter

Some AArch64 system registers report UNDEFINED behaviours if accessed
from EL2 or EL3 in a non-EL2 Host enabled (HCR_EL2.E2H == 0) environment.
Examples of these are seen in the Generic Timer system registers,
namely CNTP_CTL_EL02 or CNTKCTL_EL12.
This patch provides an ISA filter for specifying the above condition.

Change-Id: I240f9afdb000faf5d3c9274ba12bd4cc41fe8604
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24664
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: reg access permissions highest EL helper

This patch implements a helper function to filter a register access
permissions by the highest EL implemented by the system.
This filtering is convenient to follow the architecture pseudocode.

Change-Id: Iedfb2d8624c926f2f0a9326f8b1b073ea9424ab9
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24663
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Split translateFs to distinguish when MMU is on/off

This patch is splitting the big translateFs method so that it is
using different methods when the MMU is on/off

Change-Id: I198851bdbedf8a8e69730693ff87ffb9ed535ea3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24985
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,sim: Merge initCPU into the ISA System classes.

Those classes are already ISA specific, so we can just move initCPU's
contents there and take it out of utility.hh, utility.cc, and the base
System's initState.

Change-Id: I28f0d0b50d83efe5116b0b24d20f8182a02823e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24905
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,sim: Merge initCPU and startupCPU.

These two functions were called in exactly one place one right after
the other, and served similar purposes.

This change merges them together, and cleans them up slightly. It also
removes checks for FullSystem, since those functions are only called
in full system to begin with.

Change-Id: I214f7d2d3f88960dccb5895c1241f61cd78716a8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24904
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim,cpu: Move the call to initCPU into System.

The call to initCPU was moved into initState in the base CPU class
since it should only really be called when starting a simulation
fresh. Otherwise checkpointed state will be loaded over the state of
the CPU anyway, so there's no reason to set up anything else.

Unfortunately that made it possible for the System level initialization
and the CPU initialization to happen out of order, effectively letting
initCPU clobber the state the System might have set up to prepare for
executing a kernel for instance.

To work around that issue, the call was moved to init which would
necessarily happen before initState, restoring the original ordering.

This change moves the change *back* into initState, but of the System
class instead of the CPU class. This makes it possible to guarantee
that OS initialization happens after initCPU since that's also done
by System subclasses, and they control when they call initCPU of the
base class.

This also slightly simmplifies when initCPU is called since we
shouldn't need to check whether a context is switched out or not. If
it's registered with the System object, then it should be in a
currently swapped in CPU.

This also puts the initCPU and startupCPU calls right next to each
other. A future change will take advantage of that and merge the
calls together.

Also, because there are already ISA specific subclasses of System
which already have specialized versions of initState, we should be
able to move the code in initCPU and startupCPU directly into those
subclasses. That will give those subclasses more flexibilty if, for
instance, they want all CPUs to start running in the BIOS like they
would on a real system, or if they want only the BSP to be active
as if the BIOS had already paused the APs before passing control to
a bootloader or OS.

This will also remove another two TheISA:: style functions, reducing
the number of global dependencies on a single ISA.

Change-Id: Ic56924660a5b575a07844a198f69a0e7fa212b52
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24903
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,base,cpu: Add some default constructors/operators explicitly.

Having them implicitly is apparently deprecated and throws a warning
in gcc 9, breaking the build.

Change-Id: Id4e3074966d1ffc6dd1aed9397de5eea84400027
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24926
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>