Anuj Phogat [Thu, 18 Apr 2013 23:31:35 +0000 (16:31 -0700)]
mesa: Implement ext_framebuffer_multisample_blit_scaled extension
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Kenneth Graunke [Thu, 30 May 2013 06:27:45 +0000 (23:27 -0700)]
Revert "i965: fix problem with constant out of bounds access (v2)"
This reverts commit
98dfd59a0445666060c97b0dccaf0e9f030b547a.
The patch was clearly not Piglit tested, as it caused at least 225
tests to start crashing with assertion failures. That was before my
desktop tanked and the test run died completely.
Courtney Goeltzenleuchter [Tue, 28 May 2013 15:54:43 +0000 (09:54 -0600)]
ilo: simplify shader variant handling
Remove hash function on shader variants. Nature of variants limits them to a
small number and thus its more efficient to just do a memory compare of the
actual shader structures rather than compute and compare hashes.
Dave Airlie [Wed, 29 May 2013 23:51:41 +0000 (09:51 +1000)]
i965: fix problem with constant out of bounds access (v2)
This is my attempt at fixing this as the CVE is making RH security team
care enough to make me look at this. (please upstream, security fixes are
more important than whatever else you are doing, if for no other reason than
it saves me having to fix stuff I've no real clue about).
Since Frank's original fix was denied, here is my attempt to just
alias all constants that are out of bounds < 0 or > nr_params to constant 0,
hopefully this provides the undefined behaviour idr requires..
CVE-2013-1872
v2: drop the last hunk which was a separate fix (now in master).
hopefully fix the indentations.
NOTE: This is a candidate for stable branches.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Frank Henigman [Tue, 29 Jan 2013 01:06:59 +0000 (20:06 -0500)]
intel: initialize fs_visitor::params_remap in constructor
Set fs_visitor::params_remap to NULL in the constructor.
This variable was potentially tested in fs_visitor::remove_dead_constants()
before being set.
NOTE: This is a candidate for stable release branches.
Signed-off-by: Frank Henigman <fjhenigman@google.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Brian Paul [Thu, 30 May 2013 00:07:35 +0000 (18:07 -0600)]
draw: add cast in debug_printf() to silence warning
Brian Paul [Thu, 30 May 2013 00:07:11 +0000 (18:07 -0600)]
svga: add PIPE_CAP_MAX_VIEWPORTS to switch to silence warning
Zack Rusin [Sat, 25 May 2013 05:46:16 +0000 (01:46 -0400)]
draw: make sure viewport index is fetched from leading vertex
Viewport index should only be used on a per primitive basis, so
instead of fetching it from each vertex, potentially making each
vertex in a primitive use a different viewport index, which is
obviously broken, make sure that we only fetch from the first
vertex in the primitive making the viewport index the same
for the entire primtive.
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca<jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Zack Rusin [Sat, 25 May 2013 05:04:17 +0000 (01:04 -0400)]
llvmpipe: clamp scissors to be between 0 and max
We need to clamp to make sure invalid shader doesn't crash our
driver. The spec says to return 0-th index for everything that's
out of bounds.
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca<jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Zack Rusin [Sat, 25 May 2013 05:02:46 +0000 (01:02 -0400)]
draw: clamp the viewports to always be between 0 and max
If the viewport index is larger than the PIPE_MAX_VIEWPORTS,
then the first (0-th) viewport should be used.
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca<jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Zack Rusin [Sat, 25 May 2013 13:14:57 +0000 (09:14 -0400)]
gallium/docs: adds documentation for multi viewport cap
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Zack Rusin [Fri, 24 May 2013 20:39:59 +0000 (16:39 -0400)]
draw: fixup draw_find_shader_output
draw_find_shader_output like most of the code in draw used to
depend on position always being at output slot 0. which meant
that any other attribute being at 0 could signify an error.
unfortunately position can be at any of the output slots, thus
other attributes can occupy slot 0 and we need to mark the ones
which were not found by something else. This commit changes
draw_find_shader_output so that it returns -1 if it can't
find the given attribute and adjust the code that depended
on it returning >0 whenever it correctly found an attrib.
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca<jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Zack Rusin [Fri, 24 May 2013 20:28:19 +0000 (16:28 -0400)]
llvmpipe: implement support for multiple viewports
Largely related to making sure the rasterizer can correctly
pick out the correct scissor box for the current viewport.
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca<jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Zack Rusin [Fri, 24 May 2013 20:17:26 +0000 (16:17 -0400)]
draw: implement support for multiple viewports
This adds support for multiple viewports to the draw module.
Multiple viewports depend on the presence of geometry shaders
which can write the viewport index.
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca<jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Zack Rusin [Fri, 24 May 2013 20:08:39 +0000 (16:08 -0400)]
gallium: Add support for multiple viewports
Gallium supported only a single viewport/scissor combination. This
commit changes the interface to allow us to add support for multiple
viewports/scissors.
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: José Fonseca<jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Kenneth Graunke [Wed, 29 May 2013 15:31:54 +0000 (08:31 -0700)]
mesa: Delete the ctx->Array._RestartIndex derived state.
It's incorrect and isn't used any longer.
v2: Actually flush vertices/flag _NEW_TRANSFORM on RestartIndex change.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Wed, 29 May 2013 15:29:26 +0000 (08:29 -0700)]
mesa: Ignore fixed-index primitive restart in ArrayElement().
GL_PRIMITIVE_RESTART_FIXED_INDEX is only supposed to apply to
glDrawElements*. This code is for legacy drawing paths and display
lists, so it shouldn't apply.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Wed, 29 May 2013 14:57:34 +0000 (07:57 -0700)]
st/mesa: Go back to using ctx->Array.RestartIndex, not _RestartIndex.
The derived _RestartIndex field is an attempt to support both
GL_PRIMITIVE_RESTART and GL_PRIMITIVE_RESTART_FIXED_INDEX (part of ES
3.0). Gallium drivers don't appear to support ES 3.0 yet, so they don't
need to use it. Plus, it's broken and going to go away soon.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Sat, 25 May 2013 17:17:32 +0000 (10:17 -0700)]
i965: Fix can_cut_index_handle_restart_index() for byte/short types.
Pre-Haswell hardware doesn't support an arbitrary restart index, and
instead compares the index buffer value against 0xFF for byte-size
buffers, 0xFFFF for short-size buffers, or 0xFFFFFFFF for unsigned
integer buffers.
OpenGL allows the restart index to be an arbitrary unsigned integer.
When comparing against byte/short types, the index buffer value should
be promoted to a full 32-bit integer before doing the comparison. The
restart index is /not/ supposed to be masked to byte/short size.
This means that with certain restart indexes, the comparison should
always fail. For example, a restart index of 0xF000FFFF should never
match any byte/short index buffer values due to the extra high bits.
We must not enable hardware primitive restart in such a case. For now,
fall back to software primitive restart as it's the simplest fix. In
the future, we could detect restart indexes that will never match and
skip both hardware and software primitive restart.
NOTE: This is a candidate for stable branches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Fri, 24 May 2013 16:28:56 +0000 (09:28 -0700)]
i965: Use the correct restart index for fixed index mode on Haswell.
The code that updates the ctx->Array._RestartIndex derived state mashed
it to 0xFFFFFFFF when GL_PRIMITIVE_RESTART_FIXED_INDEX was enabled
regardless of the index buffer type. It's supposed to be 0xFF for byte,
0xFFFF for short, or 0xFFFFFFFF for integer types.
The new _mesa_primitive_restart_index() helper gets this right.
The hardware appears to compare against the full 32-bit value some of
the time, causing primitive restart not to occur when it should. The
fact that it works some of the time is rather frightening.
Fixes sporadic failures in the ES 3 instanced_arrays_primitive_restart
conformance test when run in combination with other tests.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Wed, 29 May 2013 15:21:14 +0000 (08:21 -0700)]
vbo: Use the new primitive restart index helper function.
This gets the correct restart index for unsigned byte/short types when
using GL_PRIMITIVE_RESTART_FIXED_INDEX.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Wed, 29 May 2013 15:07:01 +0000 (08:07 -0700)]
mesa: Add a helper function for determining the restart index.
The derived state approach currently used (_RestartIndex) doesn't work:
in the GL_PRIMITIVE_RESTART_FIXED_INDEX case, the restart index depends
on the index buffer's data type, and that isn't known until draw time.
The existing code also fails to obey the GL 4.3 rules which say that
FIXED_INDEX takes precedence over normal primitive restart.
This helper function correctly determines the restart index, and will
replace the derived state.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Sat, 25 May 2013 15:19:40 +0000 (08:19 -0700)]
vbo: Ignore PRIMITIVE_RESTART_FIXED_INDEX for glDrawArrays().
The derived _PrimitiveRestart enable flag combines the PrimitiveRestart
and PrimitiveRestartFixedIndex enable flags. However, DrawArrays is not
supposed to do FixedIndex restart:
From the OpenGL 4.3 Core specification, section 10.3.5 (page 302):
"If PRIMITIVE_RESTART_FIXED_INDEX is enabled, primitive restart is not
performed for array elements transferred by any drawing command not
taking a type parameter, including all of the *Draw* commands other
than *DrawElements*."
The OpenGL ES 3.0 specification agrees by omission:
"When DrawElements, DrawElementsInstanced, or DrawRangeElements
transfers a set of generic attribute array elements to the GL..."
Notably, DrawArrays is not included in the list of draw calls that
take PRIMITIVE_RESTART_FIXED_INDEX into consideration.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Tue, 28 May 2013 21:35:19 +0000 (14:35 -0700)]
i965/vs: Fix implied_mrf_writes() for integer division pre-gen6.
Previously it would assertion fail in debug builds (though the correct
value was returned in a non-debug build). Marking it as a candidate for
stable even though it has no current consumers in the stable branches, in
case one shows up in a later backport.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64727
NOTE: This is a candidate for stable branches.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Fri, 3 May 2013 00:44:28 +0000 (17:44 -0700)]
i965/fs: Fix test for smearing enabled on an instruction.
We were expanding the live range too far, breaking register_coalesce_2()
and compute_to_mrf() on 16-wide shaders. Turning it back on improves
GLB2.7 performance by 0.239355% +/- 0.
0850649% (n=398). shader-db stats
are:
total instructions in shared programs:
1627211 ->
1609262 (-1.10%)
instructions in affected programs: 450351 -> 432402 (-3.99%)
While 33 new 16-wide shaders are gained, 70 are lost. Despite that,
tropics (the app that lost the most 16-wide) shows a .41% +/- .16%
(n=7/8, first-run outlier removed) performance improvement on my HSW.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Thu, 9 May 2013 16:00:11 +0000 (09:00 -0700)]
i965/fs: Fix segfault in instruction scheduling with LINTERP using last GRF.
The scheduler didn't know about uniform-type accesses, and if a uniform
access was last in a 16-wide, we'd walk off the end of the array. This
never happened, because we'd never coalesce out all the GRFs, due to a bug
to be fixed in the next commit.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Mon, 6 May 2013 20:47:27 +0000 (13:47 -0700)]
mesa: Fix test for optimistic coloring being necessary.
i965 and radeon use ra_set_node_reg() to force payload registers to
specific registers while exposing those registers to the allocator still.
We were treating those register nodes as unsuccessfully allocated in the
ra_simplify() step, leading to walking the registers again to do
optimistic coloring even if there was nothing left ot do.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Anthony G. Basile [Tue, 28 May 2013 22:58:10 +0000 (22:58 +0000)]
gallium: fix build on uclibc system
execinfo.h and debug_symbol_name_glibc() are pure GNU-isms and do not
build on uclibc systems. A previous patch addressed this issue, but
there was an error. This patch corrects that error. See
https://bugs.freedesktop.org/show_bug.cgi?id=51782
https://bugs.gentoo.org/show_bug.cgi?id=469768
Signed-off-by: Anthony G. Basile <blueness@gentoo.org>
Signed-off-by: Brian Paul <brianp@vmware.com>
Eric Anholt [Tue, 28 May 2013 17:59:53 +0000 (10:59 -0700)]
intel: Enable blit glCopyTexSubImage/glBlitFramebuffer with sRGB.
Since the introduction of default-to-SARGB8 window system framebuffers,
non-blorp hardware lost blit acceleration for these two paths between the
window system and ARGB8888 textures. Since we shouldn't be doing any
conversion anyway, just compatibility-check the linear variants of the
formats.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61954
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Andreas Hartmetz [Tue, 28 May 2013 21:59:41 +0000 (23:59 +0200)]
radeonsi: Add ipo to LLVM_COMPONENTS
r600g needs it too, so add ipo in the common radeon_llvm_check().
radeonsi compiled and linked, but it failed at dynamic link time
with a missing symbol.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Roland Scheidegger [Tue, 28 May 2013 00:34:27 +0000 (02:34 +0200)]
llvmpipe: get rid of tiled/linear layout remains
Eliminate the rest of the no longer needed layout logic.
(It is possible some code could be simplified a bit further still.)
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Eric Anholt [Fri, 24 May 2013 19:50:11 +0000 (12:50 -0700)]
intel: Remove dead intel_drawbuf_region().
Since the glBitmap() MRT change, it's unused. There was basically no way
to responsibly use this function since MRT was introduced.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Fri, 24 May 2013 19:48:47 +0000 (12:48 -0700)]
intel: Fix format handling of blit glBitmap()
Any 32-bit format got ARGB8888 handling (including, say, GL_RG1616), and
anything else got 16-bit (including, say, GL_R8), which could potentially
hang the GPU by writing out of bounds.
NOTE: This is a candidate for the stable branches.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Fri, 24 May 2013 19:40:14 +0000 (12:40 -0700)]
intel: Fix MRT handling of glBitmap().
We'd only hit color buffer 0 even if multiple draw buffers were bound.
NOTE: This is a candidate for the stable branches.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Fri, 24 May 2013 18:42:10 +0000 (11:42 -0700)]
intel: Rebuild PBO blit glTexImage() on top of miptrees.
This will ensure that we have resolves if we ever extend this to
glTexSubImage(), and fixes missing image start offset handling.
The texture buffer alloc ended up getting moved up, because we want to
look at the format of the image's actual mt to see if we'll end up
blitting the right thing, in the case of packed depth/stencil uploads.
This is the last caller of intelEmitCopyBlit() on a miptree-wrapped BO.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Fri, 24 May 2013 18:10:37 +0000 (11:10 -0700)]
intel: Rebuild PBO blit glReadPixels() on top of miptrees.
The previous code was missing depth resolves, that had only been prevented
due to no blitting of Y tiling. The pair of flip args in the new blit
function means that we can just drop the pack->Invert fallback.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Fri, 24 May 2013 17:54:36 +0000 (10:54 -0700)]
intel: Rework intel_miptree_create_for_region() to wrap a BO.
I needed to do this for the PBO blit cases to use intel_miptree_blit().
But this also actually partially fixes a bug in EGLImage handling: We
can't share regions across contexts, because regions have a refcount that
isn't protected by a mutex, and different contexts can be simulataneously
accessed from multiple threads. Now we just need to get regions out of
__DRIImage. There was also a missing use of image->offset in the EGLImage
renderbuffer storage code.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Thu, 23 May 2013 23:58:58 +0000 (16:58 -0700)]
intel: Make a temporary miptree for the blit path of miptree mapping.
In a bit of debug code, we no longer have the inter-slice x/y to print.
But I think the level/slice is more useful in this case for looking at
what's getting mapped, especially given that INTEL_DEBUG=blit will tell
you the other value.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Thu, 23 May 2013 21:16:15 +0000 (14:16 -0700)]
intel: Make a temporary miptree when doing blit uploads for glTexSubImage().
While this is a bit more CPU work, it also is less code to handle this
path, and fixes problems with 32k-pitch textures and missing resolves.
v2: Add error checking in new code.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Thu, 23 May 2013 23:08:22 +0000 (16:08 -0700)]
intel: Extend the force_y_tiling flag to allow forcing no tiling.
For a blit-uploaded temporary, it's faster on current hardware to memcpy
the data into a linear CPU mapping than to go through the GTT.
v2: Turn the not-fully-supported mask into 3 supported enum values.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Reviewed-by: Paul Berry <stereotype441@gmail.com> (v2)
Reviewed-by: Chad Versace <chad.versace@linux.intel.com> (v2)
Eric Anholt [Fri, 24 May 2013 20:37:13 +0000 (13:37 -0700)]
intel: Add an assert for glCopyTexSubImage() being called on MSAA buffers.
This is just in case someone else trips over this due to our weird reuse
of this code in glBlitFramebuffer().
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Thu, 23 May 2013 20:40:26 +0000 (13:40 -0700)]
i965: Allow glCopyTexSubImage() on depth textures.
If the hw is pre-gen5 and can't blit depth, it'll cleanly error out.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Thu, 23 May 2013 23:43:58 +0000 (16:43 -0700)]
i965: Prefer blorp glBlitFramebuffer() to the glCopyTexSubImage-based blit.
I think we've measured no performance difference from this in the past,
except that the blorp code can do things like multisample resolves.
Prevents piglit regression in the next commit when a testcase started
trying to do a multisampled resolve through the old glCopyTexSubImage()
path.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Thu, 23 May 2013 20:36:26 +0000 (13:36 -0700)]
i965: Consistently do depth resolves before blitting.
We were protected for a long time by the fact that depth was Y tiled and
you couldn't blit Y. Now that we can blit Y, we were failing to resolve
depth in glCopyPixels().
Note in the comment about swrast, that the swrast map path does resolves
appropriately already.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Mon, 4 Feb 2013 22:24:09 +0000 (14:24 -0800)]
intel: Make a wrapper for intelEmitCopyBlit using miptrees.
I had previously asserted that it was hard to write a useful, simpler
blit function, but I think this might be it.
This has the side effect of extending the 32k pitch check to a few more
places that were missing it.
v2: Update comment for being moved inside intel_miptree_blit().
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Mon, 4 Feb 2013 22:21:24 +0000 (14:21 -0800)]
intel: Rename intel_renderbuffer_tile_offsets.
This makes it more consistent with intel_miptree_get_tile_offsets().
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Mon, 4 Feb 2013 18:05:51 +0000 (10:05 -0800)]
intel: Reduce intel_renderbuffer_tile_offsets to a thin wrapper.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
Eric Anholt [Mon, 4 Feb 2013 18:00:10 +0000 (10:00 -0800)]
intel: Make intel_miptree_get_tile_offsets return a page offset.
Right now, the callers in i965 don't expect a nonzero page offset to
actually occur (since that's being handled elsewhere), but it seems
like a trap to leave it this way.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Paul Berry <stereotype441@gmail.com>
José Fonseca [Tue, 28 May 2013 12:56:18 +0000 (13:56 +0100)]
glsl: Fix MSVC build.
It appears that `sizeof(Class::member)` is either non-standard or
merely unsupported in MSVC.
So use `sizeof(instance->member)` instead, which is guaranteed to work
everywhere.
Also promote the assert to a static assert.
Trivial.
Marek Olšák [Mon, 13 May 2013 13:46:49 +0000 (15:46 +0200)]
mesa: fix GLSL program objects with more than 16 samplers combined
The problem is the sampler units are allocated from the same pool for all
shader stages, so if a vertex shader uses 12 samplers (0..11), the fragment
shader samplers start at index 12, leaving only 4 sampler units
for the fragment shader. The main cause is probably the fact that samplers
(texture unit -> sampler unit mapping, etc.) are tracked globally
for an entire program object.
This commit adapts the GLSL linker and core Mesa such that the sampler units
are assigned to sampler uniforms for each shader stage separately
(if a sampler uniform is used in all shader stages, it may occupy a different
sampler unit in each, and vice versa, an i-th sampler unit may refer to
a different sampler uniform in each shader stage), and the sampler-specific
variables are moved from gl_shader_program to gl_shader.
This doesn't require any driver changes, and it fixes piglit/max-samplers
for gallium and classic swrast. It also works with any number of shader
stages.
v2: - converted tabs to spaces
- added an assertion to _mesa_get_sampler_uniform_value
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Marek Olšák [Mon, 13 May 2013 14:24:57 +0000 (16:24 +0200)]
swrast: increase array size of TextureSample
to match the size of ctx->Texture.Unit, and it will also fix
piglit/max-samplers with the following commit.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Marek Olšák [Tue, 14 May 2013 15:58:32 +0000 (17:58 +0200)]
mesa: declare UniformBufferBindings as an array with a static size
Some Gallium drivers were crashing, because the array was not large enough.
v2: clamp the per-shader maximum in st/mesa, then sum them all up
NOTE: This is a candidate for the stable branches.
Michel Dänzer [Fri, 24 May 2013 14:49:42 +0000 (16:49 +0200)]
radeonsi: Enable GLSL 1.30
Michel Dänzer [Mon, 6 May 2013 10:45:14 +0000 (12:45 +0200)]
radeonsi: Handle TGSI TXQ opcode
Michel Dänzer [Thu, 2 May 2013 07:44:45 +0000 (09:44 +0200)]
radeonsi: Add support for TGSI TXF opcode
Michel Dänzer [Fri, 24 May 2013 12:23:26 +0000 (13:23 +0100)]
radeonsi: Use tgsi_util_get_texture_coord_dim()
Michel Dänzer [Thu, 2 May 2013 12:53:17 +0000 (14:53 +0200)]
radeonsi: Handle TGSI_SEMANTIC_CLIPDIST
Michel Dänzer [Wed, 1 May 2013 16:15:36 +0000 (18:15 +0200)]
radeonsi: Make border colour state handling safe for integer textures
Michel Dänzer [Tue, 30 Apr 2013 14:34:10 +0000 (16:34 +0200)]
radeonsi: Fix hardware state for dual source blending
Set up CB_SHADER_MASK register according to pixel shader exports, and enable
some minimal state for colour buffer 1 in case dual source blending is used.
Vadim Girlin [Tue, 28 May 2013 01:24:53 +0000 (05:24 +0400)]
r600g/sb: handle more cases for folding in gvn pass
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Christian König [Thu, 23 May 2013 17:31:08 +0000 (19:31 +0200)]
st/vdpau: destroy handle table only when it's empty
Signed-off-by: Christian König <christian.koenig@amd.com>
Christian König [Thu, 23 May 2013 17:28:57 +0000 (19:28 +0200)]
st/vdpau: remove vlCreateHTAB from surface functions
Signed-off-by: Christian König <christian.koenig@amd.com>
Christian König [Thu, 23 May 2013 17:17:19 +0000 (19:17 +0200)]
st/vdpau: invalidate the handles on destruction
Fixes a problem with xbmc when switching channels.
Signed-off-by: Christian König <christian.koenig@amd.com>
Vadim Girlin [Mon, 27 May 2013 10:23:47 +0000 (14:23 +0400)]
r600g/sb: improve folding for SETcc
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Mon, 27 May 2013 11:29:56 +0000 (15:29 +0400)]
r600g/sb: optimize CNDcc instructions
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Mon, 27 May 2013 00:00:03 +0000 (04:00 +0400)]
r600g/sb: improve optimization of conditional instructions
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Chia-I Wu [Mon, 27 May 2013 04:31:01 +0000 (12:31 +0800)]
ilo: enable multiple constant buffers
This effectively enables uniform buffer object support.
Chia-I Wu [Mon, 27 May 2013 04:09:33 +0000 (12:09 +0800)]
ilo: add support for indirect access of CONST in FS
Unlike other register files, CONST is read with a message and indirect access
is easier to implement.
Chia-I Wu [Mon, 27 May 2013 04:29:51 +0000 (12:29 +0800)]
ilo: add support for TBOs on GEN6
This hunk was missing in the last commit.
Chia-I Wu [Thu, 23 May 2013 06:02:36 +0000 (14:02 +0800)]
ilo: advertise supports for pure integer formats
For pure integer formats, no filtering nor blending is needed.
Chia-I Wu [Thu, 23 May 2013 04:50:14 +0000 (12:50 +0800)]
ilo: add support for texture buffer objects
Take care of sampler views that have buffers as the underlying resources.
Update caps related to TBOs.
Chia-I Wu [Thu, 23 May 2013 05:24:55 +0000 (13:24 +0800)]
tgsi: add buffer texture to tgsi_util_get_texture_coord_dim()
TGSI_TEXTURE_BUFFER is one-dimensional. Assert that exec_tex() is never
called with TGSI_TEXTURE_BUFFER.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Vadim Girlin [Sun, 26 May 2013 21:37:54 +0000 (01:37 +0400)]
r600g/sb: improve handling of KILL instructions
This patch improves handling of unconditional KILL instructions inside
the conditional blocks, uncovering more opportunities for if-conversion.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Sun, 26 May 2013 21:41:11 +0000 (01:41 +0400)]
r600g/sb: fix peephole optimization for PRED_SETE
Fixes incorrect condition that prevented optimization for
PRED_SETE/PRED_SETE_INT.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Sun, 26 May 2013 21:39:54 +0000 (01:39 +0400)]
r600g/sb: fix scheduling of PRED_SET instructions
PRED_SET instructions that update exec mask should be scheduled immediately
prior to the "if-then-else" block, because any instruction that is
inserted after alu clause with PRED_SET and before conditional block is
also conditionally executed by hw (exec mask is already updated at that
moment).
Propbably it's better to make PRED_SET a part of conditional
"if-then-else" block in the IR to handle this more cleanly,
but for now this temporary solution should prevent the problem.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Sat, 25 May 2013 18:56:53 +0000 (22:56 +0400)]
r600g/sb: fix handling of preloaded inputs for compute shaders
For compute shaders we need to let the backend know that
GPRs 0 and 1 are preloaded with some compute-specific input
values, otherwise any use of these regs without previous
definition is considered as undefined value and usually
is simply replaced with 0.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Brian Paul [Fri, 24 May 2013 14:06:19 +0000 (08:06 -0600)]
xlib: add null ctx check in glXDestroyContext()
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64934
NOTE: This is a candidate for the stable branches.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Fri, 24 May 2013 14:06:04 +0000 (08:06 -0600)]
st/glx: add null ctx check in glXDestroyContext()
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64934
NOTE: This is a candidate for the stable branches.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Thu, 23 May 2013 15:33:19 +0000 (09:33 -0600)]
st/mesa: add switch cases for new IR enums to silence warnings
Brian Paul [Tue, 21 May 2013 20:11:42 +0000 (14:11 -0600)]
st/glx/xlib: assorted whitespace, comment fixes
Vadim Girlin [Fri, 24 May 2013 15:07:27 +0000 (19:07 +0400)]
r600g/sb: fix incorrect assert
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Fri, 24 May 2013 14:15:57 +0000 (18:15 +0400)]
r600g/sb: relax some restrictions for FETCH instructions
This allows GVN rewrite pass to propagate non-const (register)
values to FETCH source operands, helping to eliminate unnecessary
copies in some cases.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Fri, 24 May 2013 14:07:55 +0000 (18:07 +0400)]
r600g/sb: relax register allocation for compute shaders
We have to assume that all GPRs in compute shader can be indirectly
addressed because LLVM backend doesn't provide any indirect array info.
That's why for compute shaders GPR array is created that covers all used
GPRs (0..r600_bytecode::ngpr-1), but this seriously restricts register
allocation in sb.
This patch checks for actual use of indirect access in the shader and
if it's not used then GPR array is not created, so that regalloc is not
unnecessarily restricted.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Fri, 24 May 2013 12:45:58 +0000 (16:45 +0400)]
r600g/sb: fix gpr array handling for compute shaders
Fixes segfault with bfgminer and R600_DEBUG=sbcl.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Fri, 24 May 2013 12:24:09 +0000 (16:24 +0400)]
r600g/sb: fix buffer overflow in sb_ostream
Fixes segfault during bytecode dump with bfgminer kernel
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Tom Stellard [Tue, 14 May 2013 15:56:25 +0000 (08:56 -0700)]
r600g/compute: Use common transfer_{map,unmap} functions for global resources
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Tom Stellard [Tue, 14 May 2013 15:56:25 +0000 (08:56 -0700)]
r600g/compute: Use common transfer_{map,unmap} functions for kernel inputs
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Kenneth Graunke [Fri, 24 May 2013 03:19:19 +0000 (20:19 -0700)]
i965: Go back to using the kernel SOL reset feature.
It turns out the MI_LOAD_REGISTER_IMM approach doesn't work on Haswell,
and regressed essentially all the transform feedback Piglit tests.
This morally reverts
eaa6fbe6d54dc99efac4ab8e800edef65ce8220d. However,
the code is still simpler than it was. On BeginTransformFeedback, we
simply flush the batch and set the SOL reset flag so that the next batch
will start with zeroed offsets. There's still no software counting.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64887
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Wed, 15 May 2013 00:05:55 +0000 (20:05 -0400)]
freedreno: scissor fix
Don't assume the state-tracker will set the scissor after the
framebuffer state is changed.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 14 May 2013 17:57:06 +0000 (13:57 -0400)]
freedreno: implement pipe->resource_copy_region()
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Kenneth Graunke [Tue, 21 May 2013 06:46:16 +0000 (23:46 -0700)]
glsl linker: compare interface blocks during interstage linking
Verify that interface blocks match when linking separate shader
stages into a program.
Fixes piglit glsl-1.50 tests:
* linker/interface-blocks-vs-fs-member-count-mismatch.shader_test
* linker/interface-blocks-vs-fs-member-order-mismatch.shader_test
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Jordan Justen [Tue, 21 May 2013 06:42:49 +0000 (23:42 -0700)]
glsl linker: compare interface blocks during intrastage linking
Verify that interface blocks match when combining compilation
units at the same stage. (For example, when merging all vertex
shaders.)
Fixes piglit glsl-1.50 test:
* linker/interface-blocks-multiple-vs-member-count-mismatch.shader_test
v5 (Ken): Rename to link_interface_blocks.cpp and drop the separate .h
file for consistency with other linker code. Remove "ok" variable.
Fold cross_validate_interface_blocks into its caller.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sun, 17 Mar 2013 09:04:56 +0000 (02:04 -0700)]
glsl linker: support arrays of interface block instances
With this change we now support interface block arrays.
For example, cases like this:
out block_name {
float f;
} block_instance[2];
This allows Mesa to pass the piglit glsl-1.50 test:
* execution/interface-blocks-complex-vs-fs.shader_test
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sun, 10 Mar 2013 10:48:53 +0000 (03:48 -0700)]
glsl link_varyings: link interface blocks using the block name
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sun, 10 Mar 2013 10:20:03 +0000 (03:20 -0700)]
glsl linker: remove interface block instance names
Convert interface blocks with instance names into flat
interface blocks without an instance name.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sun, 10 Mar 2013 00:34:55 +0000 (16:34 -0800)]
glsl ast_to_hir: support in/out for interface blocks
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sun, 24 Mar 2013 00:16:28 +0000 (17:16 -0700)]
glsl ast_to_hir: reject row/column_major for in/out interface blocks
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Thu, 21 Mar 2013 18:10:04 +0000 (11:10 -0700)]
glsl ast_to_hir: move uniform block symbols to interface blocks namespace
Uniform/interface blocks are a separate namespace from types.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Thu, 21 Mar 2013 16:57:20 +0000 (09:57 -0700)]
glsl_symbol_table: add interface block namespaces
For interface blocks, there are three separate namespaces for
uniform, input and output blocks.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sat, 9 Mar 2013 22:52:14 +0000 (14:52 -0800)]
glsl parser: allow in & out for interface block members
Previously uniform blocks allowed for the 'uniform' keyword
to be used with members of a uniform blocks. With interface
blocks 'in' can be used on 'in' interface block members and
'out' can be used on 'out' interface block members.
The basic_interface_block rule will verify that the same
qualifier type is used with the block and each member.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>