Eddie Hung [Wed, 20 Feb 2019 23:34:59 +0000 (15:34 -0800)]
Move tests/techmap/abc9 to simple_abc9
Eddie Hung [Wed, 20 Feb 2019 23:31:35 +0000 (15:31 -0800)]
Add tests/simple_abc9
Eddie Hung [Wed, 20 Feb 2019 20:56:15 +0000 (12:56 -0800)]
abc9 to cope with multiple modules
Eddie Hung [Wed, 20 Feb 2019 20:40:17 +0000 (12:40 -0800)]
abc9 to use & syntax for -fast, and name fixes
Eddie Hung [Wed, 20 Feb 2019 20:39:51 +0000 (12:39 -0800)]
read_aiger: new naming fixes
Eddie Hung [Wed, 20 Feb 2019 19:22:56 +0000 (11:22 -0800)]
read_aiger to name wires with internal name, less likely to clash
Eddie Hung [Wed, 20 Feb 2019 19:09:13 +0000 (11:09 -0800)]
write_xaiger to not write latches, CO/PO fixes
Eddie Hung [Wed, 20 Feb 2019 19:08:49 +0000 (11:08 -0800)]
synth to take -abc9 argument
Eddie Hung [Wed, 20 Feb 2019 00:06:03 +0000 (16:06 -0800)]
abc9 to cope with indexed wires when creating $lut from $_NOT_
Eddie Hung [Tue, 19 Feb 2019 23:25:03 +0000 (15:25 -0800)]
Add a quick abc9 test
Eddie Hung [Tue, 19 Feb 2019 23:15:50 +0000 (15:15 -0800)]
Same for ascii AIGERs too
Eddie Hung [Tue, 19 Feb 2019 23:14:08 +0000 (15:14 -0800)]
read_aiger to cope with non-unique POs
Eddie Hung [Tue, 19 Feb 2019 22:20:04 +0000 (14:20 -0800)]
Merge branch 'master' into xaig
Eddie Hung [Tue, 19 Feb 2019 20:32:40 +0000 (12:32 -0800)]
Merge pull request #805 from eddiehung/dff_init
write_verilog to write initial statement for initial flop state
Eddie Hung [Tue, 19 Feb 2019 20:30:20 +0000 (12:30 -0800)]
abc9 to replace $_NOT_ with $lut
Eddie Hung [Tue, 19 Feb 2019 20:27:50 +0000 (12:27 -0800)]
read_aiger to create sane $lut names, and rename when renaming driving wire
Eddie Hung [Tue, 19 Feb 2019 18:24:55 +0000 (10:24 -0800)]
Add comment
Eddie Hung [Tue, 19 Feb 2019 18:19:53 +0000 (10:19 -0800)]
Get rid of boost dep, fix the FIXMEs for Win32?
Eddie Hung [Sun, 17 Feb 2019 20:18:12 +0000 (12:18 -0800)]
Instead of INIT param on cells, use initial statement with hier ref as
per @cliffordwolf
Eddie Hung [Sun, 17 Feb 2019 20:11:52 +0000 (12:11 -0800)]
Revert "Add INIT parameter to all ff/latch cells"
This reverts commit
742b4e01b498ae2e735d40565f43607d69a015d8.
Eddie Hung [Sun, 17 Feb 2019 19:49:06 +0000 (11:49 -0800)]
Merge https://github.com/YosysHQ/yosys into dff_init
Clifford Wolf [Sun, 17 Feb 2019 10:39:14 +0000 (11:39 +0100)]
Merge pull request #811 from ucb-bar/firrtlfixes
Update cells supported for verilog to FIRRTL conversion.
Eddie Hung [Sun, 17 Feb 2019 06:25:22 +0000 (22:25 -0800)]
Get rid of debugging stuff in abc9
Eddie Hung [Sun, 17 Feb 2019 06:22:29 +0000 (22:22 -0800)]
In read_xaiger, do not construct ConstEval for every LUT
Eddie Hung [Sun, 17 Feb 2019 06:22:17 +0000 (22:22 -0800)]
Cleanup
Eddie Hung [Sun, 17 Feb 2019 05:53:03 +0000 (21:53 -0800)]
read_aiger to ignore output = input of same wire; also create new output for different wire
Eddie Hung [Sun, 17 Feb 2019 05:09:48 +0000 (21:09 -0800)]
Cleanup
Eddie Hung [Sun, 17 Feb 2019 05:00:39 +0000 (21:00 -0800)]
write_xaiger to support non-bit cell connections, and cope with COs for -O
Eddie Hung [Sun, 17 Feb 2019 04:09:40 +0000 (20:09 -0800)]
abc9 to write_aiger with -O option, and ignore dummy outputs
Eddie Hung [Sun, 17 Feb 2019 04:08:59 +0000 (20:08 -0800)]
write_aiger -O to write dummy output as __dummy_o__
Eddie Hung [Sat, 16 Feb 2019 21:47:38 +0000 (13:47 -0800)]
abc9 to handle comb loops, cope with constant outputs, disconnect using new wire
Eddie Hung [Sat, 16 Feb 2019 21:45:51 +0000 (13:45 -0800)]
read_aiger to disable log_debug
Eddie Hung [Sat, 16 Feb 2019 21:45:17 +0000 (13:45 -0800)]
expose command to not skip 'internal' wires beginning with '$'
Eddie Hung [Sat, 16 Feb 2019 16:58:25 +0000 (08:58 -0800)]
read_xaiger() to use f.read() not readsome()
Eddie Hung [Sat, 16 Feb 2019 16:53:06 +0000 (08:53 -0800)]
abc9 to cope with non-wideports, count cells properly
Eddie Hung [Sat, 16 Feb 2019 16:48:33 +0000 (08:48 -0800)]
Tidy up write_xaiger
Eddie Hung [Sat, 16 Feb 2019 16:46:25 +0000 (08:46 -0800)]
write_aiger() to perform CI/CO post-processing and fix symbols
Eddie Hung [Sat, 16 Feb 2019 16:44:11 +0000 (08:44 -0800)]
read_aiger() to cope with constant outputs, mixed wideports, do cleaning
Eddie Hung [Fri, 15 Feb 2019 23:23:26 +0000 (15:23 -0800)]
Move lookup inside if
Eddie Hung [Fri, 15 Feb 2019 23:22:18 +0000 (15:22 -0800)]
Fixes needed for DFF circuits
Eddie Hung [Fri, 15 Feb 2019 21:00:13 +0000 (13:00 -0800)]
Refactor
Eddie Hung [Fri, 15 Feb 2019 20:55:52 +0000 (12:55 -0800)]
Cope with width != 1 when re-mapping cells
Jim Lawson [Fri, 15 Feb 2019 20:00:28 +0000 (12:00 -0800)]
Removed unused variables, functions.
Jim Lawson [Fri, 15 Feb 2019 19:56:51 +0000 (11:56 -0800)]
Append (instead of over-writing) EXTRA_FLAGS
Eddie Hung [Fri, 15 Feb 2019 19:52:34 +0000 (11:52 -0800)]
abc9 to stitch results with CI/CO properly
Eddie Hung [Fri, 15 Feb 2019 19:52:05 +0000 (11:52 -0800)]
read_aiger with more asserts, and call clean
Eddie Hung [Fri, 15 Feb 2019 19:51:21 +0000 (11:51 -0800)]
write_xaiger to cope with unknown cells by transforming them to CI/CO
Jim Lawson [Fri, 15 Feb 2019 19:14:17 +0000 (11:14 -0800)]
Update cells supported for verilog to FIRRTL conversion.
Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
Eddie Hung [Thu, 14 Feb 2019 22:52:47 +0000 (14:52 -0800)]
More cleanup
Eddie Hung [Thu, 14 Feb 2019 22:48:38 +0000 (14:48 -0800)]
More cleanup of write_xaiger
Eddie Hung [Thu, 14 Feb 2019 21:27:26 +0000 (13:27 -0800)]
Get rid of formal stuff from xaiger backend
Eddie Hung [Thu, 14 Feb 2019 21:19:27 +0000 (13:19 -0800)]
synth_ice40 to have new -abc9 arg
Eddie Hung [Thu, 14 Feb 2019 01:19:30 +0000 (17:19 -0800)]
Leave FIXME for clean
Eddie Hung [Thu, 14 Feb 2019 01:08:32 +0000 (17:08 -0800)]
Use module->addLut()
Eddie Hung [Thu, 14 Feb 2019 01:04:23 +0000 (17:04 -0800)]
Fix stitching
Eddie Hung [Thu, 14 Feb 2019 01:00:00 +0000 (17:00 -0800)]
Use ConstEval to compute LUT masks
Eddie Hung [Wed, 13 Feb 2019 22:09:36 +0000 (14:09 -0800)]
Merge remote-tracking branch 'origin/read_aiger' into xaig
Eddie Hung [Wed, 13 Feb 2019 22:08:31 +0000 (14:08 -0800)]
Merge https://github.com/YosysHQ/yosys into xaig
Eddie Hung [Wed, 13 Feb 2019 18:44:52 +0000 (10:44 -0800)]
Rip out some more stuff
Clifford Wolf [Wed, 13 Feb 2019 11:36:47 +0000 (12:36 +0100)]
Fix sign handling of real constants
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Wed, 13 Feb 2019 00:25:22 +0000 (16:25 -0800)]
Rip out unused functions in abc9
Eddie Hung [Tue, 12 Feb 2019 20:58:10 +0000 (12:58 -0800)]
Add support for read_aiger -wideports
Eddie Hung [Tue, 12 Feb 2019 20:16:37 +0000 (12:16 -0800)]
Add support for read_aiger -map
Eddie Hung [Tue, 12 Feb 2019 17:36:22 +0000 (09:36 -0800)]
Parse 'm' in xaiger
Eddie Hung [Tue, 12 Feb 2019 17:31:22 +0000 (09:31 -0800)]
WIP for ABC with aiger
Eddie Hung [Tue, 12 Feb 2019 17:24:13 +0000 (09:24 -0800)]
Missing headers for Xcode?
Eddie Hung [Tue, 12 Feb 2019 17:21:46 +0000 (09:21 -0800)]
Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger
Eddie Hung [Tue, 12 Feb 2019 17:21:15 +0000 (09:21 -0800)]
Use module->add{Not,And}Gate() functions
Clifford Wolf [Tue, 12 Feb 2019 13:41:34 +0000 (14:41 +0100)]
Merge pull request #802 from whitequark/write_verilog_async_mem_ports
write_verilog: correctly emit asynchronous transparent ports
Clifford Wolf [Tue, 12 Feb 2019 13:39:39 +0000 (14:39 +0100)]
Merge pull request #806 from daveshah1/fsm_opt_no_reset
fsm_opt: Fix runtime error for FSMs without a reset state
Eddie Hung [Mon, 11 Feb 2019 23:19:17 +0000 (15:19 -0800)]
Add read_xaiger
Eddie Hung [Mon, 11 Feb 2019 23:18:42 +0000 (15:18 -0800)]
Add write_xaiger
Eddie Hung [Mon, 11 Feb 2019 21:28:00 +0000 (13:28 -0800)]
Do not break for constraints
Eddie Hung [Mon, 11 Feb 2019 21:24:21 +0000 (13:24 -0800)]
No increment line_count for binary ANDs
Eddie Hung [Mon, 11 Feb 2019 19:51:44 +0000 (11:51 -0800)]
Do not ignore newline after AND in binary AIG
Eddie Hung [Fri, 8 Feb 2019 22:53:12 +0000 (14:53 -0800)]
Copy backends/aiger/aiger.cc to xaiger.cc
Eddie Hung [Fri, 8 Feb 2019 22:42:08 +0000 (14:42 -0800)]
Merge remote-tracking branch 'origin/dff_init' into read_aiger
Eddie Hung [Fri, 8 Feb 2019 21:58:47 +0000 (13:58 -0800)]
Compile abc9
Eddie Hung [Fri, 8 Feb 2019 21:58:20 +0000 (13:58 -0800)]
Refactor kernel/cost.h definition into cost.cc
Eddie Hung [Fri, 8 Feb 2019 21:23:54 +0000 (13:23 -0800)]
Copy abc.cc to abc9.cc
Eddie Hung [Fri, 8 Feb 2019 21:17:53 +0000 (13:17 -0800)]
addDff -> addDffGate as per @daveshah1
Eddie Hung [Fri, 8 Feb 2019 21:17:02 +0000 (13:17 -0800)]
Fix tabulation
Eddie Hung [Fri, 8 Feb 2019 20:49:55 +0000 (12:49 -0800)]
-module_name arg to go before -clk_name
Eddie Hung [Fri, 8 Feb 2019 20:41:59 +0000 (12:41 -0800)]
Support and differentiate between ASCII and binary AIG testing
Eddie Hung [Fri, 8 Feb 2019 20:41:39 +0000 (12:41 -0800)]
Add missing "[options]" to read_blif help
Eddie Hung [Fri, 8 Feb 2019 20:40:43 +0000 (12:40 -0800)]
Allow module name to be determined by argument too
Eddie Hung [Fri, 8 Feb 2019 20:04:26 +0000 (12:04 -0800)]
Refactor into AigerReader class
Eddie Hung [Fri, 8 Feb 2019 19:45:16 +0000 (11:45 -0800)]
Parse binary AIG files
Eddie Hung [Fri, 8 Feb 2019 19:41:25 +0000 (11:41 -0800)]
Add binary AIGs converted from AAG
Eddie Hung [Fri, 8 Feb 2019 18:54:31 +0000 (10:54 -0800)]
Refactor to parse_aiger_header()
Eddie Hung [Fri, 8 Feb 2019 16:37:44 +0000 (08:37 -0800)]
Add comment
Eddie Hung [Fri, 8 Feb 2019 16:37:18 +0000 (08:37 -0800)]
Handle reset logic in latches
Eddie Hung [Fri, 8 Feb 2019 16:09:30 +0000 (08:09 -0800)]
Change literal vars from int to unsigned
Eddie Hung [Fri, 8 Feb 2019 16:08:49 +0000 (08:08 -0800)]
Create clk outside of latch loop
Eddie Hung [Fri, 8 Feb 2019 16:05:27 +0000 (08:05 -0800)]
Handle latch symbols too
Eddie Hung [Fri, 8 Feb 2019 16:04:48 +0000 (08:04 -0800)]
Remove return after log_error
Eddie Hung [Fri, 8 Feb 2019 16:03:40 +0000 (08:03 -0800)]
Add support for symbol tables
Eddie Hung [Fri, 8 Feb 2019 15:31:04 +0000 (07:31 -0800)]
Stub for binary AIGER
David Shah [Thu, 7 Feb 2019 10:35:36 +0000 (10:35 +0000)]
fsm_opt: Fix runtime error for FSMs without a reset state
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Wed, 6 Feb 2019 23:51:12 +0000 (15:51 -0800)]
Cope WIDTH of ff/latch cells is default of zero