enjoy-digital [Mon, 27 Apr 2020 11:59:28 +0000 (13:59 +0200)]
Merge pull request #476 from enjoy-digital/serv
Add SERV support (The SErial RISC-V CPU)
Florent Kermarrec [Mon, 27 Apr 2020 11:46:12 +0000 (13:46 +0200)]
software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning.
Florent Kermarrec [Mon, 27 Apr 2020 11:26:45 +0000 (13:26 +0200)]
serv: connect reset.
Florent Kermarrec [Mon, 27 Apr 2020 11:17:53 +0000 (13:17 +0200)]
build/icestorm: add verilog_read -defer option to yosys script (changes similar the ones applied to trellis).
enjoy-digital [Mon, 27 Apr 2020 11:13:37 +0000 (13:13 +0200)]
Merge pull request #475 from gregdavill/read_verilog_defer
build/trellis: add verilog_read -defer option to yosys script
Greg Davill [Mon, 27 Apr 2020 10:40:25 +0000 (20:10 +0930)]
build/trellis: add verilog_read -defer option to yosys script
Florent Kermarrec [Mon, 27 Apr 2020 08:27:44 +0000 (10:27 +0200)]
serv: update copyrights (Greg Davill found the typos/issues).
Florent Kermarrec [Sun, 26 Apr 2020 19:05:47 +0000 (21:05 +0200)]
serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :).
Florent Kermarrec [Sun, 26 Apr 2020 14:26:15 +0000 (16:26 +0200)]
serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill).
Florent Kermarrec [Sat, 25 Apr 2020 10:51:33 +0000 (12:51 +0200)]
bios/sdram: reduce number of scan loops during cdly scan to speed it up.
Florent Kermarrec [Sat, 25 Apr 2020 10:12:27 +0000 (12:12 +0200)]
targets/kcu105: use cmd_latency=1.
Florent Kermarrec [Sat, 25 Apr 2020 10:11:10 +0000 (12:11 +0200)]
bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal.
We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
Florent Kermarrec [Sat, 25 Apr 2020 09:03:04 +0000 (11:03 +0200)]
targets/kc705: manual DDRPHY_CMD_DELAY no longer needed.
Florent Kermarrec [Sat, 25 Apr 2020 09:00:21 +0000 (11:00 +0200)]
bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle.
Working on KC705 that previously required manual adjustment.
enjoy-digital [Sat, 25 Apr 2020 07:59:08 +0000 (09:59 +0200)]
Merge pull request #472 from antmicro/jboc/sdram-calibration
bios/sdram: add automatic cdly calibration during write leveling
enjoy-digital [Sat, 25 Apr 2020 06:27:00 +0000 (08:27 +0200)]
Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings
litex_sim: add option to create SDRAM module from SPD data
Jędrzej Boczar [Thu, 23 Apr 2020 11:52:28 +0000 (13:52 +0200)]
bios/sdram: add automatic cdly calibration during write leveling
Florent Kermarrec [Thu, 23 Apr 2020 06:04:04 +0000 (08:04 +0200)]
initial SERV integration.
Florent Kermarrec [Wed, 22 Apr 2020 11:15:07 +0000 (13:15 +0200)]
soc/cores/spi: add optional aligned mode.
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
Florent Kermarrec [Wed, 22 Apr 2020 10:20:23 +0000 (12:20 +0200)]
cores/spi: simplify.
Florent Kermarrec [Wed, 22 Apr 2020 09:50:55 +0000 (11:50 +0200)]
build/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateImpl (thanks @tnt).
Florent Kermarrec [Wed, 22 Apr 2020 08:41:50 +0000 (10:41 +0200)]
xilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and Ultrascale.
Florent Kermarrec [Wed, 22 Apr 2020 08:33:22 +0000 (10:33 +0200)]
build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input.
Florent Kermarrec [Wed, 22 Apr 2020 08:13:28 +0000 (10:13 +0200)]
lattice/common: add LatticeECP5DDRInput.
Florent Kermarrec [Wed, 22 Apr 2020 06:45:32 +0000 (08:45 +0200)]
lattice/common: cleanup instances, simplify tritates.
Florent Kermarrec [Wed, 22 Apr 2020 06:41:17 +0000 (08:41 +0200)]
lattice/common: add LatticeiCE40DDRInput, LatticeiCE40SDROutput and LatticeiCE40SDRInput.
Florent Kermarrec [Sat, 18 Apr 2020 09:38:24 +0000 (11:38 +0200)]
platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.
Florent Kermarrec [Fri, 17 Apr 2020 19:30:33 +0000 (21:30 +0200)]
tools/remote/etherbone: update import.
Jędrzej Boczar [Fri, 17 Apr 2020 12:52:53 +0000 (14:52 +0200)]
litex_sim: add option to create SDRAM module from SPD data
Florent Kermarrec [Thu, 16 Apr 2020 09:26:59 +0000 (11:26 +0200)]
targets: manual define of the SDRAM PHY no longer needed.
Florent Kermarrec [Thu, 16 Apr 2020 08:23:31 +0000 (10:23 +0200)]
bios/sdram: update/simplify with new exported LiteDRAM parameters.
Florent Kermarrec [Thu, 16 Apr 2020 08:22:43 +0000 (10:22 +0200)]
litex_sim: add phytype to PhySettings.
Florent Kermarrec [Thu, 16 Apr 2020 06:44:36 +0000 (08:44 +0200)]
build/generic_programmer: move requests import to do it only when needed.
Florent Kermarrec [Wed, 15 Apr 2020 17:30:23 +0000 (19:30 +0200)]
bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.
Bitslip software control is now used on ECP5 to move dqs_read.
Florent Kermarrec [Wed, 15 Apr 2020 07:27:26 +0000 (09:27 +0200)]
setup.py/install_requires: add requests.
Florent Kermarrec [Wed, 15 Apr 2020 06:59:03 +0000 (08:59 +0200)]
build/generic_programmer: add automatic search/download of flash_proxy in repositories if not available locally.
enjoy-digital [Wed, 15 Apr 2020 05:56:48 +0000 (07:56 +0200)]
Merge pull request #467 from antmicro/region_type_fix
soc_core: Fix region type generation
Mateusz Holenko [Tue, 14 Apr 2020 19:43:58 +0000 (21:43 +0200)]
soc_core: Fix region type generation
Include information about being a linker region.
Florent Kermarrec [Tue, 14 Apr 2020 15:34:57 +0000 (17:34 +0200)]
stream/AsyncFIFO: add default depth (useful when used for CDC).
Florent Kermarrec [Tue, 14 Apr 2020 10:38:02 +0000 (12:38 +0200)]
build/sim/core/Makefile: add -p to mkdir modules.
enjoy-digital [Tue, 14 Apr 2020 10:16:21 +0000 (12:16 +0200)]
Merge pull request #464 from mithro/litex-sim-fixes
Improve the litex_sim Makefiles
Florent Kermarrec [Sun, 12 Apr 2020 17:46:56 +0000 (19:46 +0200)]
litex_setup: raise exception on update if repository has been been initialized.
Tim 'mithro' Ansell [Sun, 12 Apr 2020 17:29:13 +0000 (10:29 -0700)]
Remove trailing whitespace.
Florent Kermarrec [Sun, 12 Apr 2020 14:34:33 +0000 (16:34 +0200)]
cores: add External Memory Interface (EMIF) Wishbone bridge.
Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
enjoy-digital [Sun, 12 Apr 2020 13:49:49 +0000 (15:49 +0200)]
Merge pull request #462 from ironsteel/trellis-12k
Add support for ecp5 12k device in trellis.py
Rangel Ivanov [Sun, 12 Apr 2020 08:51:08 +0000 (11:51 +0300)]
boards/targets/ulx3s.py: Update --device option help message
Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
Rangel Ivanov [Sun, 12 Apr 2020 08:46:44 +0000 (11:46 +0300)]
build/lattice/trellis.py: Add 12k device
nextpnr adds the --12k option which is the same like
the --25k but with the correct idcode for the 12k devices
Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
Tim 'mithro' Ansell [Sun, 12 Apr 2020 01:26:15 +0000 (18:26 -0700)]
litex_sim: Rework Makefiles to put output files in gateware directory.
Tim 'mithro' Ansell [Sun, 12 Apr 2020 01:23:40 +0000 (18:23 -0700)]
litex_sim: Better error messages on failure to load module.
Florent Kermarrec [Fri, 10 Apr 2020 17:11:21 +0000 (19:11 +0200)]
README: LiteDRAM moved to travis-ci.com as others repositories.
Florent Kermarrec [Fri, 10 Apr 2020 13:50:35 +0000 (15:50 +0200)]
altera/common: add DDROutput, DDRInput, SDROutput, SDRInput.
Florent Kermarrec [Fri, 10 Apr 2020 12:41:01 +0000 (14:41 +0200)]
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
Florent Kermarrec [Fri, 10 Apr 2020 12:38:22 +0000 (14:38 +0200)]
build/xilinx/common: add Spartan6 specialized DDRInput, SDROutput, SDRInput and SDRTristate.
Florent Kermarrec [Fri, 10 Apr 2020 12:37:29 +0000 (14:37 +0200)]
build/io: add SDR Tristate (with infered version) and remove multi-bits support on SDRIO.
Florent Kermarrec [Fri, 10 Apr 2020 12:36:13 +0000 (14:36 +0200)]
build/lattice/common: remove multi-bits support on SDRInput/Output.
Florent Kermarrec [Fri, 10 Apr 2020 08:25:21 +0000 (10:25 +0200)]
litex/build/io: also import CRG (since using DifferentialInput).
Florent Kermarrec [Fri, 10 Apr 2020 07:18:39 +0000 (09:18 +0200)]
litex.build: update from migen.genlib.io litex.build.io.
Florent Kermarrec [Fri, 10 Apr 2020 06:47:07 +0000 (08:47 +0200)]
litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen.
This will make things easier and more consistent, all special IO primitives are now in LiteX.
Florent Kermarrec [Thu, 9 Apr 2020 21:08:59 +0000 (23:08 +0200)]
platforms/versa_ecp5: remove Lattice Programmer (no longer used since we can now use OpenOCD).
Florent Kermarrec [Thu, 9 Apr 2020 21:04:29 +0000 (23:04 +0200)]
boards/platforms: cosmetic cleanups.
Florent Kermarrec [Thu, 9 Apr 2020 16:55:01 +0000 (18:55 +0200)]
boards/plarforms/ulx3s: cleanup, fix user_leds, add spisdcard, add PULLMODE/DRIVE on SDRAM pins.
Florent Kermarrec [Thu, 9 Apr 2020 14:24:05 +0000 (16:24 +0200)]
build/lattice: add ECP5 implementation for SDRInput/SDROutput.
Florent Kermarrec [Thu, 9 Apr 2020 14:23:27 +0000 (16:23 +0200)]
litex/gen: add io with SDRInput/SDROutput (if not overrided, register is supposed to be infered).
Florent Kermarrec [Thu, 9 Apr 2020 09:14:19 +0000 (11:14 +0200)]
tools/litex_sim: remove LiteSPI support for now since breaking Travis-CI of others sub-projects.
LiteSPI is not mature enough to be integrated in LiteX sim directly. (will case trouble is things are refactored).
This could be re-introduced later when more mature. For now simulation with LiteX Sim
could be tested directly in LiteSPI with a custom simulation.
Florent Kermarrec [Thu, 9 Apr 2020 08:52:15 +0000 (10:52 +0200)]
tools/litex_term: increase workaround delay for usb_fifo. (validated on Minispartan6 and MimasA7).
Still needs to be fixed properly.
enjoy-digital [Thu, 9 Apr 2020 07:01:59 +0000 (09:01 +0200)]
Merge pull request #459 from mithro/travis-fix
Two small Travis-CI related patches
Tim 'mithro' Ansell [Thu, 9 Apr 2020 06:14:26 +0000 (23:14 -0700)]
travis: Run Windows build but allow it to fail.
Tim 'mithro' Ansell [Thu, 9 Apr 2020 06:12:41 +0000 (23:12 -0700)]
travis: Use litex_setup.py from the checked out code.
Tim Ansell [Thu, 9 Apr 2020 04:39:29 +0000 (21:39 -0700)]
Merge pull request #458 from david-sawatzke/add_triple
Add riscv64-none-elf triple
David Sawatzke [Thu, 9 Apr 2020 03:36:10 +0000 (05:36 +0200)]
Add riscv64-none-elf triple
Florent Kermarrec [Wed, 8 Apr 2020 06:54:12 +0000 (08:54 +0200)]
soc/cores/clock: add Max10PLL.
Florent Kermarrec [Wed, 8 Apr 2020 06:33:57 +0000 (08:33 +0200)]
soc/cores/clock: add Cyclone10LPPLL.
Florent Kermarrec [Wed, 8 Apr 2020 06:25:46 +0000 (08:25 +0200)]
soc/cores/clock/CycloneVPLL: fix typos.
Florent Kermarrec [Wed, 8 Apr 2020 06:16:37 +0000 (08:16 +0200)]
soc/cores/clock: rename Altera to Intel.
Florent Kermarrec [Tue, 7 Apr 2020 15:24:12 +0000 (17:24 +0200)]
soc/cores/clock: add CycloneVPLL.
Florent Kermarrec [Tue, 7 Apr 2020 15:00:40 +0000 (17:00 +0200)]
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
Florent Kermarrec [Tue, 7 Apr 2020 14:59:53 +0000 (16:59 +0200)]
soc/cores/clock: add initial AlteraClocking/CycloneIV support.
Florent Kermarrec [Tue, 7 Apr 2020 10:43:29 +0000 (12:43 +0200)]
.travis.yml: disable windows test (failing for now).
Florent Kermarrec [Tue, 7 Apr 2020 10:39:52 +0000 (12:39 +0200)]
README.md: update RISCV toolchain installation.
Florent Kermarrec [Tue, 7 Apr 2020 10:33:56 +0000 (12:33 +0200)]
.travis.yml: remove Python3.5 test.
enjoy-digital [Tue, 7 Apr 2020 10:29:04 +0000 (12:29 +0200)]
Merge pull request #451 from mithro/multi-os
Add multiple Python versions, Windows and Mac to Travis CI testing
Florent Kermarrec [Tue, 7 Apr 2020 09:48:16 +0000 (11:48 +0200)]
setup.py: simplify, switch to Python3.6+ (using python_requires), remove version.
- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.
Florent Kermarrec [Tue, 7 Apr 2020 09:05:14 +0000 (11:05 +0200)]
litex_setup: reorganize a bit, add separators/comments.
Florent Kermarrec [Tue, 7 Apr 2020 08:55:58 +0000 (10:55 +0200)]
.travis.yml: revert full url for litex_setup.py.
We want to have an almost identical .travis.yml between LiteX and the Cores.
Using $TRAVIS_BUILD_DIR works for LiteX but will not work for the cores.
enjoy-digital [Tue, 7 Apr 2020 08:51:27 +0000 (10:51 +0200)]
Merge pull request #452 from mithro/riscv-download
Add GCC downloading via litex_setup.py
Tim 'mithro' Ansell [Tue, 7 Apr 2020 00:52:07 +0000 (17:52 -0700)]
Enable testing on multiple Python versions.
Makes sure LiteX tests pass on all supported Python versions.
Tim 'mithro' Ansell [Mon, 6 Apr 2020 18:47:12 +0000 (11:47 -0700)]
Enable CI for Windows and Mac.
Tim 'mithro' Ansell [Tue, 7 Apr 2020 00:57:32 +0000 (17:57 -0700)]
Remove symlinking step.
Tim 'mithro' Ansell [Tue, 7 Apr 2020 00:45:55 +0000 (17:45 -0700)]
Use shutil.unpack_archive.
Tim 'mithro' Ansell [Tue, 7 Apr 2020 00:36:09 +0000 (17:36 -0700)]
Ignore SSL errors on CI.
Tim 'mithro' Ansell [Tue, 7 Apr 2020 00:27:24 +0000 (17:27 -0700)]
Improve the path messages a little.
Tim 'mithro' Ansell [Mon, 6 Apr 2020 23:54:25 +0000 (16:54 -0700)]
Make travis use litex_setup.py for GCC download.
Tim 'mithro' Ansell [Mon, 6 Apr 2020 23:39:49 +0000 (16:39 -0700)]
Adding SiFive RISC-V toolchain downloading to litex_setup.py
Tim 'mithro' Ansell [Mon, 6 Apr 2020 23:49:52 +0000 (16:49 -0700)]
Fix alignments.
enjoy-digital [Mon, 6 Apr 2020 21:04:47 +0000 (23:04 +0200)]
Merge pull request #450 from mithro/litex-setup-fix
litex_setup: Use subprocess so failures are noticed.
Tim 'mithro' Ansell [Mon, 6 Apr 2020 18:38:23 +0000 (11:38 -0700)]
Run `litex_setup.py` outside the git clone directory.
Otherwise it tries to overwrite the litex directory by cloning LiteX
into it.
Tim 'mithro' Ansell [Mon, 6 Apr 2020 18:25:11 +0000 (11:25 -0700)]
litex_setup: Use subprocess so failures are noticed.
os.system doesn't report if any of the commands fail. This means that if
something goes wrong it happily reports success making it hard to debug
issues.
Florent Kermarrec [Mon, 6 Apr 2020 11:16:13 +0000 (13:16 +0200)]
soc/cores: use reset_less on datapath/configuration CSRStorages.
Florent Kermarrec [Mon, 6 Apr 2020 11:14:21 +0000 (13:14 +0200)]
interconnect/csr: add reset_less parameter.
In cases CSRStorage can be considered as a datapath/configuration register and does not need to be reseted.
Florent Kermarrec [Mon, 6 Apr 2020 11:11:50 +0000 (13:11 +0200)]
interconnect/csr, wishbone: use reset_less on datapath signals.