Merge remote-tracking branch 'origin/xc7srl' into xc7mux

Update help message

Move 'shregmap -tech xilinx' into map_cells

Merge remote-tracking branch 'origin/master' into xc7srl

Merge pull request #950 from whitequark/attrmap_remove_wildcard

attrmap: extend -remove to allow removing attributes with any value

attrmap: extend -remove to allow removing attributes with any value.

Currently, `-remove foo` would only remove an attribute `foo = ""`,
which doesn't work on an attribute like `src` that may have any
value. Extend `-remove` to handle both cases. `-remove foo=""` has
the old behavior, and `-remove foo` will remove the attribute with
whatever value it may have, which is still compatible with the old
behavior.

Set ENABLE_LIBYOSYS=0 by default

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Set ENABLE_PYOSYS=0 by default

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #905 from christian-krieg/feature/python_bindings

Feature/python bindings

Merge pull request #941 from Wren6991/sim_lib_io_clke

ice40 cells_sim.v: update clock enable behaviour based on hardware experiments

Merge branch 'dh73-master'

Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master

Re-added clean after techmap in synth_xilinx

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #916 from YosysHQ/map_cells_before_map_luts

synth_xilinx to map_cells before map_luts

Merge pull request #911 from mmicko/gowin-nobram

Make nobram false by default for gowin

Merge pull request #909 from zachjs/master

support repeat loops with constant repeat counts outside of constant functions

Merge pull request #944 from YosysHQ/clifford/pmux2shiftx

Add pmux2shiftx command

Merge pull request #945 from YosysHQ/clifford/libwb

New behavior for read_verilog handling of whiteboxes

Disable blackbox detection in techmap files

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Tidy up, fix for -nosrl

Merge branch 'map_cells_before_map_luts' into xc7srl

Merge branch 'master' into map_cells_before_map_luts

Add comments

Use new pmux2shiftx from #944, remove my old attempt

ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments

Fix tests

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "noblackbox" attribute

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge remote-tracking branch 'origin/clifford/pmux2shiftx' into xc7srl

Merge remote-tracking branch 'origin/master' into xc7srl

New behavior for front-end handling of whiteboxes

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #943 from YosysHQ/clifford/whitebox

[WIP] Add "whitebox" attribute, add "read_verilog -wb"

Merge remote-tracking branch 'origin/pmux2shiftx' into xc7srl

Merge remote-tracking branch 'origin' into xc7srl

Auto-initialize OnehotDatabase on-demand in pmux2shiftx.cc

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "onehot" pass, improve "pmux2shiftx" onehot handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "techmap -wb", use in formal flows

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Check blackbox attribute in techmap/simplemap

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "wbflip" command

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #942 from YosysHQ/clifford/fix931

Improve proc full_case detection and handling

Improve "pmux2shiftx"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix some typos

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improvements in "pmux2shiftx"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improvements in pmux2shiftx

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add test for pmux2shiftx

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve pmux2shift ctrl permutation finder

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Complete rewrite of pmux2shiftx

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Import initial pmux2shiftx from eddieh

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve "show" handling of 0/1/X/Z padding

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Change "ne" to "neq" in btor2 output

we need to do this because they changed the parser:
https://github.com/Boolector/btor2tools/commit/e97fc9cedabadeec4f621de22096e514f862c690

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add tests/aiger/.gitignore

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Spelling fixes

Revert "write_json to not write contents (cells/wires) of whiteboxes"

This reverts commit 4ef03e19a8eafc324d3442f0642abf858071fdd4.

Update to ABC 3709744

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #917 from YosysHQ/eddie/fix_retime

Retime by default when abc -dff

write_json to not write contents (cells/wires) of whiteboxes

Ignore 'whitebox' attr in flatten with "-wb" option

Fix abc's remap_name to not ignore [^0-9] when extracting sid

ABC to call retime all the time

Add "whitebox" attribute, add "read_verilog -wb"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Revert "synth_* with -retime option now calls abc with -D 1 as well"

This reverts commit 9a6da9a79a22e984ee3eec02caa230b66f10e11a.

Merge branch 'master' into eddie/fix_retime

Improve proc full_case detection and handling, fixes #931

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update to ABC d1b6413

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add MUXCY and XORCY to cells_box.v

Fix wire numbering

Do not put constants into output_bits

Remove write_verilog call

Fix spacing

Merge branch 'xaig' into xc7mux

Re-enable partsel.v test

abc9 to call "setundef -zero" behaving as for abc

NULL check before use

WIP for box support

ABC to read_box before reading netlist

Make cells.box whiteboxes not blackboxes

read_verilog cells_box.v before techmap

Merge pull request #939 from YosysHQ/revert895

Revert #895 (mux-to-shiftx optimisation)

synth_xilinx: before abc read +/xilinx/cells_box.v

Add +/xilinx/cells_box.v containing models for ABC boxes

For 'stat' do not count modules with abc_box_id

Do not call abc on modules with abc_box_id attr

Revert "Add abc_box_id attribute to MUXF7/F8 cells"

This reverts commit 8fbbd9b129697152c93c35831c1d50982702a3ec.

Revert #895

Use abc_box_id

Check abc_box_id attr

Add abc_box_id attribute to MUXF7/F8 cells

Merge branch 'xaig' into xc7mux

Merge remote-tracking branch 'origin/master' into xaig

Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch

Revert "Recognise default entry in case even if all cases covered (fix for #931)"

Revert "Recognise default entry in case even if all cases covered (fix for #931)"

Merge pull request #936 from YosysHQ/README-fix-quotes

README: fix some incorrect quoting

README: fix some incorrect quoting.

GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow

Forgot backslashes

Handle __dummy_o__ and __const[01]__ in read_aiger not abc

abc to ignore __dummy_o__ and __const[01]__ when re-integrating

Output __const0__ and __const1__ CIs

Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig

Fix inout handling for -map option

Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig