whitequark [Sun, 23 Dec 2018 07:17:33 +0000 (07:17 +0000)]
back.rtlil: only translate switch tests once.
This seems to affect synthesis with Yosys but only marginally.
It is mostly a speed and readability improvement.
whitequark [Sun, 23 Dec 2018 07:13:17 +0000 (07:13 +0000)]
cli: generate: guess file type from extension.
whitequark [Sun, 23 Dec 2018 06:47:38 +0000 (06:47 +0000)]
back.rtlil: fix swapped operands in mux codegen.
whitequark [Sat, 22 Dec 2018 23:56:02 +0000 (23:56 +0000)]
cli: new module, for basic design generaton/simulation.
whitequark [Sat, 22 Dec 2018 22:19:14 +0000 (22:19 +0000)]
hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
whitequark [Sat, 22 Dec 2018 22:00:58 +0000 (22:00 +0000)]
compat.genlib.fsm: fix naming for non-Signal LHS.
whitequark [Sat, 22 Dec 2018 21:43:46 +0000 (21:43 +0000)]
hdl.ir: flatten hierarchy based on memory accesses, too.
whitequark [Sat, 22 Dec 2018 19:04:35 +0000 (19:04 +0000)]
hdl.ir: factor out _merge_subfragment. NFC.
whitequark [Sat, 22 Dec 2018 10:03:16 +0000 (10:03 +0000)]
back.rtlil: split processes as finely as possible.
This makes simulation work correctly (by introducing delta cycles,
and therefore, making the overall Verilog simulation deterministic)
at the price of pessimizing mux trees generated by Yosys and Synplify
frontends, sometimes severely.
whitequark [Sat, 22 Dec 2018 07:24:15 +0000 (07:24 +0000)]
back.rtlil: remove useless condition. NFC.
whitequark [Sat, 22 Dec 2018 06:50:32 +0000 (06:50 +0000)]
hdl.xfrm: implement LHSGroupAnalyzer.
whitequark [Sat, 22 Dec 2018 06:03:38 +0000 (06:03 +0000)]
hdl.xfrm: Abstract*Transformer→*Visitor
whitequark [Sat, 22 Dec 2018 05:27:42 +0000 (05:27 +0000)]
back.rtlil: always initialize the entire memory.
This avoids reading 'x from the memory in simulation. In general,
FPGA memories can only be initialized in block granularity, and
zero-initializing is cheap, so this is not a significant issue with
resource consumption.
whitequark [Sat, 22 Dec 2018 02:05:49 +0000 (02:05 +0000)]
compat: use nicer names for next_value/next_value_ce signals.
whitequark [Sat, 22 Dec 2018 01:09:03 +0000 (01:09 +0000)]
hdl.mem: allow changing init value after creating memory.
whitequark [Sat, 22 Dec 2018 00:53:40 +0000 (00:53 +0000)]
back.verilog: do not rename internal signals.
_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
whitequark [Sat, 22 Dec 2018 00:53:05 +0000 (00:53 +0000)]
compat: fix confusing naming for memory port address signal.
whitequark [Sat, 22 Dec 2018 00:31:31 +0000 (00:31 +0000)]
hdl.ir: fix port propagation between siblings, in the other direction.
whitequark [Sat, 22 Dec 2018 00:02:31 +0000 (00:02 +0000)]
compat: do not finalize native submodules twice.
whitequark [Fri, 21 Dec 2018 23:55:02 +0000 (23:55 +0000)]
hdl.mem: use more informative signal naming for ports.
whitequark [Fri, 21 Dec 2018 23:53:18 +0000 (23:53 +0000)]
hdl.ir: fix port propagation between siblings.
whitequark [Fri, 21 Dec 2018 13:53:06 +0000 (13:53 +0000)]
compat: provide verilog.convert shim.
whitequark [Fri, 21 Dec 2018 13:52:18 +0000 (13:52 +0000)]
hdl.ir: do not flatten instances or collect ports from their statements.
This results in absurd behavior for memories.
whitequark [Fri, 21 Dec 2018 13:15:52 +0000 (13:15 +0000)]
compat: provide Memory shim.
whitequark [Fri, 21 Dec 2018 13:01:08 +0000 (13:01 +0000)]
hdl.mem: ensure transparent read port model has correct latency.
whitequark [Fri, 21 Dec 2018 12:32:08 +0000 (12:32 +0000)]
back.pysim: handle out of bounds ArrayProxy indexes.
whitequark [Fri, 21 Dec 2018 12:29:33 +0000 (12:29 +0000)]
back.pysim: give numeric names to unnamed subfragments in VCD.
whitequark [Fri, 21 Dec 2018 12:26:49 +0000 (12:26 +0000)]
hdl.mem: use different naming for array signals.
It looks like [] is confusing gtkwave somehow.
whitequark [Fri, 21 Dec 2018 11:00:42 +0000 (11:00 +0000)]
hdl.mem: add simulation model for memory.
whitequark [Fri, 21 Dec 2018 10:25:28 +0000 (10:25 +0000)]
back.pysim: fix an issue with too few funclet slots.
whitequark [Fri, 21 Dec 2018 06:07:16 +0000 (06:07 +0000)]
hdl.mem: add tests for all error conditions.
whitequark [Fri, 21 Dec 2018 04:22:16 +0000 (04:22 +0000)]
hdl.mem: tie rdport.en high for asynchronous or transparent ports.
whitequark [Fri, 21 Dec 2018 04:21:11 +0000 (04:21 +0000)]
back.rtlil: more consistent prefixing for subfragment port wires.
whitequark [Fri, 21 Dec 2018 04:03:03 +0000 (04:03 +0000)]
hdl.ir: correctly handle named output and inout ports.
whitequark [Fri, 21 Dec 2018 01:55:59 +0000 (01:55 +0000)]
back.rtlil: implement memories.
whitequark [Fri, 21 Dec 2018 01:53:32 +0000 (01:53 +0000)]
hdl.mem: implement memories.
whitequark [Fri, 21 Dec 2018 01:51:18 +0000 (01:51 +0000)]
back.rtlil: explicitly pad constants with zeroes.
I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.
whitequark [Fri, 21 Dec 2018 01:48:02 +0000 (01:48 +0000)]
back.rtlil: fix translation of Cat.
whitequark [Thu, 20 Dec 2018 23:38:01 +0000 (23:38 +0000)]
ir: allow non-Signals in Instance ports.
whitequark [Wed, 19 Dec 2018 17:17:25 +0000 (17:17 +0000)]
setup: update pyvcd dependency, for var_type="string".
whitequark [Tue, 18 Dec 2018 20:04:22 +0000 (20:04 +0000)]
compat: import genlib.record from Migen.
whitequark [Tue, 18 Dec 2018 20:02:32 +0000 (20:02 +0000)]
compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.
whitequark [Tue, 18 Dec 2018 19:15:44 +0000 (19:15 +0000)]
hdl.ast: Cat.{operands→parts}
whitequark [Tue, 18 Dec 2018 18:02:21 +0000 (18:02 +0000)]
back.pysim: implement *.
whitequark [Tue, 18 Dec 2018 17:53:50 +0000 (17:53 +0000)]
test.sim: add tests for sync functionality and errors.
whitequark [Tue, 18 Dec 2018 15:28:27 +0000 (15:28 +0000)]
back.pysim: eliminate most dictionary lookups.
This makes the Glasgow testsuite about 30% faster.
whitequark [Tue, 18 Dec 2018 15:06:02 +0000 (15:06 +0000)]
hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim.
whitequark [Tue, 18 Dec 2018 05:19:12 +0000 (05:19 +0000)]
back.pysim: use arrays instead of dicts for signal values.
This makes the Glasgow testsuite about 40% faster.
whitequark [Tue, 18 Dec 2018 04:46:36 +0000 (04:46 +0000)]
back.pysim: naming. NFC.
whitequark [Tue, 18 Dec 2018 04:43:04 +0000 (04:43 +0000)]
back.pysim: fix an off-by-1 in add_sync_process().
whitequark [Tue, 18 Dec 2018 04:37:39 +0000 (04:37 +0000)]
back.pysim: trigger processes waiting on Tick() exactly at clock edge.
whitequark [Tue, 18 Dec 2018 03:05:16 +0000 (03:05 +0000)]
back.pysim: continue running simulator processes until they suspend.
whitequark [Mon, 17 Dec 2018 23:46:46 +0000 (23:46 +0000)]
Travis: cache Yosys installation explicitly.
whitequark [Mon, 17 Dec 2018 22:55:30 +0000 (22:55 +0000)]
fhdl.ir: add black-box fragments, fragment parameters, and Instance.
whitequark [Mon, 17 Dec 2018 15:51:55 +0000 (15:51 +0000)]
Travis: build and cache Yosys.
whitequark [Mon, 17 Dec 2018 17:21:12 +0000 (17:21 +0000)]
hdl, back: add and use SignalSet/SignalDict.
whitequark [Mon, 17 Dec 2018 17:13:08 +0000 (17:13 +0000)]
hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC.
whitequark [Mon, 17 Dec 2018 15:50:43 +0000 (15:50 +0000)]
back.rtlil: update for Yosys master.
whitequark [Mon, 17 Dec 2018 01:15:23 +0000 (01:15 +0000)]
back.rtlil: implement Array.
whitequark [Mon, 17 Dec 2018 01:05:08 +0000 (01:05 +0000)]
back.rtlil: implement Part.
whitequark [Sun, 16 Dec 2018 23:52:47 +0000 (23:52 +0000)]
back.rtlil: handle reset_less domains.
whitequark [Sun, 16 Dec 2018 23:51:24 +0000 (23:51 +0000)]
hdl.dsl: add clock domain support.
whitequark [Sun, 16 Dec 2018 23:44:00 +0000 (23:44 +0000)]
hdl.dsl: cleanup. NFC.
whitequark [Sun, 16 Dec 2018 22:26:58 +0000 (22:26 +0000)]
back.rtlil: extract _StatementCompiler. NFC.
whitequark [Sun, 16 Dec 2018 21:00:00 +0000 (21:00 +0000)]
back.rtlil: simplify. NFC.
whitequark [Sun, 16 Dec 2018 20:27:15 +0000 (20:27 +0000)]
back.rtlil: properly escape strings in attributes.
whitequark [Sun, 16 Dec 2018 18:09:01 +0000 (18:09 +0000)]
README: mention Yosys requirement.
whitequark [Sun, 16 Dec 2018 18:03:14 +0000 (18:03 +0000)]
back.rtlil: prepare for Yosys sigspec slicing improvements.
See YosysHQ/yosys#741.
whitequark [Sun, 16 Dec 2018 17:41:42 +0000 (17:41 +0000)]
compat.fhdl.structure: only convert to bool in If/Elif if necessary.
whitequark [Sun, 16 Dec 2018 17:41:11 +0000 (17:41 +0000)]
back.rtlil: avoid illegal slices.
Not sure what to do with {} [] on LHS yet--fix Yosys?
whitequark [Sun, 16 Dec 2018 16:20:45 +0000 (16:20 +0000)]
back.rtlil: use slicing to match shape when reducing width.
whitequark [Sun, 16 Dec 2018 16:05:38 +0000 (16:05 +0000)]
back.rtlil: don't emit a slice if all bits are used.
whitequark [Sun, 16 Dec 2018 13:30:20 +0000 (13:30 +0000)]
back.rtlil: reorganize value compiler into LHS/RHS.
This also implements Cat on LHS.
whitequark [Sun, 16 Dec 2018 11:26:31 +0000 (11:26 +0000)]
back.rtlil: fix naming. NFC.
whitequark [Sun, 16 Dec 2018 11:24:23 +0000 (11:24 +0000)]
hdl.xfrm: separate AST traversal from AST identity mapping.
This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
whitequark [Sun, 16 Dec 2018 10:38:25 +0000 (10:38 +0000)]
compat.fhdl: reexport Array.
whitequark [Sun, 16 Dec 2018 10:31:42 +0000 (10:31 +0000)]
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
whitequark [Sat, 15 Dec 2018 21:08:29 +0000 (21:08 +0000)]
test.sim: generalize assertOperator. NFC.
whitequark [Sat, 15 Dec 2018 21:01:38 +0000 (21:01 +0000)]
back.pysim: add (stub) LHSValueCompiler.
whitequark [Sat, 15 Dec 2018 20:58:06 +0000 (20:58 +0000)]
back.pysim: implement Part.
whitequark [Sat, 15 Dec 2018 20:42:52 +0000 (20:42 +0000)]
examples: rename clkdiv/ctrl to ctr/ctr_ce.
whitequark [Sat, 15 Dec 2018 20:40:51 +0000 (20:40 +0000)]
doc: update COMPAT_SUMMARY.
whitequark [Sat, 15 Dec 2018 19:37:36 +0000 (19:37 +0000)]
back.pysim: implement ArrayProxy.
whitequark [Sat, 15 Dec 2018 17:16:22 +0000 (17:16 +0000)]
hdl.ast: implement Array and ArrayProxy.
whitequark [Sat, 15 Dec 2018 17:03:23 +0000 (17:03 +0000)]
Lower Python version requirement to 3.6.
whitequark [Sat, 15 Dec 2018 16:13:53 +0000 (16:13 +0000)]
hdl: appropriately rename tests. NFC.
whitequark [Sat, 15 Dec 2018 14:58:31 +0000 (14:58 +0000)]
hdl.ast: improve ClockSignal, ResetSignal documentation.
whitequark [Sat, 15 Dec 2018 14:23:42 +0000 (14:23 +0000)]
Rename fhdl→hdl, genlib→lib.
whitequark [Sat, 15 Dec 2018 14:20:10 +0000 (14:20 +0000)]
Move star imports to make `from nmigen import *` usable.
whitequark [Sat, 15 Dec 2018 12:07:56 +0000 (12:07 +0000)]
doc: fix some Markdown awkwardness.
whitequark [Sat, 15 Dec 2018 12:04:52 +0000 (12:04 +0000)]
doc: update COMPAT_SUMMARY to reflect actual status.
whitequark [Sat, 15 Dec 2018 11:51:09 +0000 (11:51 +0000)]
Determine Migen's API surface and document compatibility summary.
This also reorganizes README to more clearly describe what nMigen is,
since it was getting quite outdated.
whitequark [Sat, 15 Dec 2018 10:09:14 +0000 (10:09 +0000)]
pyback.sim: test Slice, Cat, Repl.
whitequark [Sat, 15 Dec 2018 09:58:30 +0000 (09:58 +0000)]
fhdl.ast, back.pysim: implement shifts.
whitequark [Sat, 15 Dec 2018 09:46:20 +0000 (09:46 +0000)]
fhdl.ast: refactor Operator.shape(). NFC.
whitequark [Sat, 15 Dec 2018 09:31:58 +0000 (09:31 +0000)]
Consistently use '{!r}' in and only in TypeError messages.
whitequark [Sat, 15 Dec 2018 09:26:36 +0000 (09:26 +0000)]
fhdl.ir: test iter_comb(), iter_sync() and iter_signals().
whitequark [Sat, 15 Dec 2018 09:19:26 +0000 (09:19 +0000)]
fhdl.ir: fix incorrect uses of positive to say non-negative.
Also test Part and Slice properly.
whitequark [Sat, 15 Dec 2018 00:10:54 +0000 (00:10 +0000)]
compat.fhdl.structure: handle If/Elif with multi-bit condition.
whitequark [Fri, 14 Dec 2018 23:40:15 +0000 (23:40 +0000)]
compat.fhdl.module: allow adding native submodules to compat modules.