Luke Kenneth Casson Leighton [Mon, 11 May 2020 22:53:11 +0000 (23:53 +0100)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Luke Kenneth Casson Leighton [Mon, 11 May 2020 22:34:41 +0000 (23:34 +0100)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Yehowshua [Mon, 11 May 2020 22:27:49 +0000 (18:27 -0400)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Yehowshua [Mon, 11 May 2020 22:23:54 +0000 (18:23 -0400)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Luke Kenneth Casson Leighton [Mon, 11 May 2020 22:23:18 +0000 (23:23 +0100)]
Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Luke Kenneth Casson Leighton [Mon, 11 May 2020 22:19:59 +0000 (23:19 +0100)]
[libre-riscv-dev] ppc-dev linux patch support for microwatt!
bugzilla-daemon [Mon, 11 May 2020 21:20:50 +0000 (21:20 +0000)]
[libre-riscv-dev] [Bug 70] evaluate Bus Architectures
bugzilla-daemon [Mon, 11 May 2020 21:19:17 +0000 (21:19 +0000)]
[libre-riscv-dev] [Bug 70] evaluate Bus Architectures
Luke Kenneth Casson Leighton [Mon, 11 May 2020 18:37:03 +0000 (19:37 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Yehowshua [Mon, 11 May 2020 18:31:05 +0000 (14:31 -0400)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Mon, 11 May 2020 18:28:07 +0000 (19:28 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Mon, 11 May 2020 18:25:50 +0000 (19:25 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
bugzilla-daemon [Mon, 11 May 2020 18:23:29 +0000 (18:23 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 18:15:26 +0000 (18:15 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 17:52:59 +0000 (17:52 +0000)]
[libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla
Lauri Kasanen [Mon, 11 May 2020 17:34:21 +0000 (20:34 +0300)]
[libre-riscv-dev] PowerISA 3.1 (Power10) spec released
bugzilla-daemon [Mon, 11 May 2020 16:13:53 +0000 (16:13 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 16:13:04 +0000 (16:13 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 16:03:25 +0000 (16:03 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 15:51:36 +0000 (15:51 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 14:31:39 +0000 (14:31 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Michael Nolan [Mon, 11 May 2020 13:32:40 +0000 (09:32 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 11may2020
bugzilla-daemon [Mon, 11 May 2020 13:23:24 +0000 (13:23 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 12:43:28 +0000 (12:43 +0000)]
[libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla
bugzilla-daemon [Mon, 11 May 2020 12:28:35 +0000 (12:28 +0000)]
[libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla
bugzilla-daemon [Mon, 11 May 2020 12:28:05 +0000 (12:28 +0000)]
[libre-riscv-dev] [Bug 307] New: look at installing a kan-ban board on top of bugzilla
Luke Kenneth Casson Leighton [Mon, 11 May 2020 12:26:42 +0000 (13:26 +0100)]
[libre-riscv-dev] daily kan-ban update 11may2020
bugzilla-daemon [Mon, 11 May 2020 10:30:59 +0000 (10:30 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 01:11:55 +0000 (01:11 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Mon, 11 May 2020 00:04:15 +0000 (00:04 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 23:42:01 +0000 (23:42 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 23:15:34 +0000 (23:15 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 23:11:51 +0000 (23:11 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 23:06:51 +0000 (23:06 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 23:03:16 +0000 (23:03 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 13:46:03 +0000 (13:46 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Sun, 10 May 2020 13:01:02 +0000 (13:01 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Sun, 10 May 2020 11:36:43 +0000 (11:36 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Sun, 10 May 2020 11:36:20 +0000 (11:36 +0000)]
[libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC
bugzilla-daemon [Sun, 10 May 2020 11:34:24 +0000 (11:34 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Sun, 10 May 2020 11:33:38 +0000 (11:33 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Sun, 10 May 2020 11:33:23 +0000 (11:33 +0000)]
[libre-riscv-dev] [Bug 306] New: Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Sun, 10 May 2020 04:30:53 +0000 (04:30 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sun, 10 May 2020 04:25:04 +0000 (04:25 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 21:42:03 +0000 (21:42 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 21:35:01 +0000 (21:35 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 21:18:30 +0000 (21:18 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Sat, 9 May 2020 19:42:24 +0000 (20:42 +0100)]
Re: [libre-riscv-dev] Handling Interrupts
bugzilla-daemon [Sat, 9 May 2020 19:12:28 +0000 (19:12 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 19:08:05 +0000 (19:08 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 18:23:58 +0000 (18:23 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Yehowshua [Sat, 9 May 2020 17:23:58 +0000 (13:23 -0400)]
[libre-riscv-dev] Handling Interrupts
Yehowshua [Sat, 9 May 2020 14:39:10 +0000 (10:39 -0400)]
Re: [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor
Yehowshua [Sat, 9 May 2020 14:33:10 +0000 (10:33 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 08may2020
bugzilla-daemon [Sat, 9 May 2020 14:06:38 +0000 (14:06 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 14:04:31 +0000 (14:04 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 13:48:32 +0000 (13:48 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 13:45:26 +0000 (13:45 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 13:41:48 +0000 (13:41 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 13:37:42 +0000 (13:37 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Sat, 9 May 2020 13:13:41 +0000 (13:13 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Sat, 9 May 2020 13:08:52 +0000 (14:08 +0100)]
[libre-riscv-dev] insights about the selection of the design and architecture
Luke Kenneth Casson Leighton [Sat, 9 May 2020 11:33:05 +0000 (12:33 +0100)]
[libre-riscv-dev] daily kan-ban update 09may2020
Luke Kenneth Casson Leighton [Sat, 9 May 2020 10:02:13 +0000 (11:02 +0100)]
Re: [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor
Luke Kenneth Casson Leighton [Sat, 9 May 2020 09:59:13 +0000 (10:59 +0100)]
[libre-riscv-dev] pinmux to generate interfaces (with no pinmux)
Staf Verhaegen [Sat, 9 May 2020 09:12:40 +0000 (11:12 +0200)]
Re: [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor
Luke Kenneth Casson Leighton [Sat, 9 May 2020 08:25:32 +0000 (09:25 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08may2020
Luke Kenneth Casson Leighton [Sat, 9 May 2020 07:51:48 +0000 (08:51 +0100)]
Re: [libre-riscv-dev] spinlocks considered harmful
Yehowshua [Sat, 9 May 2020 00:31:29 +0000 (20:31 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 08may2020
Jacob Lifshay [Fri, 8 May 2020 23:21:48 +0000 (16:21 -0700)]
Re: [libre-riscv-dev] LD/ST CompUnit "working"
Jacob Lifshay [Fri, 8 May 2020 23:20:27 +0000 (16:20 -0700)]
[libre-riscv-dev] spinlocks considered harmful
Luke Kenneth Casson Leighton [Fri, 8 May 2020 23:18:32 +0000 (00:18 +0100)]
[libre-riscv-dev] LD/ST CompUnit "working"
Luke Kenneth Casson Leighton [Fri, 8 May 2020 23:11:26 +0000 (00:11 +0100)]
Re: [libre-riscv-dev] note on memory operation requirements for linux
Luke Kenneth Casson Leighton [Fri, 8 May 2020 23:09:50 +0000 (00:09 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08may2020
bugzilla-daemon [Fri, 8 May 2020 23:08:27 +0000 (23:08 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Fri, 8 May 2020 22:48:49 +0000 (23:48 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 22:45:26 +0000 (23:45 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 22:41:03 +0000 (23:41 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Jacob Lifshay [Fri, 8 May 2020 22:34:03 +0000 (15:34 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 08may2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 22:23:18 +0000 (23:23 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 22:19:00 +0000 (23:19 +0100)]
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
Jacob Lifshay [Fri, 8 May 2020 21:39:11 +0000 (14:39 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 20:47:24 +0000 (21:47 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Michael Nolan [Fri, 8 May 2020 20:47:18 +0000 (16:47 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Alain D D Williams [Fri, 8 May 2020 20:38:17 +0000 (21:38 +0100)]
[libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton [Fri, 8 May 2020 20:35:17 +0000 (21:35 +0100)]
Re: [libre-riscv-dev] minimum viable ASIC
Yehowshua [Fri, 8 May 2020 20:27:28 +0000 (16:27 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Jacob Lifshay [Fri, 8 May 2020 19:15:25 +0000 (12:15 -0700)]
[libre-riscv-dev] note on memory operation requirements for linux
Staf Verhaegen [Fri, 8 May 2020 19:08:50 +0000 (21:08 +0200)]
Re: [libre-riscv-dev] minimum viable ASIC
bugzilla-daemon [Fri, 8 May 2020 18:38:56 +0000 (18:38 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Staf Verhaegen [Fri, 8 May 2020 17:25:04 +0000 (19:25 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 08mar2020
Staf Verhaegen [Fri, 8 May 2020 17:23:35 +0000 (19:23 +0200)]
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
bugzilla-daemon [Fri, 8 May 2020 17:10:44 +0000 (17:10 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Fri, 8 May 2020 17:04:07 +0000 (17:04 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Fri, 8 May 2020 16:55:52 +0000 (17:55 +0100)]
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
bugzilla-daemon [Fri, 8 May 2020 16:54:32 +0000 (16:54 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Fri, 8 May 2020 16:48:11 +0000 (16:48 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Cole Poirier [Fri, 8 May 2020 16:01:57 +0000 (09:01 -0700)]
Re: [libre-riscv-dev] HDL_Workflow clarification
Luke Kenneth Casson Leighton [Fri, 8 May 2020 15:59:20 +0000 (16:59 +0100)]
Re: [libre-riscv-dev] HDL_Workflow clarification
Cole Poirier [Fri, 8 May 2020 15:42:33 +0000 (08:42 -0700)]
[libre-riscv-dev] HDL_Workflow clarification
projects / libre-riscv-dev.git / log