whitequark [Mon, 8 Jun 2020 17:38:11 +0000 (17:38 +0000)]
cxxrtl: don't check immutable values for changes in VCD writer.
This commit changes the VCD writer such that for all signals that
have `debug_item.type == VALUE && debug_item.next == nullptr`, it
would only sample the value once.
Commit
f2d7a187 added more debug information by including constant
wires, and decreased the performance of VCD writer proportionally
because the constant wires were still repeatedly sampled; this commit
eliminates the performance hit.
whitequark [Mon, 8 Jun 2020 17:29:08 +0000 (17:29 +0000)]
cxxrtl: emit debug information for constant wires.
Constant wires can represent a significant chunk of the design in
generic designs or after optimization. Emitting them in VCD files
significantly improves usability because gtkwave removes all traces
that are not present in the VCD file after reload, and iterative
development suffers if switching a varying signal to a constant
disrupts the workflow.
whitequark [Mon, 8 Jun 2020 16:36:26 +0000 (16:36 +0000)]
cxxrtl: track aliases in VCD writer.
This commit changes the VCD writer such that for all signals that
share `debug_item.curr`, it would only emit a single VCD identifier,
and sample the value once.
Commit
9b39c6f7 added redundancy to debug information by including
alias wires, and increased the size of VCD files proportionally; this
commit eliminates the redundancy from VCD files so that their size
is the same as before.
whitequark [Mon, 8 Jun 2020 16:22:30 +0000 (16:22 +0000)]
cxxrtl: emit debug information for alias wires.
Alias wires can represent a significant chunk of the design in highly
hierarchical designs; in Minerva SRAM, there are 273 member wires and
527 alias wires. Showing them in every hierarchy level significantly
improves usability.
whitequark [Mon, 8 Jun 2020 12:55:11 +0000 (12:55 +0000)]
cxxrtl: add missing installs of include files.
whitequark [Mon, 8 Jun 2020 04:08:09 +0000 (04:08 +0000)]
cxxrtl: fix typo in comment. NFC.
whitequark [Mon, 8 Jun 2020 03:21:08 +0000 (03:21 +0000)]
cxxrtl: minor debug-related improvements.
whitequark [Sun, 7 Jun 2020 20:32:00 +0000 (20:32 +0000)]
Merge pull request #2116 from whitequark/cxxrtl-vcd
cxxrtl: add a VCD writer using debug information
whitequark [Sun, 7 Jun 2020 03:48:40 +0000 (03:48 +0000)]
cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.
To avoid confusion with the C++ source files that are a part of
the simulation itself and not a part of Yosys build.
whitequark [Sun, 7 Jun 2020 03:45:53 +0000 (03:45 +0000)]
cxxrtl: add a C API for writing VCD dumps.
This C API is fully featured.
whitequark [Sat, 6 Jun 2020 21:55:53 +0000 (21:55 +0000)]
cxxrtl: only write VCD values that were actually updated.
On a representative design (Minerva SoC) this reduces VCD file size
by ~20× and runtime by ~3×.
whitequark [Sat, 6 Jun 2020 20:37:29 +0000 (20:37 +0000)]
cxxrtl: add a VCD writer using debug information.
whitequark [Sat, 6 Jun 2020 22:31:52 +0000 (22:31 +0000)]
Merge pull request #2115 from whitequark/cxxrtl-introspection
cxxrtl: add debug information to the C++ API, and add introspection via a new C API
whitequark [Fri, 5 Jun 2020 13:52:30 +0000 (13:52 +0000)]
cxxrtl: add a C API for driving and introspecting designs.
Compared to the C++ API, the C API currently has two limitations:
1. Memories cannot be updated in a race-free way.
2. Black boxes cannot be implemented in C.
whitequark [Wed, 27 May 2020 00:21:15 +0000 (00:21 +0000)]
cxxrtl: generate debug information for non-localized public wires.
Debug information describes values, wires, and memories with a simple
C-compatible layout. It can be emitted on demand into a map, which
has no runtime cost when it is unused, and allows late bound designs.
The `hdlname` attribute is used as the lookup key such that original
names, as emitted by the frontend, can be used for debugging and
introspection.
whitequark [Sat, 6 Jun 2020 12:23:06 +0000 (12:23 +0000)]
Merge pull request #2110 from BracketMaster/master
MacOS has even stricter stack limits in catalina.
whitequark [Fri, 5 Jun 2020 10:24:25 +0000 (10:24 +0000)]
Merge pull request #2113 from whitequark/cxxrtl-fix-sshr
cxxrtl: fix implementation of $sshr cell
N. Engelhardt [Fri, 5 Jun 2020 09:36:08 +0000 (11:36 +0200)]
Merge pull request #2109 from nakengelhardt/btor_internal_names
btor backend: make not printing internal names default
whitequark [Fri, 5 Jun 2020 01:31:53 +0000 (01:31 +0000)]
cxxrtl: fix implementation of $sshr cell.
Fixes #2111.
Yehowshua Immanuel [Thu, 4 Jun 2020 21:00:04 +0000 (17:00 -0400)]
more reasonable numbers for memory
Claire Wolf [Thu, 4 Jun 2020 20:25:47 +0000 (22:25 +0200)]
Add missing .gitignore file
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Yehowshua Immanuel [Thu, 4 Jun 2020 18:01:56 +0000 (14:01 -0400)]
MacOS has even stricter stack limits in catalina.
Invoking sby in macOS Catalina fails because of bizarre stack limits in Catalina.
clairexen [Thu, 4 Jun 2020 16:26:07 +0000 (18:26 +0200)]
Merge pull request #2041 from PeterCrozier/struct
Implementation of SV structs.
clairexen [Thu, 4 Jun 2020 16:23:33 +0000 (18:23 +0200)]
Merge pull request #2099 from Xiretza/manual-include-path
Use in-tree include directory in manual build
N. Engelhardt [Thu, 4 Jun 2020 16:20:08 +0000 (18:20 +0200)]
Add codeowners file (#2098)
Eddie Hung [Thu, 4 Jun 2020 15:15:25 +0000 (08:15 -0700)]
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
abc9: -dff improvements
N. Engelhardt [Thu, 4 Jun 2020 14:24:16 +0000 (16:24 +0200)]
btor backend: make not printing internal names default
Claire Wolf [Thu, 4 Jun 2020 13:53:28 +0000 (15:53 +0200)]
Add printf format attributes to btorf/infof helper functions
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
clairexen [Thu, 4 Jun 2020 13:48:40 +0000 (15:48 +0200)]
Merge pull request #2108 from nakengelhardt/btor_internal_names
btor backend: add option to not include internal names
N. Engelhardt [Thu, 4 Jun 2020 12:00:52 +0000 (14:00 +0200)]
btor backend: add option to not include internal names
whitequark [Thu, 4 Jun 2020 11:23:06 +0000 (11:23 +0000)]
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
Preserve 'signed'-ness of a verilog wire through RTLIL
N. Engelhardt [Thu, 4 Jun 2020 09:17:08 +0000 (11:17 +0200)]
Merge pull request #2070 from hackfin/master
Pyosys API: idict type handling
Eddie Hung [Thu, 4 Jun 2020 00:35:46 +0000 (17:35 -0700)]
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
abc9: fixes around handling combinatorial loops
Peter Crozier [Wed, 3 Jun 2020 16:19:28 +0000 (17:19 +0100)]
Merge branch 'master' into struct
Eddie Hung [Wed, 3 Jun 2020 15:41:55 +0000 (08:41 -0700)]
tests: tidy up testcase
Eddie Hung [Wed, 3 Jun 2020 15:37:07 +0000 (08:37 -0700)]
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings
tests: reduce test warnings
whitequark [Wed, 3 Jun 2020 12:45:02 +0000 (12:45 +0000)]
Merge pull request #2104 from whitequark/simplify-techmap
techmap: simplify
whitequark [Wed, 3 Jun 2020 01:44:06 +0000 (01:44 +0000)]
techmap: remove dead variable. NFC.
whitequark [Tue, 2 Jun 2020 23:17:46 +0000 (23:17 +0000)]
techmap: use C++11 default member initializers. NFC.
whitequark [Tue, 2 Jun 2020 22:34:01 +0000 (22:34 +0000)]
techmap: simplify.
`rewrite_filename` is already called in `Frontend::extra_args`.
whitequark [Tue, 2 Jun 2020 22:19:34 +0000 (22:19 +0000)]
techmap: use +/techmap.v instead of an ad-hoc code generator.
clairexen [Tue, 2 Jun 2020 15:13:08 +0000 (17:13 +0200)]
Merge pull request #2102 from YosysHQ/tests_fix
allow range for mux test
clairexen [Tue, 2 Jun 2020 15:12:02 +0000 (17:12 +0200)]
Merge pull request #2101 from YosysHQ/mmicko/verific_asymmetric
Support asymmetric memories for verific frontend
Miodrag Milanovic [Mon, 1 Jun 2020 11:48:19 +0000 (13:48 +0200)]
allow range for mux test
Miodrag Milanovic [Mon, 1 Jun 2020 08:30:03 +0000 (10:30 +0200)]
Support asymmetric memories for verific frontend
clairexen [Sun, 31 May 2020 18:40:48 +0000 (20:40 +0200)]
Merge pull request #1862 from boqwxp/cleanup_techmap
Clean up `passes/techmap/techmap.cc`
Eddie Hung [Sat, 30 May 2020 16:01:03 +0000 (09:01 -0700)]
abc9_ops: fix comment
Eddie Hung [Sat, 30 May 2020 15:59:20 +0000 (08:59 -0700)]
Merge pull request #2081 from YosysHQ/eddie/blackbox_ast
blackbox: use Module::makeblackbox() method
Eddie Hung [Sat, 30 May 2020 15:57:48 +0000 (08:57 -0700)]
abc9_ops: update messaging (credit to @Xiretza for spotting)
clairexen [Sat, 30 May 2020 13:04:51 +0000 (15:04 +0200)]
Merge pull request #2018 from boqwxp/qbfsat-timeout
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
Xiretza [Sat, 30 May 2020 09:21:40 +0000 (11:21 +0200)]
Use in-tree include directory in manual build
This is basically the same issue as in tests/various/plugin.sh,
which uses yosys-config to compile a plugin. `yosys-config --cxxflags`
points to `$PREFIX/share/` (/usr/local/share by default), which might
not exist yet or might be out of date. Building directly from the
headers in ./share/ avoids this.
Eddie Hung [Sat, 30 May 2020 00:33:10 +0000 (17:33 -0700)]
abc9_ops: optimise to not derive unless attribute exists
Eddie Hung [Sat, 30 May 2020 00:17:40 +0000 (17:17 -0700)]
abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
Alberto Gonzalez [Fri, 29 May 2020 21:30:24 +0000 (21:30 +0000)]
smtbmc: Remove superfluous `yosys-smt2-timeout` file macro.
Co-Authored-By: clairexen <claire@symbioticeda.com>
clairexen [Fri, 29 May 2020 14:52:11 +0000 (16:52 +0200)]
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic
ast/simplify: don't bitblast async ROMs declared as `logic`
clairexen [Fri, 29 May 2020 14:37:23 +0000 (16:37 +0200)]
Merge pull request #1885 from Xiretza/mod-rem-cells
Fix modulo/remainder semantics
clairexen [Fri, 29 May 2020 14:31:44 +0000 (16:31 +0200)]
Merge pull request #2092 from whitequark/rtlil-no-space-control
Restrict RTLIL::IdString to not contain whitespace or control chars
clairexen [Fri, 29 May 2020 14:23:10 +0000 (16:23 +0200)]
Merge pull request #2017 from boqwxp/qbfsat-cvc4
qbfsat: Add support for CVC4.
clairexen [Fri, 29 May 2020 14:21:45 +0000 (16:21 +0200)]
Merge pull request #2016 from boqwxp/qbfsat-yices
qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
whitequark [Fri, 29 May 2020 09:04:27 +0000 (09:04 +0000)]
Merge pull request #2097 from whitequark/ilang_lexer-fix-erange
ilang_lexer: fix check for out of range literal
whitequark [Mon, 18 May 2020 03:18:42 +0000 (03:18 +0000)]
ilang_lexer: fix check for out of range literal.
Commit
ca70a104 did not use a correct check.
whitequark [Fri, 29 May 2020 06:46:33 +0000 (06:46 +0000)]
Merge pull request #2033 from boqwxp/cleanup-verilog-lexer
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
whitequark [Wed, 27 May 2020 05:20:39 +0000 (05:20 +0000)]
Restrict RTLIL::IdString to not contain whitespace or control chars.
This is an existing invariant (most backends can't cope with these)
but one that was not checked or documented.
Xiretza [Thu, 28 May 2020 20:11:44 +0000 (22:11 +0200)]
Document division and modulo cells
Xiretza [Sat, 2 May 2020 09:30:30 +0000 (11:30 +0200)]
Update CHANGELOG
Xiretza [Sat, 2 May 2020 09:24:19 +0000 (11:24 +0200)]
Add comments for mod/div semantics to rtlil.h
Xiretza [Tue, 21 Apr 2020 14:37:29 +0000 (16:37 +0200)]
Expand tests/simple/constmuldivmod.v
Xiretza [Tue, 21 Apr 2020 10:51:58 +0000 (12:51 +0200)]
Add flooring division operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.
This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
Xiretza [Wed, 8 Apr 2020 17:30:47 +0000 (19:30 +0200)]
Add flooring modulo operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).
This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
whitequark [Thu, 28 May 2020 10:49:14 +0000 (10:49 +0000)]
Merge pull request #2095 from rswarbrick/hier-typo
Fix small typos in documentation for hierarchy command
Rupert Swarbrick [Thu, 28 May 2020 10:39:44 +0000 (11:39 +0100)]
Fix small typos in documentation for hierarchy command
whitequark [Thu, 28 May 2020 10:25:34 +0000 (10:25 +0000)]
Merge pull request #2091 from boqwxp/printattrs
Add `printattrs` command to print attributes of currently selected objects.
whitequark [Thu, 28 May 2020 10:00:49 +0000 (10:00 +0000)]
Merge pull request #2051 from Xiretza/makefile-cd-warning
Suppress warning during initial clone of ABC repo
whitequark [Thu, 28 May 2020 09:59:17 +0000 (09:59 +0000)]
Merge pull request #2031 from epfl-vlsc/master
Add extmodule support to firrtl backend
whitequark [Thu, 28 May 2020 09:42:58 +0000 (09:42 +0000)]
Merge pull request #2063 from boqwxp/techmapped-firrtl
firrtl: Accept techmapped cell types in FIRRTL backend.
whitequark [Thu, 28 May 2020 09:41:17 +0000 (09:41 +0000)]
Merge pull request #2088 from rswarbrick/count-at
Minor optimisation in Module::wire() and Module::cell()
whitequark [Thu, 28 May 2020 09:41:04 +0000 (09:41 +0000)]
Merge pull request #2087 from rswarbrick/lex-warn
Silence spurious warning in Verilog lexer when compiling with GCC
whitequark [Thu, 28 May 2020 09:40:49 +0000 (09:40 +0000)]
Merge pull request #2086 from rswarbrick/sigbit
Use default copy constructor for RTLIL::SigBit
whitequark [Thu, 28 May 2020 09:40:35 +0000 (09:40 +0000)]
Merge pull request #2084 from rswarbrick/c_str
Use c_str(), not str() for IdString/std::string == and != operators
Alberto Gonzalez [Thu, 28 May 2020 05:30:00 +0000 (05:30 +0000)]
printattrs: Simplify `get_indent_str()`.
Co-Authored-By: Xiretza <xiretza@xiretza.xyz>
Alberto Gonzalez [Wed, 27 May 2020 23:15:07 +0000 (23:15 +0000)]
printattrs: Refactor indentation string building for clarity.
Co-Authored-By: whitequark <whitequark@whitequark.org>
Alberto Gonzalez [Wed, 27 May 2020 07:58:10 +0000 (07:58 +0000)]
printattrs: Add test.
Alberto Gonzalez [Wed, 27 May 2020 07:40:40 +0000 (07:40 +0000)]
printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately.
Co-Authored-By: whitequark <whitequark@whitequark.org>
Alberto Gonzalez [Wed, 27 May 2020 04:07:34 +0000 (04:07 +0000)]
misc: Add `printattrs` command.
whitequark [Tue, 26 May 2020 22:18:14 +0000 (22:18 +0000)]
Merge pull request #2090 from whitequark/cxxrtl-fixes
Minor fixes for CXXRTL
whitequark [Tue, 26 May 2020 21:37:32 +0000 (21:37 +0000)]
cxxrtl: make logging a little bit nicer.
whitequark [Tue, 26 May 2020 06:00:40 +0000 (06:00 +0000)]
cxxrtl: add missing parts of commit
281c9685.
Rupert Swarbrick [Fri, 22 May 2020 13:29:42 +0000 (14:29 +0100)]
Silence spurious warning in Verilog lexer when compiling with GCC
The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.
Rupert Swarbrick [Tue, 26 May 2020 14:19:39 +0000 (15:19 +0100)]
Minor optimisation in Module::wire() and Module::cell()
The existing code does a search to figure out whether id is in the
dict (with the call to count()), and then looks it up again to get the
result (with the call to at()). This version calls find() instead,
avoiding the double lookup.
Code size increases slightly (6kb). I think this is because the
contents of find() are getting inlined, and then inlined into lots of
the callsites for cell() and wire().
Looking at the compiled code before this patch, you just get
a (non-inlined) call to count() followed by a call to at(). After the
patch, the contents of find() have been inlined (so you see do_hash,
then do_lookup). The result for each function is about 30 bytes / 40%
bigger, which presumably also enlarges call-sites that inline it.
Rupert Swarbrick [Fri, 22 May 2020 15:59:24 +0000 (16:59 +0100)]
Use default copy constructor for RTLIL::SigBit
There was a handwritten copy constructor, which I'm not sure was
actually legal C++ (it unconditionally read from the 'data' member of
a union, which wouldn't have been written if wire was true). It was
also a bit less efficient than the constructor you get from the
compiler by default (which is allowed to just copy the memory).
This gives a marginal (~0.25%) decrease in code size when compiled
with GCC 9.3.
Rupert Swarbrick [Tue, 26 May 2020 10:51:06 +0000 (11:51 +0100)]
Use c_str(), not str() for IdString/std::string == and != operators
These operators work by fetching the string from the global string
table and then comparing with the std::string that was passed in as
rhs.
Using str() means that we create a std::string (strlen; malloc;
memcpy), compare for equality (another memcmp if they have the same
length) and then finally free the string.
Using c_str() means that we pass the const char* straight to
std::string's equality operator. This ends up as a call to
std::string::compare (the const char* flavour), which is essentially
strcmp.
Eddie Hung [Mon, 25 May 2020 23:40:53 +0000 (16:40 -0700)]
abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposort
Eddie Hung [Mon, 25 May 2020 23:40:30 +0000 (16:40 -0700)]
xaiger: promote abc9_keep wires
Eddie Hung [Mon, 25 May 2020 23:39:16 +0000 (16:39 -0700)]
tests: add ecp5 latch testcase with -abc9
Eddie Hung [Mon, 25 May 2020 21:21:10 +0000 (14:21 -0700)]
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
xilinx: tidy up cells_sim.v a little
Alberto Gonzalez [Fri, 1 May 2020 23:17:35 +0000 (23:17 +0000)]
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
Alberto Gonzalez [Fri, 1 May 2020 08:12:23 +0000 (08:12 +0000)]
qbfsat: Add support for CVC4.
Alberto Gonzalez [Mon, 25 May 2020 20:32:13 +0000 (20:32 +0000)]
qbfsat: Move SMT2 info statements back to the top of the file.
Alberto Gonzalez [Thu, 30 Apr 2020 21:27:18 +0000 (21:27 +0000)]
qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.
Eddie Hung [Mon, 25 May 2020 17:53:49 +0000 (10:53 -0700)]
blackbox: re-use existing Module::makeblackbox() method