yosys.git
5 years agoMerge remote-tracking branch 'origin/master' into xc7srl
Eddie Hung [Fri, 22 Mar 2019 20:10:42 +0000 (13:10 -0700)]
Merge remote-tracking branch 'origin/master' into xc7srl

5 years agoMerge pull request #889 from YosysHQ/clifford/fix888
Clifford Wolf [Fri, 22 Mar 2019 17:03:06 +0000 (18:03 +0100)]
Merge pull request #889 from YosysHQ/clifford/fix888

Fix mem2reg handling of memories with upto data ports

5 years agoMerge pull request #890 from YosysHQ/clifford/fix887
Clifford Wolf [Fri, 22 Mar 2019 17:02:29 +0000 (18:02 +0100)]
Merge pull request #890 from YosysHQ/clifford/fix887

Trim init attributes when resizing FFs in "wreduce"

5 years agoMerge pull request #891 from YosysHQ/xilinx_keep
David Shah [Fri, 22 Mar 2019 14:28:29 +0000 (14:28 +0000)]
Merge pull request #891 from YosysHQ/xilinx_keep

xilinx: Add keep attribute where appropriate

5 years agoxilinx: Add keep attribute where appropriate
David Shah [Fri, 22 Mar 2019 13:57:17 +0000 (13:57 +0000)]
xilinx: Add keep attribute where appropriate

Signed-off-by: David Shah <dave@ds0.me>
5 years agoTrim init attributes when resizing FFs in "wreduce", fixes #887
Clifford Wolf [Fri, 22 Mar 2019 10:42:19 +0000 (11:42 +0100)]
Trim init attributes when resizing FFs in "wreduce", fixes #887

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd '-nosrl' option to synth_xilinx
Eddie Hung [Thu, 21 Mar 2019 22:04:44 +0000 (15:04 -0700)]
Add '-nosrl' option to synth_xilinx

5 years agoFix mem2reg handling of memories with upto data ports, fixes #888
Clifford Wolf [Thu, 21 Mar 2019 21:19:17 +0000 (22:19 +0100)]
Fix mem2reg handling of memories with upto data ports, fixes #888

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove "read_verilog -dump_vlog[12]" handling of upto ranges
Clifford Wolf [Thu, 21 Mar 2019 21:20:16 +0000 (22:20 +0100)]
Improve "read_verilog -dump_vlog[12]" handling of upto ranges

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove read_verilog debug output capabilities
Clifford Wolf [Thu, 21 Mar 2019 19:52:29 +0000 (20:52 +0100)]
Improve read_verilog debug output capabilities

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoOpt
Eddie Hung [Thu, 21 Mar 2019 17:20:27 +0000 (10:20 -0700)]
Opt

5 years agoFix spacing
Eddie Hung [Wed, 20 Mar 2019 19:28:39 +0000 (12:28 -0700)]
Fix spacing

5 years agoFine tune cells_map.v
Eddie Hung [Wed, 20 Mar 2019 17:55:14 +0000 (10:55 -0700)]
Fine tune cells_map.v

5 years agoRevert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
Eddie Hung [Wed, 20 Mar 2019 04:58:05 +0000 (21:58 -0700)]
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length

5 years agoAdd support for variable length Xilinx SRL > 128
Eddie Hung [Wed, 20 Mar 2019 00:44:33 +0000 (17:44 -0700)]
Add support for variable length Xilinx SRL > 128

5 years agoRestore original synth_xilinx commands
Eddie Hung [Tue, 19 Mar 2019 23:14:08 +0000 (16:14 -0700)]
Restore original synth_xilinx commands

5 years agoFix spacing
Eddie Hung [Tue, 19 Mar 2019 23:12:32 +0000 (16:12 -0700)]
Fix spacing

5 years agoshregmap -tech xilinx to delete $shiftx for var length SRL
Eddie Hung [Tue, 19 Mar 2019 22:05:08 +0000 (15:05 -0700)]
shregmap -tech xilinx to delete $shiftx for var length SRL

5 years agoFix INIT for variable length SRs that have been bumped up one
Eddie Hung [Tue, 19 Mar 2019 21:54:43 +0000 (14:54 -0700)]
Fix INIT for variable length SRs that have been bumped up one

5 years agoMerge remote-tracking branch 'origin/master' into xc7srl
Eddie Hung [Tue, 19 Mar 2019 20:11:30 +0000 (13:11 -0700)]
Merge remote-tracking branch 'origin/master' into xc7srl

5 years agoMake output port a non chain user
Eddie Hung [Tue, 19 Mar 2019 20:08:43 +0000 (13:08 -0700)]
Make output port a non chain user

5 years agoMerge pull request #885 from YosysHQ/clifford/fix873
Clifford Wolf [Tue, 19 Mar 2019 19:31:53 +0000 (20:31 +0100)]
Merge pull request #885 from YosysHQ/clifford/fix873

Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873

5 years agoAdd Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
Clifford Wolf [Tue, 19 Mar 2019 19:29:54 +0000 (20:29 +0100)]
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #808 from eddiehung/read_aiger
Eddie Hung [Tue, 19 Mar 2019 16:41:40 +0000 (09:41 -0700)]
Merge pull request #808 from eddiehung/read_aiger

Add new read_aiger frontend

5 years agoMerge https://github.com/YosysHQ/yosys into read_aiger
Eddie Hung [Tue, 19 Mar 2019 15:52:31 +0000 (08:52 -0700)]
Merge https://github.com/YosysHQ/yosys into read_aiger

5 years agoAdd author name
Eddie Hung [Tue, 19 Mar 2019 15:52:06 +0000 (08:52 -0700)]
Add author name

5 years agoMerge pull request #884 from zachjs/master
Clifford Wolf [Tue, 19 Mar 2019 13:08:57 +0000 (14:08 +0100)]
Merge pull request #884 from zachjs/master

fix local name resolution in prefix constructs

5 years agofix local name resolution in prefix constructs
Zachary Snow [Tue, 19 Mar 2019 00:34:21 +0000 (20:34 -0400)]
fix local name resolution in prefix constructs

5 years agoFix shregmap to correctly recognise non chain users; cleanup
Eddie Hung [Mon, 18 Mar 2019 23:12:19 +0000 (16:12 -0700)]
Fix shregmap to correctly recognise non chain users; cleanup

5 years agoshiftx NULL pointer check
Eddie Hung [Mon, 18 Mar 2019 20:35:54 +0000 (13:35 -0700)]
shiftx NULL pointer check

5 years agoUpdate issue template
Clifford Wolf [Sun, 17 Mar 2019 11:53:47 +0000 (12:53 +0100)]
Update issue template

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoUpdate issue template
Clifford Wolf [Sun, 17 Mar 2019 11:44:23 +0000 (12:44 +0100)]
Update issue template

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoCleanup
Eddie Hung [Sat, 16 Mar 2019 19:49:46 +0000 (12:49 -0700)]
Cleanup

5 years agoOnly accept <128 for variable length, only if $shiftx exclusive
Eddie Hung [Sat, 16 Mar 2019 15:51:13 +0000 (08:51 -0700)]
Only accept <128 for variable length, only if $shiftx exclusive

5 years agoMerge pull request #877 from FelixVi/master
Clifford Wolf [Sat, 16 Mar 2019 13:19:02 +0000 (14:19 +0100)]
Merge pull request #877 from FelixVi/master

Add note about test requirements in README

5 years agoAdd note about test requirements in README
Felix Vietmeyer [Sat, 16 Mar 2019 12:20:59 +0000 (06:20 -0600)]
Add note about test requirements in README

5 years agoCleanup synth_xilinx
Eddie Hung [Sat, 16 Mar 2019 06:01:40 +0000 (23:01 -0700)]
Cleanup synth_xilinx

5 years agoWorking
Eddie Hung [Sat, 16 Mar 2019 02:13:40 +0000 (19:13 -0700)]
Working

5 years agoImprove mix of src/wire/wirebit coverage in "mutate -list"
Clifford Wolf [Fri, 15 Mar 2019 23:55:46 +0000 (00:55 +0100)]
Improve mix of src/wire/wirebit coverage in "mutate -list"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #876 from YosysHQ/clifford/fmcombine
Clifford Wolf [Fri, 15 Mar 2019 23:17:15 +0000 (00:17 +0100)]
Merge pull request #876 from YosysHQ/clifford/fmcombine

Add fmcombine pass

5 years agoAdd "fmcombine -fwd -bwd -nop"
Clifford Wolf [Fri, 15 Mar 2019 20:45:37 +0000 (21:45 +0100)]
Add "fmcombine -fwd -bwd -nop"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd fmcombine pass
Clifford Wolf [Fri, 15 Mar 2019 19:18:38 +0000 (20:18 +0100)]
Add fmcombine pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #875 from YosysHQ/clifford/mutate
Clifford Wolf [Thu, 14 Mar 2019 23:51:40 +0000 (00:51 +0100)]
Merge pull request #875 from YosysHQ/clifford/mutate

Add "mutate" pass

5 years agoDisable realmath tests
Clifford Wolf [Thu, 14 Mar 2019 23:48:23 +0000 (00:48 +0100)]
Disable realmath tests

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprovements in "mutate" list-reduce algorithm
Clifford Wolf [Thu, 14 Mar 2019 23:18:31 +0000 (00:18 +0100)]
Improvements in "mutate" list-reduce algorithm

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd "mutate -cfg", improve pick_cover behavior
Clifford Wolf [Thu, 14 Mar 2019 22:20:41 +0000 (23:20 +0100)]
Add "mutate -cfg", improve pick_cover behavior

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd a strictly coverage-driven mutation selection strategy
Clifford Wolf [Thu, 14 Mar 2019 22:01:55 +0000 (23:01 +0100)]
Add a strictly coverage-driven mutation selection strategy

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove "mutate" wire coverage metric
Clifford Wolf [Thu, 14 Mar 2019 22:01:01 +0000 (23:01 +0100)]
Improve "mutate" wire coverage metric

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd more mutation types, improve mutation src cover
Clifford Wolf [Thu, 14 Mar 2019 18:52:02 +0000 (19:52 +0100)]
Add more mutation types, improve mutation src cover

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix smtbmc.py handling of zero appended steps
Clifford Wolf [Wed, 13 Mar 2019 18:27:17 +0000 (19:27 +0100)]
Fix smtbmc.py handling of zero appended steps

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd "mutate" command DB reduce functionality
Clifford Wolf [Wed, 13 Mar 2019 16:36:37 +0000 (17:36 +0100)]
Add "mutate" command DB reduce functionality

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd hashlib "<container>::element(int n)" methods
Clifford Wolf [Wed, 13 Mar 2019 16:36:06 +0000 (17:36 +0100)]
Add hashlib "<container>::element(int n)" methods

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd "mutate -mode inv", various other mutate improvements
Clifford Wolf [Wed, 13 Mar 2019 15:09:47 +0000 (16:09 +0100)]
Add "mutate -mode inv", various other mutate improvements

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd basic "mutate -list N" framework
Clifford Wolf [Tue, 12 Mar 2019 16:01:59 +0000 (17:01 +0100)]
Add basic "mutate -list N" framework

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #874 from YosysHQ/clifford/andopt
Clifford Wolf [Thu, 14 Mar 2019 20:22:16 +0000 (21:22 +0100)]
Merge pull request #874 from YosysHQ/clifford/andopt

Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327

5 years agoImprove handling of and-with-1 and or-with-0 in opt_expr, fixes #327
Clifford Wolf [Thu, 14 Mar 2019 19:35:15 +0000 (20:35 +0100)]
Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #872 from YosysHQ/clifford/pmuxfix
Clifford Wolf [Thu, 14 Mar 2019 17:42:45 +0000 (18:42 +0100)]
Merge pull request #872 from YosysHQ/clifford/pmuxfix

Improve handling of "full_case" attributes

5 years agoImprove handling of "full_case" attributes
Clifford Wolf [Thu, 14 Mar 2019 16:51:21 +0000 (17:51 +0100)]
Improve handling of "full_case" attributes

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix a syntax bug in ilang backend related to process case statements
Clifford Wolf [Thu, 14 Mar 2019 16:50:20 +0000 (17:50 +0100)]
Fix a syntax bug in ilang backend related to process case statements

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoReverse bits in INIT parameter for Xilinx, since MSB is shifted first
Eddie Hung [Thu, 14 Mar 2019 16:38:42 +0000 (09:38 -0700)]
Reverse bits in INIT parameter for Xilinx, since MSB is shifted first

5 years agoMisspell
Eddie Hung [Thu, 14 Mar 2019 16:06:56 +0000 (09:06 -0700)]
Misspell

5 years agoRevert "Add shregmap -init_msb_first and use in synth_xilinx"
Eddie Hung [Thu, 14 Mar 2019 16:01:48 +0000 (09:01 -0700)]
Revert "Add shregmap -init_msb_first and use in synth_xilinx"

This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75.

5 years agoMerge remote-tracking branch 'origin/master' into xc7srl
Eddie Hung [Thu, 14 Mar 2019 15:59:19 +0000 (08:59 -0700)]
Merge remote-tracking branch 'origin/master' into xc7srl

5 years agoMerge pull request #869 from cr1901/win-shell
Clifford Wolf [Thu, 14 Mar 2019 15:43:23 +0000 (16:43 +0100)]
Merge pull request #869 from cr1901/win-shell

Install launcher executable when running yosys-smtbmc on Windows.

5 years agoAdd shregmap -init_msb_first and use in synth_xilinx
Eddie Hung [Thu, 14 Mar 2019 15:10:02 +0000 (08:10 -0700)]
Add shregmap -init_msb_first and use in synth_xilinx

5 years agoFix cells_map for SRL
Eddie Hung [Thu, 14 Mar 2019 15:09:48 +0000 (08:09 -0700)]
Fix cells_map for SRL

5 years agoMove shregmap until after first techmap
Eddie Hung [Thu, 14 Mar 2019 00:13:52 +0000 (17:13 -0700)]
Move shregmap until after first techmap

5 years agoRefactor $__SHREG__ in cells_map.v
Eddie Hung [Wed, 13 Mar 2019 23:17:54 +0000 (16:17 -0700)]
Refactor $__SHREG__ in cells_map.v

5 years agoInstall launcher executable when running yosys-smtbmc on Windows.
William D. Jones [Tue, 12 Mar 2019 21:55:47 +0000 (17:55 -0400)]
Install launcher executable when running yosys-smtbmc on Windows.

Signed-off-by: William D. Jones <thor0505@comcast.net>
5 years agoMerge pull request #868 from YosysHQ/clifford/fixmem
Clifford Wolf [Wed, 13 Mar 2019 12:40:30 +0000 (13:40 +0100)]
Merge pull request #868 from YosysHQ/clifford/fixmem

Various mem2reg-related improvements in handling of memories

5 years agoFix a bug in handling quotes in multi-cmd lines in Yosys scripts
Clifford Wolf [Tue, 12 Mar 2019 20:14:50 +0000 (21:14 +0100)]
Fix a bug in handling quotes in multi-cmd lines in Yosys scripts

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #866 from YosysHQ/clifford/idstuff
Clifford Wolf [Tue, 12 Mar 2019 19:27:36 +0000 (20:27 +0100)]
Merge pull request #866 from YosysHQ/clifford/idstuff

Improve determinism of IdString DB for similar scripts

5 years agoRemove ice40/cells_sim.v hack to avoid warning for blocking memory writes
Clifford Wolf [Tue, 12 Mar 2019 19:14:18 +0000 (20:14 +0100)]
Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove handling of memories used in mem index expressions on LHS of an assignment
Clifford Wolf [Tue, 12 Mar 2019 19:12:02 +0000 (20:12 +0100)]
Improve handling of memories used in mem index expressions on LHS of an assignment

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoRemove outdated "blocking assignment to memory" warning
Clifford Wolf [Tue, 12 Mar 2019 19:10:55 +0000 (20:10 +0100)]
Remove outdated "blocking assignment to memory" warning

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoOnly set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867
Clifford Wolf [Tue, 12 Mar 2019 19:09:47 +0000 (20:09 +0100)]
Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove determinism of IdString DB for similar scripts
Clifford Wolf [Mon, 11 Mar 2019 19:12:28 +0000 (20:12 +0100)]
Improve determinism of IdString DB for similar scripts

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #864 from YosysHQ/svalabelfix
Eddie Hung [Mon, 11 Mar 2019 18:58:07 +0000 (11:58 -0700)]
Merge pull request #864 from YosysHQ/svalabelfix

Fix handling of cases that look like sva labels, fixes #862

5 years agoAdd ENABLE_GLOB Makefile switch
Clifford Wolf [Mon, 11 Mar 2019 08:08:36 +0000 (01:08 -0700)]
Add ENABLE_GLOB Makefile switch

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix handling of cases that look like sva labels, fixes #862
Clifford Wolf [Sun, 10 Mar 2019 23:27:18 +0000 (16:27 -0700)]
Fix handling of cases that look like sva labels, fixes #862

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix typo in ice40_braminit help msg
Clifford Wolf [Sat, 9 Mar 2019 21:24:55 +0000 (13:24 -0800)]
Fix typo in ice40_braminit help msg

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #859 from smunaut/ice40_braminit
Clifford Wolf [Sat, 9 Mar 2019 21:24:10 +0000 (13:24 -0800)]
Merge pull request #859 from smunaut/ice40_braminit

iCE40 BRAM primitives init from file

5 years agoFix signed $shift/$shiftx handling in write_smt2
Clifford Wolf [Sat, 9 Mar 2019 21:19:41 +0000 (13:19 -0800)]
Fix signed $shift/$shiftx handling in write_smt2

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd $dffsr support to async2sync
Clifford Wolf [Sat, 9 Mar 2019 19:52:00 +0000 (11:52 -0800)]
Add $dffsr support to async2sync

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #858 from YosysHQ/clifford/svalabels
Clifford Wolf [Sat, 9 Mar 2019 19:14:57 +0000 (11:14 -0800)]
Merge pull request #858 from YosysHQ/clifford/svalabels

Add support for using SVA labels in yosys-smtbmc console output

5 years agoMerge pull request #861 from YosysHQ/verific_chparam
Clifford Wolf [Sat, 9 Mar 2019 07:02:56 +0000 (23:02 -0800)]
Merge pull request #861 from YosysHQ/verific_chparam

Add -chparam option to verific command

5 years agoAlso add support for labels on sva module items, fixes #699
Clifford Wolf [Sat, 9 Mar 2019 06:53:58 +0000 (22:53 -0800)]
Also add support for labels on sva module items, fixes #699

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoUpdate help message for -chparam
Eddie Hung [Sat, 9 Mar 2019 01:56:16 +0000 (01:56 +0000)]
Update help message for -chparam

5 years agoAdd -chparam option to verific command
Eddie Hung [Sat, 9 Mar 2019 01:54:01 +0000 (01:54 +0000)]
Add -chparam option to verific command

5 years agoFix spelling
Eddie Hung [Sat, 9 Mar 2019 00:43:50 +0000 (00:43 +0000)]
Fix spelling

5 years agoMerge branch 'master' of github.com:YosysHQ/yosys
Clifford Wolf [Fri, 8 Mar 2019 06:44:50 +0000 (22:44 -0800)]
Merge branch 'master' of github.com:YosysHQ/yosys

5 years agoFix handling of task output ports in clocked always blocks, fixes #857
Clifford Wolf [Fri, 8 Mar 2019 06:44:37 +0000 (22:44 -0800)]
Fix handling of task output ports in clocked always blocks, fixes #857

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoice40: Run ice40_braminit pass by default
Sylvain Munaut [Thu, 7 Mar 2019 23:11:17 +0000 (00:11 +0100)]
ice40: Run ice40_braminit pass by default

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
5 years agoice40: Add ice40_braminit pass to allow initialization of BRAM from file
Sylvain Munaut [Thu, 7 Mar 2019 22:48:10 +0000 (23:48 +0100)]
ice40: Add ice40_braminit pass to allow initialization of BRAM from file

This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
5 years agoMerge pull request #856 from kprasadvnsi/master
Clifford Wolf [Thu, 7 Mar 2019 19:34:12 +0000 (11:34 -0800)]
Merge pull request #856 from kprasadvnsi/master

examples/anlogic/ now also output the SVF file.

5 years agoUse SVA label in smt export if available
Clifford Wolf [Thu, 7 Mar 2019 19:31:46 +0000 (11:31 -0800)]
Use SVA label in smt export if available

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd support for SVA labels in read_verilog
Clifford Wolf [Thu, 7 Mar 2019 19:17:32 +0000 (11:17 -0800)]
Add support for SVA labels in read_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd hack for handling SVA labels via Verific
Clifford Wolf [Thu, 7 Mar 2019 18:52:44 +0000 (10:52 -0800)]
Add hack for handling SVA labels via Verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd link to SF2 / igloo2 macro library guide
Clifford Wolf [Thu, 7 Mar 2019 17:08:26 +0000 (09:08 -0800)]
Add link to SF2 / igloo2 macro library guide

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprovements in sf2 cells_sim.v
Clifford Wolf [Thu, 7 Mar 2019 00:18:49 +0000 (16:18 -0800)]
Improvements in sf2 cells_sim.v

Signed-off-by: Clifford Wolf <clifford@clifford.at>