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Jean THOMAS [Mon, 8 Jun 2020 09:16:38 +0000 (11:16 +0200)]
Add copyright
Jean THOMAS [Mon, 8 Jun 2020 09:16:04 +0000 (11:16 +0200)]
Remove setaddr for submodule instanciation
Jean THOMAS [Mon, 8 Jun 2020 09:15:12 +0000 (11:15 +0200)]
Fix multiple drive issue
Jean THOMAS [Mon, 8 Jun 2020 09:14:42 +0000 (11:14 +0200)]
Add copyright
Jean THOMAS [Mon, 8 Jun 2020 09:12:43 +0000 (11:12 +0200)]
Fix PLL
Jean THOMAS [Fri, 5 Jun 2020 10:00:52 +0000 (12:00 +0200)]
Remove bandwidth meter
Jean THOMAS [Fri, 5 Jun 2020 10:00:42 +0000 (12:00 +0200)]
Fix direction in stream assignment
Jean THOMAS [Fri, 5 Jun 2020 08:35:02 +0000 (10:35 +0200)]
Fix typo
Jean THOMAS [Fri, 5 Jun 2020 08:29:19 +0000 (10:29 +0200)]
Remove useless variable
Jean THOMAS [Fri, 5 Jun 2020 08:29:08 +0000 (10:29 +0200)]
Fix signal drive error
Jean THOMAS [Fri, 5 Jun 2020 07:45:08 +0000 (09:45 +0200)]
Fix multi-driven signals in refresher
Jean THOMAS [Thu, 4 Jun 2020 17:17:21 +0000 (19:17 +0200)]
Bugfixing
Jean THOMAS [Thu, 4 Jun 2020 15:06:22 +0000 (17:06 +0200)]
Correct nMigen transition bugs
Jean THOMAS [Thu, 4 Jun 2020 09:54:15 +0000 (11:54 +0200)]
Add dram core as submodule
Jean THOMAS [Thu, 4 Jun 2020 09:46:38 +0000 (11:46 +0200)]
More nMigen conversion and fixes
Jean THOMAS [Thu, 4 Jun 2020 09:46:13 +0000 (11:46 +0200)]
Add second clock
Jean THOMAS [Thu, 4 Jun 2020 09:44:42 +0000 (11:44 +0200)]
Remove diff pairs in ECPIX5Platform
There is a weird issue occuring with diff pairs for clk and dqs signals. I double checked if those pins could be used for differential signals and it seems ok.
Jean THOMAS [Wed, 3 Jun 2020 18:58:22 +0000 (20:58 +0200)]
Initial commit
projects / gram.git / log