nmigen.git
5 years agohdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns.
whitequark [Mon, 16 Sep 2019 18:59:28 +0000 (18:59 +0000)]
hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns.

Fixes #207.

5 years agohdl.ast: add Value.matches(), accepting same language as Case().
whitequark [Sat, 14 Sep 2019 21:06:12 +0000 (21:06 +0000)]
hdl.ast: add Value.matches(), accepting same language as Case().

Fixes #202.

5 years agohdl.dsl: improve error messages for Case().
whitequark [Sat, 14 Sep 2019 20:46:10 +0000 (20:46 +0000)]
hdl.dsl: improve error messages for Case().

5 years agohdl.ast: add Value.xor, mapping to $reduce_xor.
whitequark [Fri, 13 Sep 2019 14:28:43 +0000 (14:28 +0000)]
hdl.ast: add Value.xor, mapping to $reduce_xor.

Fixes #147.

5 years agohdl.ast: add Value.{any,all}, mapping to $reduce_{or,and}.
whitequark [Fri, 13 Sep 2019 13:14:52 +0000 (13:14 +0000)]
hdl.ast: add Value.{any,all}, mapping to $reduce_{or,and}.

Refs #147.

5 years agolib.fifo: adjust for new CDC primitive conventions.
whitequark [Thu, 12 Sep 2019 20:01:28 +0000 (20:01 +0000)]
lib.fifo: adjust for new CDC primitive conventions.

Fixes #97.

5 years agolib.fifo: adjust properties to have consistent naming.
whitequark [Thu, 12 Sep 2019 19:51:01 +0000 (19:51 +0000)]
lib.fifo: adjust properties to have consistent naming.

5 years agobuild.plat: bypass tool detection if NMIGEN_*_env is set.
whitequark [Thu, 12 Sep 2019 21:56:48 +0000 (21:56 +0000)]
build.plat: bypass tool detection if NMIGEN_*_env is set.

It's not practical to detect tools within the toolchain environment
for various reasons, so just assume the tools are there if the user
says they are.

Before this commit, the tools would be searched outside the toolchain
environment, which of course would always fail for Vivado, ISE, etc.

5 years agovendor.xilinx_7series: Vivado requires bash on *nix as well.
whitequark [Thu, 12 Sep 2019 21:49:08 +0000 (21:49 +0000)]
vendor.xilinx_7series: Vivado requires bash on *nix as well.

5 years agohdl.mem: use keyword-only arguments as appropriate.
whitequark [Thu, 12 Sep 2019 20:03:48 +0000 (20:03 +0000)]
hdl.mem: use keyword-only arguments as appropriate.

5 years agolib.fifo: make fwft a keyword-only argument.
whitequark [Thu, 12 Sep 2019 19:36:45 +0000 (19:36 +0000)]
lib.fifo: make fwft a keyword-only argument.

Because it accepts a boolean.

5 years agolib.fifo: remove SyncFIFO.replace.
whitequark [Thu, 12 Sep 2019 19:14:56 +0000 (19:14 +0000)]
lib.fifo: remove SyncFIFO.replace.

This obscure functionality was likely only ever used in old MiSoC
code, and doesn't justify the added complexity. It was also not
provided (and could not be reasonably provided) in SyncFIFOBuffered,
which made its utility extremely marginal.

5 years agoREADME: update Yosys version requirement.
whitequark [Thu, 12 Sep 2019 14:33:38 +0000 (14:33 +0000)]
README: update Yosys version requirement.

5 years agolib.cdc: make domain properties private.
whitequark [Thu, 12 Sep 2019 13:54:48 +0000 (13:54 +0000)]
lib.cdc: make domain properties private.

It is not correct to access domain properties from user code, because
it will not match the reality if DomainRenamer has been applied to
the module.

5 years agolib.io: style. NFC.
whitequark [Thu, 12 Sep 2019 13:51:18 +0000 (13:51 +0000)]
lib.io: style. NFC.

5 years agolib.cdc: adjust ResetSynchronizer for new CDC primitive conventions.
whitequark [Thu, 12 Sep 2019 13:48:45 +0000 (13:48 +0000)]
lib.cdc: adjust ResetSynchronizer for new CDC primitive conventions.

Refs #97.

5 years agolib.cdc: adjust MultiReg for new CDC primitive conventions.
whitequark [Thu, 12 Sep 2019 13:48:24 +0000 (13:48 +0000)]
lib.cdc: adjust MultiReg for new CDC primitive conventions.

Refs #97.

5 years agobuild.plat,vendor: allow clock constraints on arbitrary signals.
whitequark [Wed, 11 Sep 2019 23:35:43 +0000 (23:35 +0000)]
build.plat,vendor: allow clock constraints on arbitrary signals.

Currently only done for Synopsys based toolchains (i.e. not nextpnr).

Refs #88.

5 years agoback: return name map from convert_fragment().
whitequark [Wed, 11 Sep 2019 23:14:00 +0000 (23:14 +0000)]
back: return name map from convert_fragment().

5 years agohdl.ast: warn if reset value is truncated.
whitequark [Tue, 10 Sep 2019 07:25:28 +0000 (07:25 +0000)]
hdl.ast: warn if reset value is truncated.

Fixes #183.

5 years agovendor.lattice_ecp5: pass ecppack_opts to ecppack.
Darrell Harmon [Tue, 10 Sep 2019 03:32:36 +0000 (21:32 -0600)]
vendor.lattice_ecp5: pass ecppack_opts to ecppack.

5 years agohdl.ast: check type of Sample(domain=...).
whitequark [Sun, 8 Sep 2019 23:55:05 +0000 (23:55 +0000)]
hdl.ast: check type of Sample(domain=...).

Fixes #199.

5 years agohdl.dsl: add Default(), an alias for Case() with no arguments.
whitequark [Sun, 8 Sep 2019 12:24:18 +0000 (12:24 +0000)]
hdl.dsl: add Default(), an alias for Case() with no arguments.

Fixes #197.

5 years agohdl.mem,lib,examples: use Signal.range().
whitequark [Sun, 8 Sep 2019 12:19:13 +0000 (12:19 +0000)]
hdl.mem,lib,examples: use Signal.range().

5 years agohdl.ast: add Signal.range(...), to replace Signal(min=..., max=...).
whitequark [Sun, 8 Sep 2019 12:10:31 +0000 (12:10 +0000)]
hdl.ast: add Signal.range(...), to replace Signal(min=..., max=...).

Fixes #196.

5 years agoRemove nmigen.lib from prelude.
whitequark [Fri, 6 Sep 2019 06:47:27 +0000 (06:47 +0000)]
Remove nmigen.lib from prelude.

Currently it's just MultiReg, and there's no particularly good reason
to privilege this specific CDC primitive so much.

5 years agoFix .gitignore.
whitequark [Fri, 6 Sep 2019 05:30:22 +0000 (05:30 +0000)]
Fix .gitignore.

5 years agosetup: replace versioneer with setuptools_scm.
whitequark [Fri, 6 Sep 2019 05:11:41 +0000 (05:11 +0000)]
setup: replace versioneer with setuptools_scm.

Has the same problems with git-archive but is much less invasive.

5 years agohdl.ast,back.rtlil: implement Cover.
whitequark [Tue, 3 Sep 2019 01:32:24 +0000 (01:32 +0000)]
hdl.ast,back.rtlil: implement Cover.

Fixes #194.

5 years agohdl.cd: add negedge clock domains.
whitequark [Sat, 31 Aug 2019 22:05:48 +0000 (22:05 +0000)]
hdl.cd: add negedge clock domains.

Fixes #185.

5 years ago_toolchain,build.plat,vendor.*: add required_tools list and checks.
Emily [Fri, 30 Aug 2019 23:27:22 +0000 (00:27 +0100)]
_toolchain,build.plat,vendor.*: add required_tools list and checks.

5 years agovendor.lattice_ecp5: drive GSR synchronous to user clock by default.
whitequark [Fri, 30 Aug 2019 10:10:13 +0000 (10:10 +0000)]
vendor.lattice_ecp5: drive GSR synchronous to user clock by default.

Fixes #167.

5 years agobuild.dsl: allow both str and int resource attributes.
whitequark [Fri, 30 Aug 2019 08:35:52 +0000 (08:35 +0000)]
build.dsl: allow both str and int resource attributes.

5 years agotest.tools: use _toolchain.get_tool.
Emily [Wed, 28 Aug 2019 11:52:16 +0000 (12:52 +0100)]
test.tools: use _toolchain.get_tool.

5 years ago_toolchain: new module, for injecting dependencies in e.g. Nix.
whitequark [Wed, 28 Aug 2019 11:32:18 +0000 (11:32 +0000)]
_toolchain: new module, for injecting dependencies in e.g. Nix.

5 years agoback.verilog: bump Yosys version requirement to 0.9.
whitequark [Mon, 26 Aug 2019 09:35:37 +0000 (09:35 +0000)]
back.verilog: bump Yosys version requirement to 0.9.

Fixes #55.

5 years agovendor.lattice_ecp5: revert default toolchain to Trellis.
whitequark [Sun, 25 Aug 2019 08:07:00 +0000 (08:07 +0000)]
vendor.lattice_ecp5: revert default toolchain to Trellis.

This was unintentionally changed in 7fc1058e.

5 years agoback.pysim: implement sim.add_clock(if_exists=True). locally_working
whitequark [Fri, 23 Aug 2019 08:53:48 +0000 (08:53 +0000)]
back.pysim: implement sim.add_clock(if_exists=True).

5 years agoback.pysim: don't crash when trying to drive a nonexistent domain clock.
whitequark [Fri, 23 Aug 2019 08:37:59 +0000 (08:37 +0000)]
back.pysim: don't crash when trying to drive a nonexistent domain clock.

5 years agobuild.run: add BuildPlan.digest(), useful for caching.
whitequark [Fri, 23 Aug 2019 01:10:51 +0000 (01:10 +0000)]
build.run: add BuildPlan.digest(), useful for caching.

5 years agovendor.lattice_ecp5: add Diamond support.
whitequark [Tue, 20 Aug 2019 12:27:19 +0000 (12:27 +0000)]
vendor.lattice_ecp5: add Diamond support.

5 years agovendor: eliminate unnecessary LUT instantiation.
whitequark [Thu, 22 Aug 2019 20:54:42 +0000 (20:54 +0000)]
vendor: eliminate unnecessary LUT instantiation.

Fixes #165.

5 years agoexamples/basic/uart: document `divisor` parameter.
Reto Kramer [Thu, 22 Aug 2019 19:28:40 +0000 (12:28 -0700)]
examples/basic/uart: document `divisor` parameter.

5 years agoback.rtlil: print real parameters with maximum precision.
whitequark [Thu, 22 Aug 2019 04:42:30 +0000 (04:42 +0000)]
back.rtlil: print real parameters with maximum precision.

5 years agoback.rtlil: add support for real (float) parameters on Instances.
Darrell Harmon [Thu, 22 Aug 2019 04:13:05 +0000 (22:13 -0600)]
back.rtlil: add support for real (float) parameters on Instances.

Required for Xilinx MMCME2_BASE, etc.

5 years agovendor.xilinx_series7: use STARTUPE2, not STARTUPE3.
Darrell Harmon [Wed, 21 Aug 2019 22:25:55 +0000 (16:25 -0600)]
vendor.xilinx_series7: use STARTUPE2, not STARTUPE3.

STARTUPE3 is for Ultrascale.

5 years agovendor.lattice_ice40: remove `--placer heap` default option.
whitequark [Wed, 21 Aug 2019 21:32:12 +0000 (21:32 +0000)]
vendor.lattice_ice40: remove `--placer heap` default option.

It is not the place of nMigen to decide on this default, since both
SA and HeAP have valid uses that are not covered by the other.

5 years agovendor: style. NFC.
whitequark [Wed, 21 Aug 2019 21:31:19 +0000 (21:31 +0000)]
vendor: style. NFC.

5 years agobuild.plat: remove TemplatedPlatform.unix_interpreter.
whitequark [Wed, 21 Aug 2019 21:02:05 +0000 (21:02 +0000)]
build.plat: remove TemplatedPlatform.unix_interpreter.

Vendor toolchains generally require far more workarounds than this,
and we already have a perfectly fine way of overriding templates.

5 years agoback.pysim: allow coroutines as processes.
whitequark [Wed, 21 Aug 2019 03:28:48 +0000 (03:28 +0000)]
back.pysim: allow coroutines as processes.

This is a somewhat obscure use case, but it is possible to use async
functions with pysim by carefully using @asyncio.coroutine. That is,
async functions can call back into pysim if they are declared in
a specific way:

  @asyncio.coroutine
  def do_something(self, value):
    yield self.reg.eq(value)

which may then be called from elsewhere with:

  async def test_case(self):
    await do_something(0x1234)

This approach is unfortunately limited in that async functions
cannot yield directly. It should likely be improved by using async
generators, but supporting coroutines in pysim is unobtrustive and
allows existing code that made use of this feature in oMigen to work.

5 years agotest.test_examples: Convert pathlib-specific class to string.
William D. Jones [Mon, 5 Aug 2019 01:52:23 +0000 (21:52 -0400)]
test.test_examples: Convert pathlib-specific class to string.

subprocess.check_call iterates over its arguments to check for spaces
and tabs, and on Windows, the pathlib-specific WindowsPath is not
iterable.

5 years agoback.verilog: parse output of `yosys -V`.
whitequark [Mon, 19 Aug 2019 23:28:33 +0000 (23:28 +0000)]
back.verilog: parse output of `yosys -V`.

See #55.

5 years agoFix nmigen.__version__ to work on git-archive artifacts.
whitequark [Mon, 19 Aug 2019 23:14:41 +0000 (23:14 +0000)]
Fix nmigen.__version__ to work on git-archive artifacts.

Fixes #137.

5 years agobuild.plat, hdl.ir: coordinate missing domain creation.
whitequark [Mon, 19 Aug 2019 22:32:50 +0000 (22:32 +0000)]
build.plat, hdl.ir: coordinate missing domain creation.

Platform.prepare() was completely broken after addition of local
clock domains, and only really worked before by a series of
accidents because there was a circular dependency between creation
of missing domains, fragment preparation, and insertion of pin
subfragments.

This commit untangles the dependency by adding a separate public
method Fragment.create_missing_domains(), used in build.plat.

It also makes DomainCollector consider both used and defined domains,
such that it will work on fragments before domain propagation, since
create_missing_domains() can be called by user code before prepare().

The fragment driving missing clock domain is not flattened anymore,
because flattening does not work well combined with local domains.

5 years agovendor.lattice_ice40: use a local clock domain in create_missing_domain().
whitequark [Mon, 19 Aug 2019 21:46:44 +0000 (21:46 +0000)]
vendor.lattice_ice40: use a local clock domain in create_missing_domain().

5 years agolib.cdc: use a local clock domain in ResetSynchronizer.
whitequark [Mon, 19 Aug 2019 20:47:40 +0000 (20:47 +0000)]
lib.cdc: use a local clock domain in ResetSynchronizer.

This reverts commit 779f3ee906190b92e5a07e5adcd62b20213bb936.
This reverts commit 300d47ca2ebbabb31d2f191acf80c9b89659c4f0.
This reverts commit 9c54d0c061884317d1558de9f9be52d1ec8dea68.

5 years agoREADME: fix typos.
whitequark [Mon, 19 Aug 2019 21:44:23 +0000 (21:44 +0000)]
README: fix typos.

5 years agohdl.cd: implement local clock domains.
whitequark [Mon, 19 Aug 2019 20:46:46 +0000 (20:46 +0000)]
hdl.cd: implement local clock domains.

Closes #175.

5 years agoback.pysim: index domains by identity, not by name.
whitequark [Mon, 19 Aug 2019 21:29:53 +0000 (21:29 +0000)]
back.pysim: index domains by identity, not by name.

Changed in preparation for introducing local clock domains.

5 years agohdl.xfrm: lower resets in DomainLowerer as well.
whitequark [Mon, 19 Aug 2019 21:32:48 +0000 (21:32 +0000)]
hdl.xfrm: lower resets in DomainLowerer as well.

Changed in preparation for introducing local clock domains.

Also makes elaboration about 15% faster.

5 years agohdl.xfrm: consider fragment's own domains in DomainLowerer.
whitequark [Mon, 19 Aug 2019 21:06:54 +0000 (21:06 +0000)]
hdl.xfrm: consider fragment's own domains in DomainLowerer.

Changed in preparation for introducing local clock domains.

5 years agoformal→asserts
whitequark [Mon, 19 Aug 2019 20:23:24 +0000 (20:23 +0000)]
formal→asserts

Closes #171.

5 years agotracer: fix typo.
whitequark [Mon, 19 Aug 2019 20:20:18 +0000 (20:20 +0000)]
tracer: fix typo.

Introduced in 62b3e366.

5 years agobuild.plat: do not prepare fragments twice.
whitequark [Mon, 19 Aug 2019 19:29:47 +0000 (19:29 +0000)]
build.plat: do not prepare fragments twice.

Fixes #169.

5 years agoback.{rtlil,verilog}: split convert_fragment() off convert().
whitequark [Mon, 19 Aug 2019 19:27:02 +0000 (19:27 +0000)]
back.{rtlil,verilog}: split convert_fragment() off convert().

Because Fragment.prepare is not (currently) idempotent, it is useful
to be able to avoid calling it when converting. Even if it is made
idempotent, it can be slow on large designs, so it is advantageous
regardless of that.

5 years agobuild.dsl: add conn argument to Connector.
Robin Heinemann [Sun, 18 Aug 2019 19:56:25 +0000 (21:56 +0200)]
build.dsl: add conn argument to Connector.

5 years agocompat.fhdl.decorators: avoid using deprecated NativeCEInserter.
whitequark [Sun, 18 Aug 2019 16:27:11 +0000 (16:27 +0000)]
compat.fhdl.decorators: avoid using deprecated NativeCEInserter.

5 years agohdl.xfrm: make deprecated CEInserter more well-behaved.
whitequark [Sun, 18 Aug 2019 16:26:45 +0000 (16:26 +0000)]
hdl.xfrm: make deprecated CEInserter more well-behaved.

5 years agohdl.ast: implement Initial.
whitequark [Thu, 15 Aug 2019 02:53:07 +0000 (02:53 +0000)]
hdl.ast: implement Initial.

This is the last remaining part for first-class formal support.

5 years agohdl.xfrm: sample cache should be per-fragment.
whitequark [Thu, 15 Aug 2019 02:42:14 +0000 (02:42 +0000)]
hdl.xfrm: sample cache should be per-fragment.

5 years agohdl.xfrm: CEInserter→EnableInserter.
whitequark [Mon, 12 Aug 2019 13:37:18 +0000 (13:37 +0000)]
hdl.xfrm: CEInserter→EnableInserter.

Fixes #166.

5 years agohdl.ast: hash-cons ValueKey.
whitequark [Thu, 8 Aug 2019 10:56:23 +0000 (10:56 +0000)]
hdl.ast: hash-cons ValueKey.

This speeds up elaboration by ~10%.

5 years agotracer: use sys._getframe directly.
whitequark [Thu, 8 Aug 2019 10:23:35 +0000 (10:23 +0000)]
tracer: use sys._getframe directly.

This speeds up elaboration by ~30-40%.

5 years agocompat.fhdl.decorators: port from oMigen.
whitequark [Thu, 8 Aug 2019 08:09:28 +0000 (08:09 +0000)]
compat.fhdl.decorators: port from oMigen.

5 years agocompat.fhdl.module: fix finalization of transformed compat submodules.
whitequark [Thu, 8 Aug 2019 07:45:34 +0000 (07:45 +0000)]
compat.fhdl.module: fix finalization of transformed compat submodules.

Before this commit, the TransformedElaboratable of a CompatModule
would be ignored, and .get_fragment() would be used to retrieve
the CompatModule within.

After this commit, the finalization process is reworked to match
oMigen's finalization closely, and all submodules, native and compat,
are added in the same way that preserves applied transforms.

5 years agovendor.lattice_ice40: add iCE5LP2K support.
whitequark [Wed, 7 Aug 2019 09:25:20 +0000 (09:25 +0000)]
vendor.lattice_ice40: add iCE5LP2K support.

5 years agovendor.lattice_ice40: add iCE40UP3K support.
whitequark [Wed, 7 Aug 2019 09:06:27 +0000 (09:06 +0000)]
vendor.lattice_ice40: add iCE40UP3K support.

5 years agovendor.lattice_ice40: add iCE5LP1K support.
whitequark [Wed, 7 Aug 2019 09:00:41 +0000 (09:00 +0000)]
vendor.lattice_ice40: add iCE5LP1K support.

5 years agovendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic.
whitequark [Sun, 4 Aug 2019 23:27:47 +0000 (23:27 +0000)]
vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic.

On Xilinx devices, flip-flops are reset to their initial state with
an internal global reset network, but this network is deasserted
asynchronously to user clocks. Use BUFGCE and STARTUP to hold default
clock low until after GWE is deasserted.

5 years agovendor.xilinx_spartan_3_6: reconsider bitgen defaults.
whitequark [Sun, 4 Aug 2019 23:23:06 +0000 (23:23 +0000)]
vendor.xilinx_spartan_3_6: reconsider bitgen defaults.

Previously changed in 27063a3b.

I haven't realized the .bin file is the same as the .bit file without
a small header. That means generating it is free and it's just easier
to let programming tools to be able to always rely on its existence.

5 years agovendor.xilinx_spartan_3_6: set bitgen defaults to `-g Binary:Yes -g Compress`.
whitequark [Sun, 4 Aug 2019 14:16:02 +0000 (14:16 +0000)]
vendor.xilinx_spartan_3_6: set bitgen defaults to `-g Binary:Yes -g Compress`.

  * `-g Binary:Yes` should be overridable.
  * `-g Compress` is a good default.

5 years agovendor.xilinx_spartan_3_6: always use -w for map/par/bitgen.
whitequark [Sun, 4 Aug 2019 14:12:02 +0000 (14:12 +0000)]
vendor.xilinx_spartan_3_6: always use -w for map/par/bitgen.

-w stands for "override output file", and supplying user options
should not remove it.

5 years agovendor.xilinx_spartan_3_6: do not use retiming by default.
whitequark [Sun, 4 Aug 2019 13:48:33 +0000 (13:48 +0000)]
vendor.xilinx_spartan_3_6: do not use retiming by default.

This was added in b404d603, probably by mistake, and is certainly
wrong given that we do not (yet) correctly mark CDC FFs.

5 years agovendor.xilinx_spartan_3_6: force use of bash on UNIX.
whitequark [Sun, 4 Aug 2019 13:19:50 +0000 (13:19 +0000)]
vendor.xilinx_spartan_3_6: force use of bash on UNIX.

5 years agobuild.plat: allow selecting a specific UNIX shell interpreter.
whitequark [Sun, 4 Aug 2019 13:18:29 +0000 (13:18 +0000)]
build.plat: allow selecting a specific UNIX shell interpreter.

Mostly because vendor tools have bashisms.

5 years agovendor.lattice_ice40: avoid routing conflicts with SDR/DDR input pins.
whitequark [Sun, 4 Aug 2019 00:30:50 +0000 (00:30 +0000)]
vendor.lattice_ice40: avoid routing conflicts with SDR/DDR input pins.

5 years agoback.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS.
whitequark [Sat, 3 Aug 2019 23:57:50 +0000 (23:57 +0000)]
back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS.

Using 'x is legal RTLIL, in theory, but in practice it crashes Yosys
and when it doesn't, it causes Yosys to produce invalid Verilog.
Using a dummy wire is always safe and is not a major readability
issue as this is a rare corner case.

(It is not trivial to shorten the RHS in this case, because during
expansion of an ArrayProxy, match_shape() could be called in
a context far from the RHS handling logic.)

5 years agoback.rtlil: actually match shape of left hand side.
whitequark [Sat, 3 Aug 2019 23:43:57 +0000 (23:43 +0000)]
back.rtlil: actually match shape of left hand side.

This comes up in code such as:
  Array([Signal(1), Signal(8)]).eq(Const(0, 8))

5 years agovendor.lattice_ice40: add missing signal indexing.
whitequark [Sat, 3 Aug 2019 22:59:33 +0000 (22:59 +0000)]
vendor.lattice_ice40: add missing signal indexing.

5 years agobuild.run: use keyword-only arguments where appropriate.
whitequark [Sat, 3 Aug 2019 22:52:58 +0000 (22:52 +0000)]
build.run: use keyword-only arguments where appropriate.

5 years agocompat.fhdl.specials: track changes in build.plat.
whitequark [Sat, 3 Aug 2019 22:52:34 +0000 (22:52 +0000)]
compat.fhdl.specials: track changes in build.plat.

5 years agohdl.dsl: reword m.If(~True) warning to be more clear.
whitequark [Sat, 3 Aug 2019 18:52:24 +0000 (18:52 +0000)]
hdl.dsl: reword m.If(~True) warning to be more clear.

Before this commit, it only suggested one thing (silencing it) and
that's wrong almost all of the time, so suggest the right thing
instead.

5 years agobuild.plat,vendor: automatically create sync domain from default_clk.
whitequark [Sat, 3 Aug 2019 18:36:58 +0000 (18:36 +0000)]
build.plat,vendor: automatically create sync domain from default_clk.

But only if it is not defined by the programmer.

Closes #57.

5 years agohdl.ir: allow adding more than one domain in missing domain callback.
whitequark [Sat, 3 Aug 2019 18:19:40 +0000 (18:19 +0000)]
hdl.ir: allow adding more than one domain in missing domain callback.

This is useful for injecting complex power-on reset logic.

5 years agohdl.ir: don't expose as ports missing domains added via elaboratables.
whitequark [Sat, 3 Aug 2019 16:39:21 +0000 (16:39 +0000)]
hdl.ir: don't expose as ports missing domains added via elaboratables.

The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.

5 years agobuild.plat: add default_rst, to be used with default_clk.
whitequark [Sat, 3 Aug 2019 16:28:03 +0000 (16:28 +0000)]
build.plat: add default_rst, to be used with default_clk.

5 years agobuild.plat: add default_clk{,_constraint,_frequency}.
whitequark [Sat, 3 Aug 2019 16:18:46 +0000 (16:18 +0000)]
build.plat: add default_clk{,_constraint,_frequency}.

This is the equivalent of oMigen's default_clk and default_clk_period
except the period is taken from the resource.

5 years agohdl.ir: allow returning elaboratables from missing domain callback.
whitequark [Sat, 3 Aug 2019 15:44:02 +0000 (15:44 +0000)]
hdl.ir: allow returning elaboratables from missing domain callback.

This allows e.g. injecting a clock/reset generator in platform build
code on demand (i.e. if the domain is not instantiated manually).

See #57.

5 years agohdl.ir: raise DomainError if a domain is used but not defined.
whitequark [Sat, 3 Aug 2019 15:31:00 +0000 (15:31 +0000)]
hdl.ir: raise DomainError if a domain is used but not defined.

Before this commit, a KeyError would be raised elsewhere in guts of
hdl.ir, which is not helpful.

5 years agohdl.ir: call back from Fragment.prepare if a clock domain is missing.
whitequark [Sat, 3 Aug 2019 14:54:20 +0000 (14:54 +0000)]
hdl.ir: call back from Fragment.prepare if a clock domain is missing.

See #57.