gem5.git
6 years agobase: Fix unused function warning
Nikos Nikoleris [Thu, 1 Feb 2018 17:57:48 +0000 (17:57 +0000)]
base: Fix unused function warning

After refactoring the remote gdb interface, break_type is declared as
const function and is only used as a parameter to DPRINTF function
calls. This means that it is seen as unused when compiling
gem5.fast. This changeset fixes the warning.

Change-Id: Iea89b66c53c62341c043d8bd3838ebc27ee333bc
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7741
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agoalpha: fix for no 'break' in the case statement
Sujay Phadke [Tue, 23 Jan 2018 17:54:12 +0000 (23:24 +0530)]
alpha: fix for no 'break' in the case statement

gem5 won't compile correctly since g++ will throw a warning (error)
that the next case statement below this one is reachable since there is
no 'break' statement.

Signed-off-by: Sujay Phadke
Change-Id: Icab646ee5abcfeb6ba3e690909042927b4003eba
Reviewed-on: https://gem5-review.googlesource.com/7521
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agoscons: Resolve backtrace implementation existence testing failure
Hanhwi Jang [Tue, 30 Jan 2018 10:17:33 +0000 (19:17 +0900)]
scons: Resolve backtrace implementation existence testing failure

Change backtrace implementation testing code not to have NULL pointer.

SCons fails to find backtrace implementation even if it exists.
The implementation testing code contains NULL pointers as a backtrace
buffer argument. Some compilers check the buffer is NULL pointed
or not, and generate a compilation error.

Change-Id: Icc5bc9a887b7a6bbc804b5b8a5a35a935c78a922
Reviewed-on: https://gem5-review.googlesource.com/7681
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarch-x86: consistent style of comments in system files
Christian Menard [Tue, 30 Jan 2018 10:12:31 +0000 (11:12 +0100)]
arch-x86: consistent style of comments in system files

Change-Id: I9f208819b8c1a5c46a77262eb533bb47adb2b905
Reviewed-on: https://gem5-review.googlesource.com/7701
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarch-x86: Granularity bit and segment limit
Maximilian Stein [Mon, 29 Jan 2018 11:21:32 +0000 (12:21 +0100)]
arch-x86: Granularity bit and segment limit

If set, the granularity bit indicates that the segment limit of segment
descriptors shall be interpreted as number of 4K blocks rather than
bytes.

The high part (bit 48 to 51) of segment descriptor limits is only 4 bits
wide while the low part (bit 0 to 15) spans 16 bits.

Change-Id: Ie386224ca815275fdb31498fe68310ed9c62cc87
Reviewed-on: https://gem5-review.googlesource.com/7601
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoriscv: Add overrides to various StaticInst methods.
Gabe Black [Mon, 29 Jan 2018 23:17:08 +0000 (15:17 -0800)]
riscv: Add overrides to various StaticInst methods.

This makes riscv compile with the version of clang(++) I have on my
workstation.

Change-Id: I0478616810fbc8a715fd61323b7e0f73676c8328
Reviewed-on: https://gem5-review.googlesource.com/7643
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase: Remove the ability to cprintf stringstreams directly.
Gabe Black [Mon, 29 Jan 2018 22:42:26 +0000 (14:42 -0800)]
base: Remove the ability to cprintf stringstreams directly.

The cprintf functions don't know ahead of time what format characters
are going to be used with what underlying data types, and so any
type must be minimally usable with the default specialization of
format_integer, format_char, format_float and format_string. All of
those functions ultimately print their parameter with out << data
except the one which prints stringstreams. That function accesses the
buffer of the string stream with .str(), and then prints that instead.

That should technically work out ok as long as stringstreams are only
printed using %s, but there's no way to guarantee that ahead of time.
To avoid that problem, and because gem5 doesn't ever actually use the
ability to print stringstreams directly, this change removes that
feature and modifies the corresponding part of the unit test.

If we ever do want to print the contents of a string stream, it won't
be difficult to add a .str() to it.

Change-Id: Id902eaff042b96b374efe0183e5e3be9626e8c88
Reviewed-on: https://gem5-review.googlesource.com/7642
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase: Delete commented out versions of the format_integer function.
Gabe Black [Mon, 29 Jan 2018 22:38:37 +0000 (14:38 -0800)]
base: Delete commented out versions of the format_integer function.

If they're needed, they'd be fairly easy to recreate and are also
available in the revision history.

Change-Id: I5cf5e4b1271ce488016464048de69bc643dee4d9
Reviewed-on: https://gem5-review.googlesource.com/7641
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarch-arm: understandably initialize register permissions
Curtis Dunham [Wed, 6 Dec 2017 22:51:26 +0000 (16:51 -0600)]
arch-arm: understandably initialize register permissions

Move massive initialization routine to the bottom of miscregs.cc.
Additionally, share register metadata across ISA instances by
making lookUpMiscReg a static member of the ISA and only
initializing it once.

Change-Id: I6d6ab26200c4e781151cc6efd97ce2420e2bf4cc
Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6803
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarm: extend MiscReg metadata structures
Curtis Dunham [Fri, 3 Nov 2017 22:39:45 +0000 (17:39 -0500)]
arm: extend MiscReg metadata structures

Implement proper handling of RES0/RES1 and RAZ/RAO bitfields.

Change-Id: I344c32c3fb1d142acfb0521ba3590ddd2b1f5360
Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6802
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarch-arm: understandably initialize register mappings
Curtis Dunham [Wed, 6 Dec 2017 20:42:07 +0000 (14:42 -0600)]
arch-arm: understandably initialize register mappings

The mappings for sharing a backing store between AArch32
and AArch64 system registers are made clearer using an
initializer object.

Change-Id: I29dcfab2797b4d36b3182342997edffde334a291
Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6801
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoconfig, arm: enable device tree autogeneration for bigLITTLE
Curtis Dunham [Mon, 11 Sep 2017 20:17:00 +0000 (15:17 -0500)]
config, arm: enable device tree autogeneration for bigLITTLE

Change-Id: Iaa5eeb3504b3ff9e46b6f592a06d6b833c830d83
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5969
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoconfig: Embed Device Tree generation in fs.py config
Glenn Bergmans [Mon, 14 Mar 2016 20:29:12 +0000 (20:29 +0000)]
config: Embed Device Tree generation in fs.py config

Equips the fs.py config routine with an extra commandline option
--generate-dtb that will generate a dtb file automatically before
running the simulation. Only works with ARM systems and gives a warning
if the simulated system is not of --machine-type VExpress_GEM5_V1.

Change-Id: I7766e5459fd9bec2245de83cef103091ebaf7229
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5968
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarm: DT autogeneration - generate PCI node
Glenn Bergmans [Fri, 22 Jan 2016 15:40:14 +0000 (15:40 +0000)]
arm: DT autogeneration - generate PCI node

Enables automatic generation of Device Trees for RealView PCI host
controllers. Note that some parts are more hard coded than you'd want,
but this is due to the limited understanding the PCI host has of its
configuration (i.e. it doesn't know all memory ranges). Fixing this,
for now at least, went beyond the scope and intentions of the
Device Tree generating code: use with care!

Change-Id: I2041871e0eb4d04fb5191257c47dd38649d1c0cc
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5967
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarm: DT autogeneration - Generate energy controller node
Glenn Bergmans [Fri, 22 Jan 2016 15:40:14 +0000 (15:40 +0000)]
arm: DT autogeneration - Generate energy controller node

Adds Device Tree methods for the energy controller to allow for
DVFS simulations with automatically generated DTB files

Change-Id: Id8682f07dff1bbe63987e757faa0694e03ee86ab
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5966
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarm: DT autogeneration - autogenerate RealView Platform devices
Glenn Bergmans [Thu, 17 Dec 2015 11:49:51 +0000 (11:49 +0000)]
arm: DT autogeneration - autogenerate RealView Platform devices

Implements the Device Tree generating code for devices required by the
RealView VExpress_GEM5_V1 platform

Change-Id: I14244b2f3c028cbddba3c23ce7433fe3b301a0e8
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5965
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarm: DT autogeneration - Generate memory node
Glenn Bergmans [Fri, 22 Jan 2016 15:25:40 +0000 (15:25 +0000)]
arm: DT autogeneration - Generate memory node

Implements a high level method for generating a Device Tree node for
an AbstractMemory object.

Change-Id: I544ec642f182f103df26de535fdfaf03b3787a08
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5964
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarm: DT autogeneration - Generate cpus node
Glenn Bergmans [Fri, 22 Jan 2016 15:23:03 +0000 (15:23 +0000)]
arm: DT autogeneration - Generate cpus node

Equips cpu models with a method to generate the cpu node.

Note: even though official documentation requires that CPU ids start
counting from 0 in every cluster, GEM5 requires a globally unique cpu_id.

Change-Id: Ida3e17af3124a68ef7dbf2449cd034dfc3ec39df
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5963
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarm: DT autogeneration - Device Tree generation methods
Glenn Bergmans [Wed, 16 Dec 2015 15:43:42 +0000 (15:43 +0000)]
arm: DT autogeneration - Device Tree generation methods

This patch adds an extra layer to the pyfdt library such that usage
gets easier and device tree nodes can be specified in less code,
without limiting original usage. Note to not import both the pyfdt
and fdthelper in the same namespace (but generally fdthelper is all
you need, because it supplies the same classes even when they are not
extended in any way)

Also, this patch lays out the primary functionality for generating a
device tree, where every SimObject gets an empty generateDeviceTree
method and ArmSystems loop over their children in an effort to merge
all the nodes. Devices are implemented in other patches.

Change-Id: I4d0a0666827287fe42e18447f19acab4dc80cc49
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5962
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoext: DT autogeneration - Add PyFtd to m5 space
Glenn Bergmans [Wed, 16 Dec 2015 15:43:42 +0000 (15:43 +0000)]
ext: DT autogeneration - Add PyFtd to m5 space

This patch adds pyfdt.py to the m5.ext module. This is used in
succeeding patches for generating and editing dtb files and flat
device trees for DT autogeneration.

The file is in the m5_root/src/python/m5/ext directory, as opposed to
the m5_root/ext, because this library is part of the m5 object space
and linking to the m5_root/ext directory from the SConscript file
in src/python can not be done reliably. Linking from the root level
SConscript is also not an option, because it doesn't have the PySource
method defined.

Cloned from: https://github.com/superna9999/pyfdt
Commit: accbcd254584c9295a18878d32999d0c7c156f8e
Version: 0.3

Change-Id: I928bdc912a9507d1f8a3290acf445c7cae496552
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5961
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarm: make Arm GenericTimer a ClockedObject
Curtis Dunham [Thu, 7 Sep 2017 21:13:54 +0000 (16:13 -0500)]
arm: make Arm GenericTimer a ClockedObject

Within a device tree, the GenericTimer device needs to point (via phandle)
to a clock domain which is itself also an object in the device tree. Within
gem5, clock domains are managed by making all clocked SimObjects inherit
from ClockedObject rather than SimObject.

Without this change, the GenericTimer is unable to generate the appropriate
clock domain phandle, and will crash during DTB autogeneration.

Change-Id: I6d3fb6362847c6a01720b2f14b3d595d1e59f01f
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4960
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agobase: Add an "override" to name() in the HardBreakpoint class.
Gabe Black [Sat, 27 Jan 2018 11:18:15 +0000 (03:18 -0800)]
base: Add an "override" to name() in the HardBreakpoint class.

clang reports an error otherwise and fails to compile.

Change-Id: I3603d6c710641f1289e35c67f89a49f5cb71e95e
Reviewed-on: https://gem5-review.googlesource.com/7582
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agobase: Get bitunions to compile on clang 3.8.
Gabe Black [Sat, 27 Jan 2018 11:15:13 +0000 (03:15 -0800)]
base: Get bitunions to compile on clang 3.8.

clang was getting very upset and interpretting a member function
pointer as a call to the actual underlying function, and then
complaining that it was a non-static function call without an instance.

It seems what it was really upset about was that the class who's scope
the member function pointer belonged to (the current class) wasn't done
being defined. This *should* be ok as far as I can tell, but clang was
having none of it.

This change reworks how the type of the setter function arguments are
determined to work around that limitation. The bitunion test was run
with clang++ and g++ and both pass, and I've built gem5.opt for ARM
successfully.

Change-Id: Ib9351784a897af4867fe08045577e0247334ea11
Reviewed-on: https://gem5-review.googlesource.com/7581
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoutil: Implement Lua module for m5ops.
Hanhwi Jang [Sat, 9 Dec 2017 17:02:34 +0000 (02:02 +0900)]
util: Implement Lua module for m5ops.

This module allows m5ops to be executed in Lua programs.
To compile it (in util/m5):
    The following command generates Lua moduel, gem5OpLua.so.

    make -f Makefile.<arch> gem5OpLua.so

To use it:
    First, put gem5OpLua.so in Lua library search path.
    Then, import the module and execute the m5op function.

Example usage, creating a checkpoint.

    m5 = require("gem5OpLua")
    m5.do_checkpoint(0, 0)

Change-Id: Icc18a1fb6c050afeb1cf4558fbdc724fb26a90e2
Reviewed-on: https://gem5-review.googlesource.com/6541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarch-x86: Adding clflush, clflushopt, clwb instructions
Swapnil Haria [Tue, 16 Jan 2018 03:49:17 +0000 (21:49 -0600)]
arch-x86: Adding clflush, clflushopt, clwb instructions

This patch adds support for cache flushing instructions in x86.
It piggybacks on support for similar instructions in arm ISA
added by Nikos Nikoleris. I have tested each instruction using
microbenchmarks.

Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d
Reviewed-on: https://gem5-review.googlesource.com/7401
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarch: Remove the "arch/tlb.hh" switching header.
Gabe Black [Tue, 9 Jan 2018 07:44:40 +0000 (23:44 -0800)]
arch: Remove the "arch/tlb.hh" switching header.

This header is no longer used.

Change-Id: I8da7f8618d647dd11c581818c13855c4e20d32d2
Reviewed-on: https://gem5-review.googlesource.com/7351
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agotarch, mem: Abstract the data stored in the SE page tables.
Gabe Black [Tue, 9 Jan 2018 07:37:57 +0000 (23:37 -0800)]
tarch, mem: Abstract the data stored in the SE page tables.

Rather than store the actual TLB entry that corresponds to a mapping,
we can just store some abstracted information (address, a few flags)
and then let the caller turn that into the appropriate entry. There
could potentially be some small amount of overhead from creating
entries vs. storing them and just installing them, but it's likely
pretty minimal since that only happens on a TLB miss (ideally rare),
and, if it is problematic, there could be some preallocated TLB
entries which are just minimally filled in as necessary.

This has the nice effect of finally making the page tables ISA
agnostic.

Change-Id: I11e630f60682f0a0029b0683eb8ff0135fbd4317
Reviewed-on: https://gem5-review.googlesource.com/7350
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agox86, mem: Rewrite the multilevel page table class.
Gabe Black [Mon, 8 Jan 2018 12:41:25 +0000 (04:41 -0800)]
x86, mem: Rewrite the multilevel page table class.

The new version extracts all the x86 specific aspects of the class,
and builds the interface around a variable collection of template
arguments which are classes that represent the different levels of the
page table. The multilevel page table class is now much more ISA
independent.

Change-Id: Id42e168a78d0e70f80ab2438480cb6e00a3aa636
Reviewed-on: https://gem5-review.googlesource.com/7347
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoutil: Implement PIC version of m5ops for X86.
Hanhwi Jang [Wed, 10 Jan 2018 02:39:38 +0000 (11:39 +0900)]
util: Implement PIC version of m5ops for X86.

Using m5ops for X86 in shared objects requires PIC for the m5ops.
Typically, the PIC version is used to make m5op interfaces to other
languages like python and lua.

Change-Id: I2463904c13ea8b839d0386d3c743d8dad1e1e6bc
Reviewed-on: https://gem5-review.googlesource.com/7261
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agox86, mem: Don't try to force physical addresses on the system.
Gabe Black [Mon, 8 Jan 2018 05:32:39 +0000 (21:32 -0800)]
x86, mem: Don't try to force physical addresses on the system.

Use the system object to allocate physical memory instead of manually
placing certain structures and then forcing the system to start other
allocations after them in physical memory.

Change-Id: Ie18c81645c3b648c64a6d7a649a0e50f7028f344
Reviewed-on: https://gem5-review.googlesource.com/7346
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
6 years agox86, mem: Get rid of PageTableOps::getBasePtr.
Gabe Black [Sat, 6 Jan 2018 07:52:29 +0000 (23:52 -0800)]
x86, mem: Get rid of PageTableOps::getBasePtr.

Pass this constant into the page table constructor.

Change-Id: Icbf730f18d9dfcfebd10a196f7f799514728b0fb
Reviewed-on: https://gem5-review.googlesource.com/7345
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
6 years agox86, mem: Pass the multi level page table layout in as a parameter.
Gabe Black [Sat, 6 Jan 2018 01:48:40 +0000 (17:48 -0800)]
x86, mem: Pass the multi level page table layout in as a parameter.

Don't get it from a global constant declared in an ISA header file.

Change-Id: Ie19440abdd76500a5e12e6791e6f755ad9e95af3
Reviewed-on: https://gem5-review.googlesource.com/7344
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
6 years agoarch, mem: Make the page table lookup function return a pointer.
Gabe Black [Fri, 5 Jan 2018 23:01:00 +0000 (15:01 -0800)]
arch, mem: Make the page table lookup function return a pointer.

This avoids having a copy in the lookup function itself, and the
declaration of a lot of temporary TLB entry pointers in callers. The
gpu TLB seems to have had the most dependence on the original signature
of the lookup function, partially because it was relying on a somewhat
unsafe copy to a TLB entry using a base class pointer type.

Change-Id: I8b1cf494468163deee000002d243541657faf57f
Reviewed-on: https://gem5-review.googlesource.com/7343
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase: Hide the BitUnion::__StorageType type.
Gabe Black [Mon, 8 Jan 2018 03:56:25 +0000 (19:56 -0800)]
base: Hide the BitUnion::__StorageType type.

Since this type is now accessible through a clean interface, hide it
from anybody that tries to peak around the curtain.

Change-Id: I1257b6675a45b8648be459ad8e8d0f27a6feee6b
Reviewed-on: https://gem5-review.googlesource.com/7205
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarm, base: Generalize and move the BitUnion hash struct.
Gabe Black [Mon, 8 Jan 2018 03:44:55 +0000 (19:44 -0800)]
arm, base: Generalize and move the BitUnion hash struct.

The ARM types.hh file defined an STL style hash structure to operate
on the ExtMachInst, but it referred to the underlying storage type
using internal typedefs in the BitUnion types. To avoid having to do
that, this change adds a hash structure to bitunion.hh which will work
on any BitUnion, and gets rid of the ARM ExtMachInst version.

Change-Id: I7c1c84d61b59061fec98abaaeab6becd06537dee
Reviewed-on: https://gem5-review.googlesource.com/7204
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosim: Use the new BitUnion templates in serialize.hh.
Gabe Black [Mon, 8 Jan 2018 03:35:40 +0000 (19:35 -0800)]
sim: Use the new BitUnion templates in serialize.hh.

serialize.hh should not reference internal implementation details in
the underlying BitUnion types.

Change-Id: I1ce29243db63801b7788f037fdc54811bdab889c
Reviewed-on: https://gem5-review.googlesource.com/7203
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
6 years agobase: Enable specializing templates on BitUnion types.
Gabe Black [Mon, 8 Jan 2018 02:38:04 +0000 (18:38 -0800)]
base: Enable specializing templates on BitUnion types.

Previously these relied on reaching into private internal definitions
in the BitUnion types.

Change-Id: Ia6c94de92986b85ec9e5fcb197459d450111fb36
Reviewed-on: https://gem5-review.googlesource.com/7202
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase: Rework bitunions so they can be more flexible.
Gabe Black [Sat, 6 Jan 2018 13:30:46 +0000 (05:30 -0800)]
base: Rework bitunions so they can be more flexible.

They are now oriented around a class which makes it easy to provide
custom setter/getter functions which let you set or read bits in an
arbitrary way.

Future additions may add the ability to add custom bitfield methods,
and index-able bitfields.

Change-Id: Ibd6d4d9e49107490f6dad30a4379a8c93bda9333
Reviewed-on: https://gem5-review.googlesource.com/7201
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosim, arch, base: Refactor the base remote GDB class.
Gabe Black [Tue, 16 Jan 2018 09:25:39 +0000 (01:25 -0800)]
sim, arch, base: Refactor the base remote GDB class.

Fold the GDBListener class into the main BaseRemoteGDB class, move
around a bunch of functions, convert a lot of internal functions to
be private, move some functions into the .cc, make some functions
non-virtual which didn't really need to be overridden.

Change-Id: Id0832b730b0fdfb2eababa5067e72c66de1c147d
Reviewed-on: https://gem5-review.googlesource.com/7422
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarch, mem, sim: Consolidate and rename the SE mode page table classes.
Gabe Black [Thu, 4 Jan 2018 09:22:49 +0000 (01:22 -0800)]
arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoutil: Add an option to specify paths in list_changes.py
Andreas Sandberg [Wed, 17 Jan 2018 18:06:05 +0000 (18:06 +0000)]
util: Add an option to specify paths in list_changes.py

Add an option to restrict change lists to changes that touch one or
more subdirectories in the source tree.

Change-Id: Id4e34fe300fdc3657505e2e188c727e583bcf611
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7461
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
6 years agomem: Change the multilevel page table to inherit from FuncPageTable.
Gabe Black [Thu, 4 Jan 2018 08:30:38 +0000 (00:30 -0800)]
mem: Change the multilevel page table to inherit from FuncPageTable.

KVM looks up translations using the image of the page table in the
guest's memory, but we don't have to. By maintaining that image in
addition to rather than instead of maintaining an abstract copy makes
our lookups faster, and ironically avoids duplicate implementation.

Change-Id: I9ff4cae6f7cf4027c3738b75f74eae50dde2fda1
Reviewed-on: https://gem5-review.googlesource.com/7341
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarch-riscv: Fix floating-poing op classes
Alec Roelke [Fri, 8 Dec 2017 23:29:56 +0000 (18:29 -0500)]
arch-riscv: Fix floating-poing op classes

This patch applies correct miscellaneous or multiply-accumulate op
classes to floating point instructions which had previously been
incorrectly classed as add or multiply instructions.

Change-Id: I959dd8d3152aa341e0f060b003ce1da8c4d688fb
Reviewed-on: https://gem5-review.googlesource.com/6521
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

6 years agoarch-riscv: Fix floating-point conversion bugs
Alec Roelke [Tue, 5 Dec 2017 03:54:35 +0000 (22:54 -0500)]
arch-riscv: Fix floating-point conversion bugs

Using the fetestexcept function to check for specific types of floating
point exceptions is unreliable for some kinds of
floating-point-to-integer conversion operations. RISC-V code used to
make use of them to check for some exceptional cases like overflow and
underflow, which caused incorrect output when compiler optimization is
turned on. This patch changes the use of fetestexcept to explicit checks
for those exceptional cases.

Change-Id: Id983906ea0664dc246e115a9e470d9ab7733bde1
Reviewed-on: https://gem5-review.googlesource.com/6402
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

6 years agosim: Simplify registerThreadContext a little bit.
Gabe Black [Sat, 13 Jan 2018 00:16:56 +0000 (16:16 -0800)]
sim: Simplify registerThreadContext a little bit.

The code in this function was a little convoluted. This change attempts
to simplify it a little bit to make it easier to read.

Change-Id: I1ae557b9fede47fa89a9ea550bd0af8ad242449f
Reviewed-on: https://gem5-review.googlesource.com/7421
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agomem: Track TLB entries in the lookup cache as pointers.
Gabe Black [Sat, 23 Dec 2017 03:21:30 +0000 (19:21 -0800)]
mem: Track TLB entries in the lookup cache as pointers.

Using the architectural page table on x86 and the functional page table
on ARM, both with the twolf benchmark in SE mode, there was no
performance penalty for doing so, and again possibly a performance
improvement. By using a pointer instead of an inline instance, it's
possible for the actual type of the TLB entry to be hidden somewhat,
taking a step towards abstracting away another aspect of the ISAs.

Since the TLB entries are no longer overwritten and now need to be
allocated and freed, this change introduces return types from the
updateCache and eraseCacheEntry functions. These functions will return
the pointer to any entry which has been displaced from the cache which
the caller can either free or ignore, depending on whether the entry
has a purpose outside of the cache.

Because the functional page table stores its entries over a longer time
period, it will generally not delete the pointer returned from those
functions. The "architechtural" page table, ie the one which is backed
by memory, doesn't have any other use for the TlbEntrys and will delete
them. That leads to more news and deletes than there used to be.

To address that, and also to speed up the architectural page table in
general, it would be a good idea to augment the functional page table
with an image of the table in memory, instead of replacing it with one.
The functional page table would provide quick lookups and also avoid
having to translate page table entries to TLB entries, making
performance essentially equivalent to the functional case. The backing
page tables, which are primarily for consumption by the physical
hardware when in KVM, can be updated when mappings change but otherwise
left alone.

If we end up doing that, we could just let the ISA specific process
classes enable whatever additional TLB machinery they need, likely
a backing copy in memory, without any knowledge or involvement from
the ISA agnostic class. We would be able to get rid of the useArchPT
setting and the bits of code in the configs which set it.

Change-Id: I2e21945cd852bb1b3d0740fe6a4c5acbfd9548c5
Reviewed-on: https://gem5-review.googlesource.com/6983
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
6 years agoarch: Fix a fatal_if in most of the arch's process classes.
Gabe Black [Sun, 14 Jan 2018 19:44:04 +0000 (11:44 -0800)]
arch: Fix a fatal_if in most of the arch's process classes.

When switching an assert to a fatal while addressing recent review
feedback, I forgot to reverse the polarity of the condition, making
the fatal fire in exactly the opposite of the conditions it was meant
to.

Change-Id: Icf49864ef449052bbb0d427dca786006166575c4
Reviewed-on: https://gem5-review.googlesource.com/7381
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agosim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().
Xiaoyu Ma [Thu, 30 Nov 2017 15:48:52 +0000 (07:48 -0800)]
sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().

Before this CL, the addTwoLevelCacheHierarchy() function uses the
default L2XBar class as the interconnect between CPU L1 caches and
L2. This CL allows passing a user-defined bus to overwrite the
default L2XBar by adding an optional argument to the function.

Change-Id: I917657272fd4924ee0bed882a226851afba26847
Reviewed-on: https://gem5-review.googlesource.com/7364
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agoutil/m5: add Android.mk
Earl Ou [Fri, 6 Oct 2017 12:55:41 +0000 (20:55 +0800)]
util/m5: add Android.mk

Add Android.mk so we can build m5 tool in Android tree.

Change-Id: I7023130bd3ce5e015b8f7c41941eafb4611da8cb
Reviewed-on: https://gem5-review.googlesource.com/7363
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarch-riscv: Don't crash when printing unknown CSRs
Alec Roelke [Fri, 15 Dec 2017 04:22:10 +0000 (23:22 -0500)]
arch-riscv: Don't crash when printing unknown CSRs

This patch fixes a potential crash if an unnamed CSR is accessed and
debug flags are enabled that print disassembly.  Unknown CSRs will be
identified as "??" followed by the address that was used.

Change-Id: If5ac57f1422bd59c72a1a06206fa9d9dc05d21ef
Reviewed-on: https://gem5-review.googlesource.com/7321
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

6 years agomem-ruby: Fix wakeup timeouts for the MOESI_CMP_token protocol
Nikos Nikoleris [Wed, 3 Jan 2018 11:10:09 +0000 (12:10 +0100)]
mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token protocol

This changeset fixes a bug that was affecting the MOESI_CMP_token
protocol where setting the next timeout required an absolute tick in
the future.

Change-Id: Ibfdb59354e13c7e552cb3389e71bda010f333249
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7163
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agomem-ruby: Remove function that maps responses to a DMA engine
Nikos Nikoleris [Tue, 2 Jan 2018 20:33:25 +0000 (21:33 +0100)]
mem-ruby: Remove function that maps responses to a DMA engine

The function map_Address_to_DMA was used to route responses to the
first (and assumed to be the only) DMA engine in the system. This
function is now unused as protocols handle responses and route them to
the right DMA engine.

Change-Id: I2fba913cf2f12321d1a1e38e7ee85bdf26b8a47a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7162
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agomem-ruby: Add support for multiple DMA engines in MESI_Two_Level
Nikos Nikoleris [Tue, 2 Jan 2018 20:28:07 +0000 (21:28 +0100)]
mem-ruby: Add support for multiple DMA engines in MESI_Two_Level

Previously the MESI_Two_Level protocol supported systems with a single
DMA engine and responses from the directory to DMA requests were
routed back to the only DMA engine. This changeset adds support for
multiple DMA engines in the system by routing the response to the DMA
engine that originally sent the request.

Change-Id: I10ceda682ea29746636862ec8ef2a9c4220ca045
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7161
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agocpu: Make the CPU's TLB parameter a BaseTLB.
Gabe Black [Tue, 9 Jan 2018 03:08:17 +0000 (19:08 -0800)]
cpu: Make the CPU's TLB parameter a BaseTLB.

This is instead of the architecture specific version.

Change-Id: I906ec16eee1f65f0e9b9c24b401430f9ea01637b
Reviewed-on: https://gem5-review.googlesource.com/7349
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarm, power: Make the python TLB simobjects inherit from BaseTLB.
Gabe Black [Tue, 9 Jan 2018 03:07:21 +0000 (19:07 -0800)]
arm, power: Make the python TLB simobjects inherit from BaseTLB.

These were still inheriting from SimObject instead of BaseTLB, making
them incompatible with parameters which expect a BaseTLB.

Change-Id: I05115cc5515f745fdeb85e4dea8eded613647e40
Reviewed-on: https://gem5-review.googlesource.com/7348
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarch,mem: Remove the default value for page size.
Gabe Black [Sat, 23 Dec 2017 01:14:47 +0000 (17:14 -0800)]
arch,mem: Remove the default value for page size.

This breaks one more architecture dependence outside of the ISAs.

Change-Id: I071f9ed73aef78e1cd1752247c183e30854b2d28
Reviewed-on: https://gem5-review.googlesource.com/6982
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
6 years agoarch,mem: Move page table construction into the arch classes.
Gabe Black [Sat, 23 Dec 2017 00:14:03 +0000 (16:14 -0800)]
arch,mem: Move page table construction into the arch classes.

This gets rid of an awkward NoArchPageTable class, and also gives the
arch a place to inject ISA specific parameters (specifically page size)
without having to have TheISA:: in the generic version of these types.

Change-Id: I1412f303460d5c43dafdb9b3cd07af81c908a441
Reviewed-on: https://gem5-review.googlesource.com/6981
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoconfigs: Fill in the cpu.isa field in etrace_replay.py since no default are provided now
Chen Zou [Wed, 3 Jan 2018 22:31:06 +0000 (16:31 -0600)]
configs: Fill in the cpu.isa field in etrace_replay.py since no default are provided now

Change-Id: I5f337b9969820bd74ed67e576e2d1a8e4666ecdb
Reviewed-on: https://gem5-review.googlesource.com/7021
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agostyle: change C/C++ source permissions to noexec
BKP [Tue, 9 Jan 2018 19:16:29 +0000 (13:16 -0600)]
style: change C/C++ source permissions to noexec

Several files in the repository were tracked with execute permissions
even though the files are just normal C/C++ files (and the one .isa).

Change-Id: I976b096acab4a1fc74c5699ef1f9b222c1e635c2
Reviewed-on: https://gem5-review.googlesource.com/7241
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarch-riscv: Make use of ImmOp's polymorphism
Alec Roelke [Sat, 2 Dec 2017 17:58:14 +0000 (12:58 -0500)]
arch-riscv: Make use of ImmOp's polymorphism

This patch makes use of ImmOp's polymorphism to remove unnecessary
casting from the implementations of arithmetic instructions with
immediate operands and to remove the CUIOp format by combining it with
the CIOp format (compressed arithmetic instructions with immediate
operands). Interestingly, RISC-V specifies that instructions with
unsigned immediate operands still need to sign-extend the immediates
from 12 (or 20) bits to 64 bits, so that is left alone.

Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16
Reviewed-on: https://gem5-review.googlesource.com/6401
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

6 years agoalpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.
Gabe Black [Wed, 20 Dec 2017 07:14:34 +0000 (23:14 -0800)]
alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.

This constant is, first, a #define, and second only used in one place.

In that one place, it appears that the code it guards is no longer
necessary in general. It was originally written to avoid refetching a
block of data that you're still in, even if you've moved slightly
farther in it because you're skipping the next instruction due to an
annulled branch delay slot. In reality however, in SPARC, the one ISA
I'm aware of which has this sort of branching behavior, the PC state
object will correctly determine that no branch is happening in these
cases. Code lower down in the loop will then recompute where fetching
should continue based on the next PC, automatically skipping the
annulled branch slot without misinterpretting the gap as a branch.

This change therefore also removes this block of code.

Change-Id: I820ebc9df10aeb4fcb69c12f6a784e9ec616743c
Reviewed-on: https://gem5-review.googlesource.com/6821
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarch-riscv,sim: Support clone syscall in RISC-V
Tuan Ta [Sun, 17 Sep 2017 16:57:21 +0000 (12:57 -0400)]
arch-riscv,sim: Support clone syscall in RISC-V

(1) This patch sets a correct order of clone syscall's arguments for
RISC-V. Linux kernel 4.15 uses CLONE_BACKWARDS flag by default for
RISC-V. The flag in the Linux kernel defines the list of clone syscall's
arguments in the following order:

  clone_flags   (flags)
  newsp         (newStack)
  parent_tidptr (ptidPtr)
  tls           (tlsPtr)
  child_tidptr  (ctidPtr)

Code reference:
  https://github.com/riscv/riscv-linux/blob/master/kernel/fork.c
  https://github.com/riscv/riscv-linux/blob/master/arch/riscv/Kconfig

(2) This patch copies a parent thread's register values to its child
thread in clone syscall.

Change-Id: I2eb1c8e80990861080ce7153503ed784fb2c7bdf
Reviewed-on: https://gem5-review.googlesource.com/6904
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
6 years agomem-cache: Prune unnecessary writebacks in exclusive caches
Nikos Nikoleris [Mon, 4 Sep 2017 15:38:36 +0000 (16:38 +0100)]
mem-cache: Prune unnecessary writebacks in exclusive caches

Exclusive caches use the tempBlock to fill for responses from a
downstream cache. The reason for this is that they only pass the block
to the cache above without keeping a copy. When all requests are
serviced the block is immediately invalidated unless it is dirty, in
which case it has to be written back to the memory below.

To avoid unnecessary writebacks, this changeset forces mostly
exclusive caches to issuse requests that can only fetch clean data
when possible.

Reported-by: Quereshi Muhammad Avais <avais@kaist.ac.kr>
Change-Id: I01b377563f5aa3e12d22f425a04db7c023071849
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agoutil: Add the missing wakecpu m5op in X86.
Hanhwi Jang [Fri, 8 Dec 2017 10:14:24 +0000 (19:14 +0900)]
util: Add the missing wakecpu m5op in X86.

Change-Id: I74876a4638ad37308ecdb0ef68513a968fac8787
Reviewed-on: https://gem5-review.googlesource.com/6501
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoutil: resolve m5op name mismatching in m5op headers.
Hanhwi Jang [Fri, 8 Dec 2017 05:34:59 +0000 (14:34 +0900)]
util: resolve m5op name mismatching in m5op headers.

Two m5op, load_symbol and dist_toggle_sync are defined with
different name in C and asm version headers 'm5ops.h'
The m5ops are named to m5_load_symbol() and m5_dist_toggle_sync().

Change-Id: I9630d74f3fb95bc3dc5fa082778d8f6eaa49b3cb
Reviewed-on: https://gem5-review.googlesource.com/6481
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agocpu: Use the NotAnInst flag to avoid passing an inst to fetch faults.
Gabe Black [Sat, 6 Jan 2018 00:20:14 +0000 (16:20 -0800)]
cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults.

When a fault happens in fetch in O3, a dummy inst is created to carry
the fault through the pipeline to commit, but conceptually there isn't
actually any instruction since we failed to fetch one.

This change marks the dummy instruction as NotAnInst, and when any
such instruction gets to commit, the fault object associated with it
is invoked and passed a null static inst pointer instead of a pointer
to the dummy inst.

Change-Id: I18d993083406deb625402e06af4ba0d4772ca5a3
Reviewed-on: https://gem5-review.googlesource.com/7124
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agocpu: Add a NotAnInst flag to the BaseDynInst class.
Gabe Black [Fri, 5 Jan 2018 23:40:47 +0000 (15:40 -0800)]
cpu: Add a NotAnInst flag to the BaseDynInst class.

This flag means that the instruction isn't an actual instruction, it's
just a placeholder to carry a fault down a pipeline, for instance.

Change-Id: I1cc12b068662dbd3d3b089c9941a07b6e88b57e3
Reviewed-on: https://gem5-review.googlesource.com/7123
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agocpu, power: Get rid of the remnants of the EA computation insts.
Gabe Black [Fri, 5 Jan 2018 23:33:08 +0000 (15:33 -0800)]
cpu, power: Get rid of the remnants of the EA computation insts.

Get rid of some remnants of a system which was intended to separate
address computation into its own instruction object.

Change-Id: I23f9ffd70fcb89a8ea5bbb934507fb00da9a0b7f
Reviewed-on: https://gem5-review.googlesource.com/7122
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarm: Make translateFunctional override the base implementation.
Gabe Black [Sat, 6 Jan 2018 00:17:44 +0000 (16:17 -0800)]
arm: Make translateFunctional override the base implementation.

Now that translateFunctional is a virtual function, having an extra
parameter with a default value makes the compiler fall through to the
base implementation instead of overriding it. This change removes the
default value for the extra parameter, and adds a small wrapper with
the correct signature which overrides the base implementation and calls
the full version with the previously default value for the extra
parameter. To callers this will look like the same thing, but the
the right function will get called.

This was what was already being done for transateAtomic and
translateTiming.

Change-Id: I0b71adf34fd6f326005edbb8eaac93275b437c55
Reviewed-on: https://gem5-review.googlesource.com/7121
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agogpu-compute: call createThreads() on cpu objs in apu_se.py
Tony Gutierrez [Fri, 5 Jan 2018 23:10:47 +0000 (18:10 -0500)]
gpu-compute: call createThreads() on cpu objs in apu_se.py

commit 8ad26e2688b8736f9290086bb4026cc7500429e9
cpu: Don't override ISA if provided by user

removed the default ISA from the BaseCPU, and instead relies on
createThreads() to initiate a default ISA if none is specified. the apu_se.py
script, however does not call creatThreads() leading to a fatal when
constructing CPU objects. this patch adds the appropriate calls to
createThreads() inside apu_se.py.

Change-Id: I16a5929454c59d68a3f1b7b3858c48a70cb76412
Reviewed-on: https://gem5-review.googlesource.com/7101
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

6 years agoarch-riscv: Ignore sched_yield syscall in SE mode
Tuan Ta [Sat, 23 Dec 2017 01:10:46 +0000 (20:10 -0500)]
arch-riscv: Ignore sched_yield syscall in SE mode

Change-Id: I14f22c06eb8fdbe063980b4cd0a49387b9113a97
Reviewed-on: https://gem5-review.googlesource.com/6961
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
6 years agosim: Fix a bug in prlimit syscall in SE mode
Tuan Ta [Thu, 21 Dec 2017 16:06:10 +0000 (11:06 -0500)]
sim: Fix a bug in prlimit syscall in SE mode

The old_limit pointer is supposed to be the 4th argument (index 3) of
the prlimit syscall. This patch sets old_limit pointer to the correct
argument.

Change-Id: I97808f7234cd2622cb3eb2f1e0beb7fc8cf492c1
Reviewed-on: https://gem5-review.googlesource.com/6903
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

6 years agoarch-riscv: Ignore set_robust_list and get_robust_list syscalls
Tuan Ta [Sun, 17 Dec 2017 19:22:12 +0000 (14:22 -0500)]
arch-riscv: Ignore set_robust_list and get_robust_list syscalls

Change-Id: I5a4744e5aed07337144af9f07978b83405b6695b
Reviewed-on: https://gem5-review.googlesource.com/6902
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

6 years agoarch-riscv: Add an implementation of set_tid_address syscall in RISCV
Tuan Ta [Fri, 15 Dec 2017 21:07:05 +0000 (16:07 -0500)]
arch-riscv: Add an implementation of set_tid_address syscall in RISCV

Change-Id: Ida29ea6f6a9c3efe00aaebbfcb6b537fc62f6d06
Reviewed-on: https://gem5-review.googlesource.com/6901
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

6 years agoarch-riscv: Correct syscall argument reg count
Alec Roelke [Fri, 5 Jan 2018 00:04:43 +0000 (19:04 -0500)]
arch-riscv: Correct syscall argument reg count

As per the discussion in patch #6904 and the Linux 4.15 kernel code for
RISC-V, RISC-V has 7 system call argument registers, x10 through x16 (a0
through a6), with x17 (a7) being used for the system call number.

Change-Id: I0080eca78ffa844b322bb2cff2a51ab2815f3809
Reviewed-on: https://gem5-review.googlesource.com/7081
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

6 years agoarch-riscv: Remove "magic" syscall number constant
Alec Roelke [Thu, 4 Jan 2018 19:17:13 +0000 (14:17 -0500)]
arch-riscv: Remove "magic" syscall number constant

getSyscallArg() in RISC-V has an explicit check to make sure that the
register index is within the bounds of the system call register indices
vector. This patch fixes it so that it uses SyscallArgumentRegs.size()
rather than a "magic" constant that has to be updated every time
SyscallArgumentRegs is changed.

Change-Id: I2935d811177dc8028cb3df64b250ba997bc970d8
Reviewed-on: https://gem5-review.googlesource.com/7061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

6 years agoconfig: Handle NULL simobject parameters in read_config.py.
Gabe Black [Fri, 22 Dec 2017 04:49:50 +0000 (20:49 -0800)]
config: Handle NULL simobject parameters in read_config.py.

Change-Id: If0f87e8ee37099be4d0f3567db4fc34f8467e409
Reviewed-on: https://gem5-review.googlesource.com/6943
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agoconfig: Fix parsing AddrRange parameters in read_config.py.
Gabe Black [Fri, 22 Dec 2017 04:26:41 +0000 (20:26 -0800)]
config: Fix parsing AddrRange parameters in read_config.py.

The format of AddrRange parameters was changed, but
config/example/read_config.py wasn't updated for the new format.

Change-Id: Ie0da7aaa47c827bacc2b4f7f44929efd868b8794
Reviewed-on: https://gem5-review.googlesource.com/6942
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agoconfig: Add a --checkpoint-dir argument to read_config.py.
Gabe Black [Fri, 15 Dec 2017 01:29:17 +0000 (17:29 -0800)]
config: Add a --checkpoint-dir argument to read_config.py.

This argument lets the user restore a checkpoint after loading
simulator state from config.ini.

Change-Id: I6e0630d75b798a1d2536e2408660843f57f46c4b
Reviewed-on: https://gem5-review.googlesource.com/6941
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

7 years agoalpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.
Gabe Black [Wed, 20 Dec 2017 08:06:07 +0000 (00:06 -0800)]
alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.

It's no longer used.

Change-Id: I4a71bcb214f1bb186b92ef50841eca635e6701c5
Reviewed-on: https://gem5-review.googlesource.com/6826
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

7 years agoriscv,x86: Stop using the arch Nop machine instruction unnecessarily.
Gabe Black [Wed, 20 Dec 2017 08:02:47 +0000 (00:02 -0800)]
riscv,x86: Stop using the arch Nop machine instruction unnecessarily.

That particular ExtMachInst is a convenient placeholder, but a value
of 0 in RISCV or a static uninitialized ExtMachInst (which will
therefore be all zeroes) on x86 works just as well, and removes the
need for an ISA specific constant.

Also, the idea of a universal Nop doesn't always make sense since it
could be that what, exactly, doesn't do anything depends on context
which would be lost on a constant value of an ExtMachInst. For
instance, the value of an ExtMachInst that makes sense might depend on
what mode the CPU was in, etc.

Change-Id: I1f1a43a5c607a667e11b79bcf6e059e4f7141b3f
Reviewed-on: https://gem5-review.googlesource.com/6825
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Gabe Black <gabeblack@google.com>

7 years agoarch,cpu: "virtualize" the TLB interface.
Gabe Black [Fri, 22 Dec 2017 09:07:55 +0000 (01:07 -0800)]
arch,cpu: "virtualize" the TLB interface.

CPUs have historically instantiated the architecture specific version
of the TLBs to avoid a virtual function call, making them a little bit
more dependent on what the current ISA is. Some simple performance
measurement, the x86 twolf regression on the atomic CPU, shows that
there isn't actually any performance benefit, and if anything the
simulator goes slightly faster (although still within margin of error)
when the TLB functions are virtual.

This change switches everything outside of the architectures themselves
to use the generic BaseTLB type, and then inside the ISA for them to
cast that to their architecture specific type to call into architecture
specific interfaces.

The ARM TLB needed the most adjustment since it was using non-standard
translation function signatures. Specifically, they all took an extra
"type" parameter which defaulted to normal, and translateTiming
returned a Fault. translateTiming actually doesn't need to return a
Fault because everywhere that consumed it just stored it into a
structure which it then deleted(?), and the fault is stored in the
Translation object when the translation is done.

A little more work is needed to fully obviate the arch/tlb.hh header,
so the TheISA::TLB type is still visible outside of the ISAs.
Specifically, the TlbEntry type is used in the generic PageTable which
lives in src/mem.

Change-Id: I51b68ee74411f9af778317eff222f9349d2ed575
Reviewed-on: https://gem5-review.googlesource.com/6921
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
7 years agocpu: Use the generic nop static inst instead of decoding the arch version.
Gabe Black [Wed, 20 Dec 2017 07:48:00 +0000 (23:48 -0800)]
cpu: Use the generic nop static inst instead of decoding the arch version.

This removes a dependence on the ISA.

Change-Id: I01013bc70558f0831327213912bcac11258066a6
Reviewed-on: https://gem5-review.googlesource.com/6824
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

7 years agocpu: Add a pointer to a generic Nop StaticInst.
Gabe Black [Wed, 20 Dec 2017 07:44:39 +0000 (23:44 -0800)]
cpu: Add a pointer to a generic Nop StaticInst.

This can be used whenever generic code needs a filler instruction that
doesn't do anything.

Change-Id: Ib245d3e880a951e229eb315a09ecc7c47e6ae00f
Reviewed-on: https://gem5-review.googlesource.com/6823
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

7 years agoarch-arm: Fixed WFE/WFI trapping behaviour
Giacomo Travaglini [Fri, 1 Dec 2017 16:25:55 +0000 (16:25 +0000)]
arch-arm: Fixed WFE/WFI trapping behaviour

This patch fixes the WFx trapping behaviour by introducing the arm arm
v8 pseudocode functions: checkForWFxTrap32 and checkForWFxTrap64

Change-Id: I3db0d78b5c4ad46860e6d199c2f2fc7b41842840
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6622
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

7 years agoarch-arm: Hyp routed undef fault need to change its syndrome
Giacomo Travaglini [Fri, 1 Dec 2017 13:24:29 +0000 (13:24 +0000)]
arch-arm: Hyp routed undef fault need to change its syndrome

If undefined instruction has to be routed to EL2, the HSR register
must change the HSR.EC and HSR.ISS accordingly, which means not using
the EL1 exception syndrome, but the unknown reason one (EC=0, ISS=0)

Change-Id: I1540c713ab545bf307c1dad3ae305de4178443f4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6621
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

7 years agoarch-arm: Fix StaticInst encoding() method
Giacomo Travaglini [Tue, 19 Dec 2017 18:15:32 +0000 (18:15 +0000)]
arch-arm: Fix StaticInst encoding() method

The previously introduced method was missing the machInst value
to be masked.

Change-Id: Ic722f7cc2abc680da1a1f19c08299338b5c859a6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chuan Zhu <chuan.zhu@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6881
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

7 years agocpu: Fix exit_gen.cc which used misc.hh instead of logging.hh.
Gabe Black [Wed, 20 Dec 2017 07:35:30 +0000 (23:35 -0800)]
cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh.

Change-Id: I868021a01eb3e7902a4d64283bdfaa93c6d9f964
Reviewed-on: https://gem5-review.googlesource.com/6822
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

7 years agoarch-arm: Instruction size methods in StaticInst class
Giacomo Travaglini [Fri, 15 Dec 2017 10:03:19 +0000 (10:03 +0000)]
arch-arm: Instruction size methods in StaticInst class

This patch is introducing some methods in StaticInst so that is possible
to get the instruction size in byte of the instruction (can be 2 bytes
in Thumb) and the correct opcode (The machInst field contains some
appended metadata)

Change-Id: I3bed4d9fd7c77feaeded40ded192afe445d306ea
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6781
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

7 years agoarch-arm: Change casting type from reinterpret to static
Giacomo Travaglini [Fri, 15 Dec 2017 15:56:03 +0000 (15:56 +0000)]
arch-arm: Change casting type from reinterpret to static

Cosmetic fix: prefer static_cast rather than reinterpret_cast in
hierarchy.

Change-Id: Ic0e5a4df9b18072a6df5ee316f674241074c349a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6761
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

7 years agocpu-tester: Added ExitGen to TrafficGen
Riken Gohil [Tue, 1 Aug 2017 10:08:16 +0000 (11:08 +0100)]
cpu-tester: Added ExitGen to TrafficGen

Added the ExitGen to the TrafficGenerator which allows an EXIT
state to be added to the TrafficGen configuration file. Entering this
state will cause the simulation to exit immediately. Please note that
if multiple TrafficGen instances have an EXIT state, the first of these
to be encountered will cause the simulation to terminate.

Change-Id: Ieea51f05ffb780771f007787a2b119f79143d0c1
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5723
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

7 years agocpu-tester: Refactoring traffic generators into separate files.
Riken Gohil [Wed, 12 Jul 2017 16:33:11 +0000 (17:33 +0100)]
cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 years agomem-ruby: Support atomic_noncaching acceses in ruby
Swapnil Haria [Thu, 9 Nov 2017 19:04:39 +0000 (13:04 -0600)]
mem-ruby: Support atomic_noncaching acceses in ruby

Ruby has no support for atomic_noncaching accesses, which prevents using
it with kvm-cpu. This patch fixes this by directly forwarding atomic
requests from the ruby port/sequencer to the corresponding directory
based on the destination address of the packet.

Change-Id: I0b4928bfda44fd9e5e48583c51d1ea422800da2d
Reviewed-on: https://gem5-review.googlesource.com/5601
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>

7 years agoarch-riscv: Define AT_RANDOM properly
Alec Roelke [Thu, 14 Dec 2017 17:17:31 +0000 (12:17 -0500)]
arch-riscv: Define AT_RANDOM properly

According to the getauxval(3) man page, the AT_RANDOM aux value should
be a pointer to 16 random bytes.  In the initial implementation of
RISC-V, this was based on spike's program stack setup, which copied the
program header table there instead.  This patch changes the
implementation to use the proper 16 random bytes, making it compatible
with some RISC-V programs that use custom linker scripts.

Change-Id: Idaae7f19bf3ed3fd06d293e5e9c0b6f778270eb2
Reviewed-on: https://gem5-review.googlesource.com/6681
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

7 years agoarch-riscv: Increase maximum stack size
Alec Roelke [Thu, 14 Dec 2017 00:00:11 +0000 (19:00 -0500)]
arch-riscv: Increase maximum stack size

This patch increases the maximum stack size of RISC-V, which should help
to reduce problems with programs that allocate large amounts of data on
the stack or do many small allocations.

Change-Id: I1d760050229b12f01a4a8f24c047b587299fef6d
Reviewed-on: https://gem5-review.googlesource.com/6661
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

7 years agomisc: Updates for gcc7.2 for x86
Jason Lowe-Power [Wed, 13 Dec 2017 18:19:04 +0000 (10:19 -0800)]
misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
  case statments. C++17 adds the [[fallthrough]]; declaration. However,
  to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
  M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
  if that doesn't exist, it defaults to nothing (no older compilers
  generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
  in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
  https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>
7 years agoext: Upgrade PyBind11 to version 2.2.1
Jason Lowe-Power [Sat, 18 Nov 2017 01:02:05 +0000 (17:02 -0800)]
ext: Upgrade PyBind11 to version 2.2.1

This upgrade is necessary for pybind to build with GCC 7.2.

We still need to add the patch for stl.h. MSC_FULL_VER change is no longer
needed.
See https://gem5-review.googlesource.com/c/public/gem5/+/2230

Change-Id: I806729217d022070583994c2dfcaa74476aef30f
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5801
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

7 years agox86: Use operand size 4 when it would be 2 for cmpxchg8b.
Gabe Black [Wed, 13 Dec 2017 09:03:00 +0000 (01:03 -0800)]
x86: Use operand size 4 when it would be 2 for cmpxchg8b.

This means the instruction is treated as cmpxchg8b when the effective
operand size is 16 bits.

Change-Id: I4d9bb295f96097e1746a9bbccb2c579d14738fab
Reviewed-on: https://gem5-review.googlesource.com/6603
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

7 years agoscons, tests: Fix occasional linking error
Andreas Sandberg [Wed, 13 Dec 2017 14:29:39 +0000 (14:29 +0000)]
scons, tests: Fix occasional linking error

There are some cases where scons incorrectly adds the same object
multiple times to the linker command line. This seems to be caused by
the test's source list being updated in place when determining test
framework dependencies. Fix this by explicitly copying the source list
and manipulate the copy.

Without this change, the following command fails:
scons ./build/ARM/unittests.opt/base/pixeltest.xml

Whereas this command succeeds:
scons ./build/ARM/base/pixeltest.opt

Change-Id: I642efdf9d62a5478e49ba51efe1a3a5ba453e21f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6641
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
7 years agoscons, tests: Add support for GTest XML generation
Andreas Sandberg [Wed, 13 Dec 2017 11:14:28 +0000 (11:14 +0000)]
scons, tests: Add support for GTest XML generation

The GTest framework supports result generation in XML (JUnit). Enable
this by creating unit test specific targets in the
build/${BUILD_OPTS}/unittests.${VARIANT} directory. Targets in the
directory use the following naming convention:

${SRC_PATH}/${TEST_NAME}.xml

For example, the opt version of the bitunion test built for ARM would
have this path:

build/ARM/unittests.opt/base/bituniontest.xml

Change-Id: I174dff16817734db05b08ce1d5bcf52e8697bbac
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6624
Reviewed-by: Gabe Black <gabeblack@google.com>