Luke Kenneth Casson Leighton [Sun, 19 Jun 2022 15:08:03 +0000 (16:08 +0100)]
extend minor_22.csv bitsel pattern to cover bits 21..31
Dmitry Selyutin [Fri, 17 Jun 2022 13:51:18 +0000 (13:51 +0000)]
sv_binutils: drop SVP64_NAME_MAX
Dmitry Selyutin [Fri, 17 Jun 2022 13:50:00 +0000 (13:50 +0000)]
sv_binutils: minor naming conventions fixup
Dmitry Selyutin [Fri, 17 Jun 2022 13:47:38 +0000 (13:47 +0000)]
sv_binutils: rename Entry to Record
Dmitry Selyutin [Fri, 17 Jun 2022 13:41:32 +0000 (13:41 +0000)]
sv_binutils: rename Record to Desc
Luke Kenneth Casson Leighton [Fri, 17 Jun 2022 13:20:44 +0000 (14:20 +0100)]
whoops on an OR rather than an AND
Luke Kenneth Casson Leighton [Fri, 17 Jun 2022 13:14:28 +0000 (14:14 +0100)]
add "redirection" of MTSPR/MFSPR into TRAP pipeline for KAIVB
in PowerDecoderSubset
https://bugs.libre-soc.org/show_bug.cgi?id=859
this reduces a lot of messing about by actually storing KAIVB
directly in the TRAP pipeline which is the only place it is used
Luke Kenneth Casson Leighton [Fri, 17 Jun 2022 12:54:52 +0000 (13:54 +0100)]
add KAIVB SPR 850
https://bugs.libre-soc.org/show_bug.cgi?id=859
Luke Kenneth Casson Leighton [Tue, 14 Jun 2022 14:13:43 +0000 (15:13 +0100)]
update version to 0.0 to stop unnecessary pip3 installs
Luke Kenneth Casson Leighton [Tue, 14 Jun 2022 14:11:36 +0000 (15:11 +0100)]
add version constraints on setup install_requires
Dmitry Selyutin [Wed, 8 Jun 2022 17:53:49 +0000 (17:53 +0000)]
media/Makefile: switch to explicit LE toolchain
Dmitry Selyutin [Wed, 8 Jun 2022 12:31:46 +0000 (12:31 +0000)]
svp64.py: simplify core script translation
Dmitry Selyutin [Wed, 8 Jun 2022 11:52:44 +0000 (11:52 +0000)]
mp3_0: update assembly listing
Dmitry Selyutin [Mon, 6 Jun 2022 19:30:42 +0000 (19:30 +0000)]
svp64.py: fix stdin/stdout modus operandi
Dmitry Selyutin [Mon, 6 Jun 2022 18:27:50 +0000 (18:27 +0000)]
svp64.py: switch print statements to logger
Dmitry Selyutin [Wed, 1 Jun 2022 19:56:13 +0000 (19:56 +0000)]
sv_binutils: consider RA0 operand
Dmitry Selyutin [Wed, 1 Jun 2022 18:39:30 +0000 (18:39 +0000)]
sv_binutils: drop redundant prefix in C tags
Dmitry Selyutin [Wed, 1 Jun 2022 18:16:14 +0000 (18:16 +0000)]
sv_binutils: exclude useless records
Dmitry Selyutin [Wed, 1 Jun 2022 18:07:11 +0000 (18:07 +0000)]
sv_binutils: refactor CSV iteration
Dmitry Selyutin [Wed, 1 Jun 2022 17:03:41 +0000 (17:03 +0000)]
sv_binutils: allow excluding enum values
Dmitry Selyutin [Wed, 1 Jun 2022 17:39:24 +0000 (17:39 +0000)]
sv_binutils: update sv_extra naming
Dmitry Selyutin [Wed, 1 Jun 2022 11:12:52 +0000 (11:12 +0000)]
sv_binutils: fix selector names
Dmitry Selyutin [Wed, 1 Jun 2022 11:05:00 +0000 (11:05 +0000)]
sv_binutils: use ppc_opindex_t instead of unsigned char
Dmitry Selyutin [Tue, 31 May 2022 19:21:15 +0000 (19:21 +0000)]
sv_binutils: use BC instead of CRB
Dmitry Selyutin [Tue, 31 May 2022 16:16:03 +0000 (16:16 +0000)]
sv_binutils: fix enum name in C code
Dmitry Selyutin [Fri, 27 May 2022 12:17:24 +0000 (12:17 +0000)]
sv_binutils: follow binutils PPC indentation
Dmitry Selyutin [Fri, 27 May 2022 12:16:23 +0000 (12:16 +0000)]
sv_binutils: make C enums more readable
Dmitry Selyutin [Fri, 27 May 2022 12:12:26 +0000 (12:12 +0000)]
sv_binutils: rename opsel to opindex as in binutils
Luke Kenneth Casson Leighton [Thu, 26 May 2022 17:00:33 +0000 (18:00 +0100)]
add preamble on reg field encoding
Luke Kenneth Casson Leighton [Thu, 26 May 2022 16:49:36 +0000 (17:49 +0100)]
split out CR field encoding into function
add link to specification
Luke Kenneth Casson Leighton [Thu, 26 May 2022 15:11:04 +0000 (16:11 +0100)]
add some code-comments to explain CR field svp64 EXTRA encoding
Luke Kenneth Casson Leighton [Thu, 26 May 2022 14:55:03 +0000 (15:55 +0100)]
Revert "svp64.py: simplify CR sv_extra and field processing"
This reverts commit
d56564910763a69f113615bedf94022da9457de5.
Dmitry Selyutin [Thu, 26 May 2022 14:23:07 +0000 (14:23 +0000)]
svp64.py: always put leading zeroes for prefix
Dmitry Selyutin [Thu, 26 May 2022 12:14:03 +0000 (12:14 +0000)]
svp64.py: simplify CR sv_extra and field processing
Luke Kenneth Casson Leighton [Fri, 20 May 2022 11:54:05 +0000 (12:54 +0100)]
bit of a mess being sorted out
1) update to this page was inconsistent: now fixed
https://libre-soc.org/openpower/sv/bitmanip/
2) power_decoder.py bitsel for minor_22.csv had been set to (1,5) which
is *only four bits* (LSB0 numbering, python-style) 1 2 3 4
where what was actually needed was (1,6) to be bits (MSB0) 26..30
3) when converting to "ignore" format (previous:
0b00000 new 000000-)
and adding the extra bit, (2) messed things up.
bitsel has now been set to (0,6) which is bits 0 1 2 3 4 5
aka (MSB0) 26..31 and the four instructions setvl/svremap/svshap/svstep
set to 10011- and 011001 etc. as appropriate
4) the minor_22.csv entries for both svshape and svremap were set to
Rc=1 mode which is NOT correct
astoundingly the unit tests all functioned correctly despite the above
errors. now all corrected, unit test test_caller_setvl.py still functions
Dmitry Selyutin [Thu, 19 May 2022 11:02:52 +0000 (11:02 +0000)]
temporarily revert opcode changes
b9ffa13 isatables/minor_22.csv: reflect a new XO bit
0e87485 power_decoder: reflect a new XO bit
e5564ad svp64.py: sync remap opcode
c968dab svp64.py: sync svshape opcode
Dmitry Selyutin [Thu, 19 May 2022 07:58:09 +0000 (07:58 +0000)]
isatables/minor_22.csv: reflect a new XO bit
Dmitry Selyutin [Thu, 19 May 2022 07:56:30 +0000 (07:56 +0000)]
power_decoder: reflect a new XO bit
Dmitry Selyutin [Wed, 18 May 2022 20:01:40 +0000 (20:01 +0000)]
svp64.py: sync remap opcode
Dmitry Selyutin [Wed, 18 May 2022 19:39:22 +0000 (19:39 +0000)]
svp64.py: sync svshape opcode
Luke Kenneth Casson Leighton [Wed, 18 May 2022 10:32:37 +0000 (11:32 +0100)]
add BM-Form and CRB-Form for bitmanip
Luke Kenneth Casson Leighton [Mon, 16 May 2022 13:37:25 +0000 (14:37 +0100)]
add to VA-Form, alter XO on SVM and SVRM Form
Luke Kenneth Casson Leighton [Mon, 16 May 2022 12:42:36 +0000 (13:42 +0100)]
add VA2-Form for Bitmanip ops [DRAFT]
Luke Kenneth Casson Leighton [Sun, 15 May 2022 22:49:29 +0000 (23:49 +0100)]
add L field to TLI-Form for grwvlut
Luke Kenneth Casson Leighton [Sat, 14 May 2022 12:20:04 +0000 (13:20 +0100)]
cut/paste error resulted in Rc=0 twice, should be Rc=1
Luke Kenneth Casson Leighton [Sat, 14 May 2022 12:18:16 +0000 (13:18 +0100)]
cut/paste error resulted in Rc=0 twice, should be Rc=1
Luke Kenneth Casson Leighton [Thu, 12 May 2022 06:34:23 +0000 (07:34 +0100)]
add "DRAFT" in front of svfparith instruction descriptions
Jacob Lifshay [Thu, 12 May 2022 01:52:07 +0000 (18:52 -0700)]
add ci
Luke Kenneth Casson Leighton [Tue, 10 May 2022 09:55:22 +0000 (10:55 +0100)]
add SimpleV-Form SVL/SVM/SVRM to svp64.py
Luke Kenneth Casson Leighton [Tue, 10 May 2022 09:49:38 +0000 (10:49 +0100)]
rename comments persistent bit on svremap
Luke Kenneth Casson Leighton [Mon, 9 May 2022 14:24:29 +0000 (15:24 +0100)]
comments for setvl were the wrong bit-position
not the actual fields (whew)
Luke Kenneth Casson Leighton [Mon, 9 May 2022 13:40:46 +0000 (14:40 +0100)]
update comments on sv.svstep
Luke Kenneth Casson Leighton [Mon, 9 May 2022 13:38:23 +0000 (14:38 +0100)]
remove sv.setvl but *not* sv.svstep
Luke Kenneth Casson Leighton [Mon, 9 May 2022 13:37:06 +0000 (14:37 +0100)]
whitespace
Luke Kenneth Casson Leighton [Mon, 9 May 2022 13:35:22 +0000 (14:35 +0100)]
Revert "remove appearance of supporting sv.setvl and sv.svstep"
This reverts commit
7351a6051e032234cb52a0833f3eb2262023a775.
Luke Kenneth Casson Leighton [Sun, 8 May 2022 18:08:23 +0000 (19:08 +0100)]
remove appearance of supporting sv.setvl and sv.svstep
Luke Kenneth Casson Leighton [Sun, 8 May 2022 12:00:43 +0000 (13:00 +0100)]
add code-comments explaining that setvl, svstep svremap and svshape are
all 32-bit *only* as they are *control* instructions not themselves
vector instructions
Dmitry Selyutin [Wed, 4 May 2022 16:02:57 +0000 (16:02 +0000)]
sv_binutils: do not index array entries
Dmitry Selyutin [Wed, 4 May 2022 14:32:12 +0000 (14:32 +0000)]
sv_binutils: update disclaimer
Dmitry Selyutin [Tue, 3 May 2022 17:00:18 +0000 (17:00 +0000)]
sv_binutils: whitespaces cleanup, another take
Luke Kenneth Casson Leighton [Tue, 3 May 2022 16:53:33 +0000 (17:53 +0100)]
space at end of lines
Luke Kenneth Casson Leighton [Tue, 3 May 2022 10:31:00 +0000 (11:31 +0100)]
code-comments on madded and divmod2du should say RS=RT+MAXVL now
Luke Kenneth Casson Leighton [Tue, 3 May 2022 10:30:23 +0000 (11:30 +0100)]
properly fix pagereader.py to parse markdown with indented comments
these are supposed to be developer-hints rather than actually end up
in the pseudocode itself
Luke Kenneth Casson Leighton [Tue, 3 May 2022 08:49:28 +0000 (09:49 +0100)]
allow HTML comments to start with whitespace
this is very deliberate as these comments should not appear in the
pseudocode
Jacob Lifshay [Tue, 3 May 2022 08:30:50 +0000 (01:30 -0700)]
add Rc to ternlogi
Jacob Lifshay [Tue, 3 May 2022 08:28:58 +0000 (01:28 -0700)]
format code
Jacob Lifshay [Tue, 3 May 2022 08:12:09 +0000 (01:12 -0700)]
add make generate
Jacob Lifshay [Tue, 3 May 2022 08:07:22 +0000 (01:07 -0700)]
add svfixedarith.py to .gitignore
Jacob Lifshay [Tue, 3 May 2022 08:05:58 +0000 (01:05 -0700)]
fix syntax error
Luke Kenneth Casson Leighton [Mon, 2 May 2022 15:40:49 +0000 (16:40 +0100)]
whitespace cleanup
Luke Kenneth Casson Leighton [Mon, 2 May 2022 14:53:28 +0000 (15:53 +0100)]
re-run sv_analysis to add mode field to csvs
Luke Kenneth Casson Leighton [Mon, 2 May 2022 14:53:10 +0000 (15:53 +0100)]
add missing SVP64 RM "Mode" field which qualifies instructions
as either NORMAL, LDST, BRANCH, or CROPS
Luke Kenneth Casson Leighton [Fri, 29 Apr 2022 09:47:03 +0000 (10:47 +0100)]
higher bits need to be checked for overflow not lower
after swapping RC and RA, RC is now in the higher bits of divmod2du
Luke Kenneth Casson Leighton [Fri, 29 Apr 2022 09:33:43 +0000 (10:33 +0100)]
invert RC and RA, making divmod2du more like divdu
not divdeu
Luke Kenneth Casson Leighton [Wed, 27 Apr 2022 12:53:24 +0000 (13:53 +0100)]
accidentally added svfixedarith.mdwn to wiki rather than
as an underlay in openpower-isa repo
Dmitry Selyutin [Mon, 25 Apr 2022 20:28:08 +0000 (20:28 +0000)]
sv_binutils: fix fields enum c_decl method
Dmitry Selyutin [Mon, 25 Apr 2022 20:20:22 +0000 (20:20 +0000)]
sv_binutils: fix fields enum naming
Dmitry Selyutin [Mon, 25 Apr 2022 20:15:41 +0000 (20:15 +0000)]
sv_binutils: comment about enum aliases
Dmitry Selyutin [Mon, 25 Apr 2022 20:14:50 +0000 (20:14 +0000)]
sv_binutils: fix missing fields aliases
Dmitry Selyutin [Mon, 25 Apr 2022 19:50:13 +0000 (19:50 +0000)]
sv_binutils: wrap SVP64_FIELD_SET macro
Dmitry Selyutin [Mon, 25 Apr 2022 19:40:32 +0000 (19:40 +0000)]
sv_binutils: undefine temporary macros
Dmitry Selyutin [Mon, 25 Apr 2022 19:31:01 +0000 (19:31 +0000)]
sv_binutils: refactor fields generation
Dmitry Selyutin [Mon, 25 Apr 2022 11:17:46 +0000 (11:17 +0000)]
sv_binutils: support any arguments in c_value method
Dmitry Selyutin [Mon, 25 Apr 2022 09:25:57 +0000 (09:25 +0000)]
sv_binutils: convert c_var methods to simple functions
Dmitry Selyutin [Mon, 25 Apr 2022 09:13:36 +0000 (09:13 +0000)]
sv_binutils: introduce Bitmap class
Dmitry Selyutin [Mon, 25 Apr 2022 07:38:25 +0000 (07:38 +0000)]
selectable_int: remove debug prints
Dmitry Selyutin [Mon, 25 Apr 2022 07:14:57 +0000 (07:14 +0000)]
sv_binutils: fix metaclass arguments
Dmitry Selyutin [Wed, 20 Apr 2022 18:49:20 +0000 (18:49 +0000)]
selectable_int: derive SelectableIntMapping on per-class basis
Dmitry Selyutin [Wed, 20 Apr 2022 12:27:57 +0000 (12:27 +0000)]
sv_binutils: generate fields tables
Dmitry Selyutin [Wed, 20 Apr 2022 11:45:30 +0000 (11:45 +0000)]
sv_binutils: introduce Enum c_name property
Dmitry Selyutin [Wed, 20 Apr 2022 10:56:29 +0000 (10:56 +0000)]
sv_binutils: generate entries and num_entries via classes
Dmitry Selyutin [Wed, 20 Apr 2022 09:36:56 +0000 (09:36 +0000)]
sv_binutils: allow to instantiate integers from symbols
Dmitry Selyutin [Wed, 20 Apr 2022 09:16:33 +0000 (09:16 +0000)]
sv_binutils: introduce fields generation
Dmitry Selyutin [Wed, 20 Apr 2022 09:10:47 +0000 (09:10 +0000)]
isa.caller: support default SVP64PrefixFields initialization
Dmitry Selyutin [Wed, 20 Apr 2022 01:09:37 +0000 (01:09 +0000)]
sv_binutils: simplify array syntax
Dmitry Selyutin [Wed, 20 Apr 2022 00:30:07 +0000 (00:30 +0000)]
sv_binutils: introduce uint8_t and size_t; drop integer metaclass
Dmitry Selyutin [Wed, 20 Apr 2022 00:24:28 +0000 (00:24 +0000)]
sv_binutils: deprecate Opcode classes
Dmitry Selyutin [Wed, 20 Apr 2022 00:18:30 +0000 (00:18 +0000)]
sv_binutils: introduce prefix and suffix in c_var method
Dmitry Selyutin [Tue, 19 Apr 2022 23:10:35 +0000 (23:10 +0000)]
sv_binutils: introduce Array class
Dmitry Selyutin [Tue, 19 Apr 2022 22:58:08 +0000 (22:58 +0000)]
sv_binutils: use c_typedef more often