yosys.git
4 years agoMerge pull request #2102 from YosysHQ/tests_fix
clairexen [Tue, 2 Jun 2020 15:13:08 +0000 (17:13 +0200)]
Merge pull request #2102 from YosysHQ/tests_fix

allow range for mux test

4 years agoMerge pull request #2101 from YosysHQ/mmicko/verific_asymmetric
clairexen [Tue, 2 Jun 2020 15:12:02 +0000 (17:12 +0200)]
Merge pull request #2101 from YosysHQ/mmicko/verific_asymmetric

Support asymmetric memories for verific frontend

4 years agoallow range for mux test
Miodrag Milanovic [Mon, 1 Jun 2020 11:48:19 +0000 (13:48 +0200)]
allow range for mux test

4 years agoSupport asymmetric memories for verific frontend
Miodrag Milanovic [Mon, 1 Jun 2020 08:30:03 +0000 (10:30 +0200)]
Support asymmetric memories for verific frontend

4 years agoMerge pull request #1862 from boqwxp/cleanup_techmap
clairexen [Sun, 31 May 2020 18:40:48 +0000 (20:40 +0200)]
Merge pull request #1862 from boqwxp/cleanup_techmap

Clean up `passes/techmap/techmap.cc`

4 years agoMerge pull request #2081 from YosysHQ/eddie/blackbox_ast
Eddie Hung [Sat, 30 May 2020 15:59:20 +0000 (08:59 -0700)]
Merge pull request #2081 from YosysHQ/eddie/blackbox_ast

blackbox: use Module::makeblackbox() method

4 years agoMerge pull request #2018 from boqwxp/qbfsat-timeout
clairexen [Sat, 30 May 2020 13:04:51 +0000 (15:04 +0200)]
Merge pull request #2018 from boqwxp/qbfsat-timeout

smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.

4 years agosmtbmc: Remove superfluous `yosys-smt2-timeout` file macro.
Alberto Gonzalez [Fri, 29 May 2020 21:30:24 +0000 (21:30 +0000)]
smtbmc: Remove superfluous `yosys-smt2-timeout` file macro.

Co-Authored-By: clairexen <claire@symbioticeda.com>
4 years agoMerge pull request #2029 from whitequark/fix-simplify-memory-sv_logic
clairexen [Fri, 29 May 2020 14:52:11 +0000 (16:52 +0200)]
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic

ast/simplify: don't bitblast async ROMs declared as `logic`

4 years agoMerge pull request #1885 from Xiretza/mod-rem-cells
clairexen [Fri, 29 May 2020 14:37:23 +0000 (16:37 +0200)]
Merge pull request #1885 from Xiretza/mod-rem-cells

Fix modulo/remainder semantics

4 years agoMerge pull request #2092 from whitequark/rtlil-no-space-control
clairexen [Fri, 29 May 2020 14:31:44 +0000 (16:31 +0200)]
Merge pull request #2092 from whitequark/rtlil-no-space-control

Restrict RTLIL::IdString to not contain whitespace or control chars

4 years agoMerge pull request #2017 from boqwxp/qbfsat-cvc4
clairexen [Fri, 29 May 2020 14:23:10 +0000 (16:23 +0200)]
Merge pull request #2017 from boqwxp/qbfsat-cvc4

qbfsat: Add support for CVC4.

4 years agoMerge pull request #2016 from boqwxp/qbfsat-yices
clairexen [Fri, 29 May 2020 14:21:45 +0000 (16:21 +0200)]
Merge pull request #2016 from boqwxp/qbfsat-yices

qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.

4 years agoMerge pull request #2097 from whitequark/ilang_lexer-fix-erange
whitequark [Fri, 29 May 2020 09:04:27 +0000 (09:04 +0000)]
Merge pull request #2097 from whitequark/ilang_lexer-fix-erange

ilang_lexer: fix check for out of range literal

4 years agoilang_lexer: fix check for out of range literal.
whitequark [Mon, 18 May 2020 03:18:42 +0000 (03:18 +0000)]
ilang_lexer: fix check for out of range literal.

Commit ca70a104 did not use a correct check.

4 years agoMerge pull request #2033 from boqwxp/cleanup-verilog-lexer
whitequark [Fri, 29 May 2020 06:46:33 +0000 (06:46 +0000)]
Merge pull request #2033 from boqwxp/cleanup-verilog-lexer

verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.

4 years agoRestrict RTLIL::IdString to not contain whitespace or control chars.
whitequark [Wed, 27 May 2020 05:20:39 +0000 (05:20 +0000)]
Restrict RTLIL::IdString to not contain whitespace or control chars.

This is an existing invariant (most backends can't cope with these)
but one that was not checked or documented.

4 years agoDocument division and modulo cells
Xiretza [Thu, 28 May 2020 20:11:44 +0000 (22:11 +0200)]
Document division and modulo cells

4 years agoUpdate CHANGELOG
Xiretza [Sat, 2 May 2020 09:30:30 +0000 (11:30 +0200)]
Update CHANGELOG

4 years agoAdd comments for mod/div semantics to rtlil.h
Xiretza [Sat, 2 May 2020 09:24:19 +0000 (11:24 +0200)]
Add comments for mod/div semantics to rtlil.h

4 years agoExpand tests/simple/constmuldivmod.v
Xiretza [Tue, 21 Apr 2020 14:37:29 +0000 (16:37 +0200)]
Expand tests/simple/constmuldivmod.v

4 years agoAdd flooring division operator
Xiretza [Tue, 21 Apr 2020 10:51:58 +0000 (12:51 +0200)]
Add flooring division operator

The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.

4 years agoAdd flooring modulo operator
Xiretza [Wed, 8 Apr 2020 17:30:47 +0000 (19:30 +0200)]
Add flooring modulo operator

The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.

4 years agoMerge pull request #2095 from rswarbrick/hier-typo
whitequark [Thu, 28 May 2020 10:49:14 +0000 (10:49 +0000)]
Merge pull request #2095 from rswarbrick/hier-typo

Fix small typos in documentation for hierarchy command

4 years agoFix small typos in documentation for hierarchy command
Rupert Swarbrick [Thu, 28 May 2020 10:39:44 +0000 (11:39 +0100)]
Fix small typos in documentation for hierarchy command

4 years agoMerge pull request #2091 from boqwxp/printattrs
whitequark [Thu, 28 May 2020 10:25:34 +0000 (10:25 +0000)]
Merge pull request #2091 from boqwxp/printattrs

Add `printattrs` command to print attributes of currently selected objects.

4 years agoMerge pull request #2051 from Xiretza/makefile-cd-warning
whitequark [Thu, 28 May 2020 10:00:49 +0000 (10:00 +0000)]
Merge pull request #2051 from Xiretza/makefile-cd-warning

Suppress warning during initial clone of ABC repo

4 years agoMerge pull request #2031 from epfl-vlsc/master
whitequark [Thu, 28 May 2020 09:59:17 +0000 (09:59 +0000)]
Merge pull request #2031 from epfl-vlsc/master

Add extmodule support to firrtl backend

4 years agoMerge pull request #2063 from boqwxp/techmapped-firrtl
whitequark [Thu, 28 May 2020 09:42:58 +0000 (09:42 +0000)]
Merge pull request #2063 from boqwxp/techmapped-firrtl

firrtl: Accept techmapped cell types in FIRRTL backend.

4 years agoMerge pull request #2088 from rswarbrick/count-at
whitequark [Thu, 28 May 2020 09:41:17 +0000 (09:41 +0000)]
Merge pull request #2088 from rswarbrick/count-at

Minor optimisation in Module::wire() and Module::cell()

4 years agoMerge pull request #2087 from rswarbrick/lex-warn
whitequark [Thu, 28 May 2020 09:41:04 +0000 (09:41 +0000)]
Merge pull request #2087 from rswarbrick/lex-warn

Silence spurious warning in Verilog lexer when compiling with GCC

4 years agoMerge pull request #2086 from rswarbrick/sigbit
whitequark [Thu, 28 May 2020 09:40:49 +0000 (09:40 +0000)]
Merge pull request #2086 from rswarbrick/sigbit

Use default copy constructor for RTLIL::SigBit

4 years agoMerge pull request #2084 from rswarbrick/c_str
whitequark [Thu, 28 May 2020 09:40:35 +0000 (09:40 +0000)]
Merge pull request #2084 from rswarbrick/c_str

Use c_str(), not str() for IdString/std::string == and != operators

4 years agoprintattrs: Simplify `get_indent_str()`.
Alberto Gonzalez [Thu, 28 May 2020 05:30:00 +0000 (05:30 +0000)]
printattrs: Simplify `get_indent_str()`.

Co-Authored-By: Xiretza <xiretza@xiretza.xyz>
4 years agoprintattrs: Refactor indentation string building for clarity.
Alberto Gonzalez [Wed, 27 May 2020 23:15:07 +0000 (23:15 +0000)]
printattrs: Refactor indentation string building for clarity.

Co-Authored-By: whitequark <whitequark@whitequark.org>
4 years agoprintattrs: Add test.
Alberto Gonzalez [Wed, 27 May 2020 07:58:10 +0000 (07:58 +0000)]
printattrs: Add test.

4 years agoprintattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately.
Alberto Gonzalez [Wed, 27 May 2020 07:40:40 +0000 (07:40 +0000)]
printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately.

Co-Authored-By: whitequark <whitequark@whitequark.org>
4 years agomisc: Add `printattrs` command.
Alberto Gonzalez [Wed, 27 May 2020 04:07:34 +0000 (04:07 +0000)]
misc: Add `printattrs` command.

4 years agoMerge pull request #2090 from whitequark/cxxrtl-fixes
whitequark [Tue, 26 May 2020 22:18:14 +0000 (22:18 +0000)]
Merge pull request #2090 from whitequark/cxxrtl-fixes

Minor fixes for CXXRTL

4 years agocxxrtl: make logging a little bit nicer.
whitequark [Tue, 26 May 2020 21:37:32 +0000 (21:37 +0000)]
cxxrtl: make logging a little bit nicer.

4 years agocxxrtl: add missing parts of commit 281c9685.
whitequark [Tue, 26 May 2020 06:00:40 +0000 (06:00 +0000)]
cxxrtl: add missing parts of commit 281c9685.

4 years agoSilence spurious warning in Verilog lexer when compiling with GCC
Rupert Swarbrick [Fri, 22 May 2020 13:29:42 +0000 (14:29 +0100)]
Silence spurious warning in Verilog lexer when compiling with GCC

The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.

4 years agoMinor optimisation in Module::wire() and Module::cell()
Rupert Swarbrick [Tue, 26 May 2020 14:19:39 +0000 (15:19 +0100)]
Minor optimisation in Module::wire() and Module::cell()

The existing code does a search to figure out whether id is in the
dict (with the call to count()), and then looks it up again to get the
result (with the call to at()). This version calls find() instead,
avoiding the double lookup.

Code size increases slightly (6kb). I think this is because the
contents of find() are getting inlined, and then inlined into lots of
the callsites for cell() and wire().

Looking at the compiled code before this patch, you just get
a (non-inlined) call to count() followed by a call to at(). After the
patch, the contents of find() have been inlined (so you see do_hash,
then do_lookup). The result for each function is about 30 bytes / 40%
bigger, which presumably also enlarges call-sites that inline it.

4 years agoUse default copy constructor for RTLIL::SigBit
Rupert Swarbrick [Fri, 22 May 2020 15:59:24 +0000 (16:59 +0100)]
Use default copy constructor for RTLIL::SigBit

There was a handwritten copy constructor, which I'm not sure was
actually legal C++ (it unconditionally read from the 'data' member of
a union, which wouldn't have been written if wire was true). It was
also a bit less efficient than the constructor you get from the
compiler by default (which is allowed to just copy the memory).

This gives a marginal (~0.25%) decrease in code size when compiled
with GCC 9.3.

4 years agoUse c_str(), not str() for IdString/std::string == and != operators
Rupert Swarbrick [Tue, 26 May 2020 10:51:06 +0000 (11:51 +0100)]
Use c_str(), not str() for IdString/std::string == and != operators

These operators work by fetching the string from the global string
table and then comparing with the std::string that was passed in as
rhs.

Using str() means that we create a std::string (strlen; malloc;
memcpy), compare for equality (another memcmp if they have the same
length) and then finally free the string.

Using c_str() means that we pass the const char* straight to
std::string's equality operator. This ends up as a call to
std::string::compare (the const char* flavour), which is essentially
strcmp.

4 years agoMerge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
Eddie Hung [Mon, 25 May 2020 21:21:10 +0000 (14:21 -0700)]
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy

xilinx: tidy up cells_sim.v a little

4 years agosmtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
Alberto Gonzalez [Fri, 1 May 2020 23:17:35 +0000 (23:17 +0000)]
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.

4 years agoqbfsat: Add support for CVC4.
Alberto Gonzalez [Fri, 1 May 2020 08:12:23 +0000 (08:12 +0000)]
qbfsat: Add support for CVC4.

4 years agoqbfsat: Move SMT2 info statements back to the top of the file.
Alberto Gonzalez [Mon, 25 May 2020 20:32:13 +0000 (20:32 +0000)]
qbfsat: Move SMT2 info statements back to the top of the file.

4 years agoqbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
Alberto Gonzalez [Thu, 30 Apr 2020 21:27:18 +0000 (21:27 +0000)]
qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.

Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.

4 years agoblackbox: re-use existing Module::makeblackbox() method
Eddie Hung [Mon, 25 May 2020 17:53:49 +0000 (10:53 -0700)]
blackbox: re-use existing Module::makeblackbox() method

4 years agotests: xilinx macc test to have initval, shorten BMC depth for runtime
Eddie Hung [Mon, 25 May 2020 16:35:41 +0000 (09:35 -0700)]
tests: xilinx macc test to have initval, shorten BMC depth for runtime

4 years agoxilinx: tidy up cells_sim.v a little
Eddie Hung [Mon, 25 May 2020 16:47:08 +0000 (09:47 -0700)]
xilinx: tidy up cells_sim.v a little

4 years agoMerge pull request #2044 from YosysHQ/eddie/fix2037
Eddie Hung [Mon, 25 May 2020 16:14:00 +0000 (09:14 -0700)]
Merge pull request #2044 from YosysHQ/eddie/fix2037

verilog: allow attributes on behavioural statements (including null statement)

4 years agoverilog: move attr from simple_behav_stmt to its children to attach
Eddie Hung [Thu, 21 May 2020 16:46:26 +0000 (09:46 -0700)]
verilog: move attr from simple_behav_stmt to its children to attach

4 years agotest: add attribute-before-stmt test from @nakengelhardt
Eddie Hung [Thu, 14 May 2020 23:32:14 +0000 (16:32 -0700)]
test: add attribute-before-stmt test from @nakengelhardt

4 years agoverilog: do not warn for attributes on null statements
Eddie Hung [Thu, 14 May 2020 17:46:40 +0000 (10:46 -0700)]
verilog: do not warn for attributes on null statements

4 years agotests: add an generate-else test too
Eddie Hung [Mon, 11 May 2020 17:26:08 +0000 (10:26 -0700)]
tests: add an generate-else test too

4 years agoverilog: handle empty generate statement by removing gen_stmt_or_null...
Eddie Hung [Mon, 11 May 2020 17:20:33 +0000 (10:20 -0700)]
verilog: handle empty generate statement by removing gen_stmt_or_null...

... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.

4 years agoverilog: fix #2037 by permitting (and freeing) attributes on null stmt
Eddie Hung [Mon, 11 May 2020 16:33:19 +0000 (09:33 -0700)]
verilog: fix #2037 by permitting (and freeing) attributes on null stmt

4 years agotests: add #2037 testcase
Eddie Hung [Mon, 11 May 2020 16:33:11 +0000 (09:33 -0700)]
tests: add #2037 testcase

4 years agoMerge pull request #2015 from boqwxp/qbfsat-bisection
clairexen [Mon, 25 May 2020 13:50:18 +0000 (15:50 +0200)]
Merge pull request #2015 from boqwxp/qbfsat-bisection

qbfsat: Add an iterative bisection optimization method and make it the default.

4 years agoMerge pull request #2075 from YosysHQ/eddie/xaiger_cleanup
Eddie Hung [Sun, 24 May 2020 17:10:50 +0000 (10:10 -0700)]
Merge pull request #2075 from YosysHQ/eddie/xaiger_cleanup

xaiger: do not derive cells

4 years agoxaiger: add testcase
Eddie Hung [Sun, 24 May 2020 15:48:23 +0000 (08:48 -0700)]
xaiger: add testcase

4 years agoxaiger: do not derive cells
Eddie Hung [Sun, 24 May 2020 15:17:30 +0000 (08:17 -0700)]
xaiger: do not derive cells

4 years agoMerge pull request #2074 from YosysHQ/eddie/ecp5_cleanup
Eddie Hung [Sat, 23 May 2020 16:28:42 +0000 (09:28 -0700)]
Merge pull request #2074 from YosysHQ/eddie/ecp5_cleanup

ecp5: cleanup unused +/ecp5/abc9_model.v

4 years agoecp5: cleanup unused +/ecp5/abc9_model.v
Eddie Hung [Sat, 23 May 2020 15:17:40 +0000 (08:17 -0700)]
ecp5: cleanup unused +/ecp5/abc9_model.v

4 years agoqbfsat: Remove cruft inadvertently left untouched in commit 86fc49a9d60f9ad4cdeec9366...
Alberto Gonzalez [Thu, 21 May 2020 23:20:44 +0000 (23:20 +0000)]
qbfsat: Remove cruft inadvertently left untouched in commit 86fc49a9d60f9ad4cdeec93663e7245a9fdf60c6.

4 years agoqbfsat: Add bisection mode and make it the default.
Alberto Gonzalez [Sat, 25 Apr 2020 04:12:02 +0000 (04:12 +0000)]
qbfsat: Add bisection mode and make it the default.

Also adds `-nooptimize` and reorganizes `qbfsat.cc` a bit.

4 years agoMerge pull request #2072 from whitequark/cxxrtl-dont-purge
whitequark [Fri, 22 May 2020 20:08:39 +0000 (20:08 +0000)]
Merge pull request #2072 from whitequark/cxxrtl-dont-purge

cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level

4 years agocxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level.
whitequark [Fri, 22 May 2020 17:44:05 +0000 (17:44 +0000)]
cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level.

This isn't actually necessary anymore after scheduling was improved,
and `clean -purge` disrupts the mapping between wires in the input
RTLIL netlist and the output CXXRTL code.

4 years agoabc9_ops: update comment
Eddie Hung [Fri, 22 May 2020 04:39:13 +0000 (21:39 -0700)]
abc9_ops: update comment

4 years agoMerge pull request #2057 from YosysHQ/eddie/fix_task_attr
Eddie Hung [Thu, 21 May 2020 18:00:36 +0000 (11:00 -0700)]
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr

verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)

4 years agoUpdate frontends/verilog/verilog_parser.y
Eddie Hung [Thu, 21 May 2020 16:10:56 +0000 (09:10 -0700)]
Update frontends/verilog/verilog_parser.y

Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
4 years agoMerge pull request #2059 from boqwxp/logger-vector-to-dict
Miodrag Milanović [Thu, 21 May 2020 13:36:30 +0000 (15:36 +0200)]
Merge pull request #2059 from boqwxp/logger-vector-to-dict

log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.

4 years agoMerge pull request #2046 from PeterCrozier/trap
N. Engelhardt [Wed, 20 May 2020 08:12:24 +0000 (10:12 +0200)]
Merge pull request #2046 from PeterCrozier/trap

Extend YS_DEBUGTRAP to MacOS.

4 years agoMerge pull request #2054 from boqwxp/fix-smtbmc
N. Engelhardt [Wed, 20 May 2020 06:55:36 +0000 (08:55 +0200)]
Merge pull request #2054 from boqwxp/fix-smtbmc

smtbmc: Fix return status handling.

4 years agokernel: Try an order-independent approach to hashing `dict`.
Alberto Gonzalez [Mon, 18 May 2020 17:10:01 +0000 (17:10 +0000)]
kernel: Try an order-independent approach to hashing `dict`.

Co-Authored-By: David Shah <dave@ds0.me>
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
4 years agosmtbmc: Fix typo in error message.
Alberto Gonzalez [Tue, 19 May 2020 16:13:44 +0000 (16:13 +0000)]
smtbmc: Fix typo in error message.

Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
4 years agoAdd force_downto and force_upto wire attributes.
Marcelina Kościelnicka [Mon, 18 May 2020 16:15:03 +0000 (18:15 +0200)]
Add force_downto and force_upto wire attributes.

Fixes #2058.

4 years agoMerge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
Eddie Hung [Mon, 18 May 2020 15:06:50 +0000 (08:06 -0700)]
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff

abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)

4 years agofirrtl: Accept techmapped cell types in FIRRTL backend.
Alberto Gonzalez [Sun, 17 May 2020 08:44:31 +0000 (08:44 +0000)]
firrtl: Accept techmapped cell types in FIRRTL backend.

4 years agoRevert "Add support for non-power-of-two mem chunks in verific importer"
Claire Wolf [Sun, 17 May 2020 09:31:11 +0000 (11:31 +0200)]
Revert "Add support for non-power-of-two mem chunks in verific importer"

This reverts commit 173aa27ca5ef6e7c0a9277e8da7765adcd63bfe9.

4 years agolog: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning...
Alberto Gonzalez [Thu, 14 May 2020 22:52:07 +0000 (22:52 +0000)]
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.

4 years agoabc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
Eddie Hung [Thu, 14 May 2020 23:44:35 +0000 (16:44 -0700)]
abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_

instead of moving them to $__ prefix

4 years agoverilog: attributes before task enable (but 13 s/r conflicts)
Eddie Hung [Thu, 14 May 2020 23:10:11 +0000 (16:10 -0700)]
verilog: attributes before task enable (but 13 s/r conflicts)

4 years agotests: attributes before task enable
Eddie Hung [Thu, 14 May 2020 23:09:41 +0000 (16:09 -0700)]
tests: attributes before task enable

4 years agoMerge pull request #2055 from YosysHQ/eddie/logger_multiple
Eddie Hung [Thu, 14 May 2020 22:30:08 +0000 (15:30 -0700)]
Merge pull request #2055 from YosysHQ/eddie/logger_multiple

logger: fix for multiple calls with same pattern

4 years agokernel: Ensure `dict` always hashes to the same value given the same contents.
Alberto Gonzalez [Fri, 24 Apr 2020 08:37:16 +0000 (08:37 +0000)]
kernel: Ensure `dict` always hashes to the same value given the same contents.

4 years agokernel: Re-implement `dict` hash code as a `dict` member function instead of a specia...
Alberto Gonzalez [Wed, 22 Apr 2020 22:04:22 +0000 (22:04 +0000)]
kernel: Re-implement `dict` hash code as a `dict` member function instead of a specialized template for `hash_ops`.

4 years agotechmap: Replace naughty `const_cast<>()`s.
Alberto Gonzalez [Tue, 21 Apr 2020 17:47:00 +0000 (17:47 +0000)]
techmap: Replace naughty `const_cast<>()`s.

Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
4 years agotechmap: Replace pseudo-private member usage with the range accessor function and...
Alberto Gonzalez [Tue, 21 Apr 2020 07:51:29 +0000 (07:51 +0000)]
techmap: Replace pseudo-private member usage with the range accessor function and some naughty `const_cast<>()`s.

4 years agotechmap: sort celltypeMap as it determines techmap order
Eddie Hung [Tue, 21 Apr 2020 03:56:38 +0000 (20:56 -0700)]
techmap: sort celltypeMap as it determines techmap order

4 years agoReplace `std::set`s using custom comparators with `pool`.
Alberto Gonzalez [Mon, 20 Apr 2020 22:55:11 +0000 (22:55 +0000)]
Replace `std::set`s using custom comparators with `pool`.

Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
4 years agotechmap: prefix special wires with backslash for use as IdString
Eddie Hung [Mon, 20 Apr 2020 22:50:12 +0000 (15:50 -0700)]
techmap: prefix special wires with backslash for use as IdString

4 years agoFurther clean up `passes/techmap/techmap.cc`.
Alberto Gonzalez [Mon, 20 Apr 2020 21:57:23 +0000 (21:57 +0000)]
Further clean up `passes/techmap/techmap.cc`.

Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
4 years agoUse `emplace()` for more efficient insertion into various `dict`s.
Alberto Gonzalez [Mon, 20 Apr 2020 05:59:00 +0000 (05:59 +0000)]
Use `emplace()` for more efficient insertion into various `dict`s.

4 years agoBuild constant bits directly rather than constructing an object and copying its bits.
Alberto Gonzalez [Mon, 20 Apr 2020 05:10:08 +0000 (05:10 +0000)]
Build constant bits directly rather than constructing an object and copying its bits.

4 years agoReplace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.
Alberto Gonzalez [Mon, 20 Apr 2020 04:46:09 +0000 (04:46 +0000)]
Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.

4 years agoUse `emplace()` rather than `insert()`.
Alberto Gonzalez [Mon, 20 Apr 2020 04:42:19 +0000 (04:42 +0000)]
Use `emplace()` rather than `insert()`.