yosys.git
8 years agoImproved verilog parser errors
Clifford Wolf [Thu, 25 Aug 2016 09:44:25 +0000 (11:44 +0200)]
Improved verilog parser errors

8 years agoMore yosys-smtbmc smtc features
Clifford Wolf [Wed, 24 Aug 2016 21:18:29 +0000 (23:18 +0200)]
More yosys-smtbmc smtc features

8 years agoyosys-smtbmc --smtc -g
Clifford Wolf [Wed, 24 Aug 2016 20:09:50 +0000 (22:09 +0200)]
yosys-smtbmc --smtc -g

8 years agoAdded SV "restrict" keyword
Clifford Wolf [Wed, 24 Aug 2016 13:30:08 +0000 (15:30 +0200)]
Added SV "restrict" keyword

8 years agoMinor yosys-smtbmc bugfix
Clifford Wolf [Mon, 22 Aug 2016 15:45:01 +0000 (17:45 +0200)]
Minor yosys-smtbmc bugfix

8 years agoAdded "yosys-smtbmc --constr"
Clifford Wolf [Mon, 22 Aug 2016 15:27:43 +0000 (17:27 +0200)]
Added "yosys-smtbmc --constr"

8 years agoAdded "yosys-smtbmc --dump-constr"
Clifford Wolf [Mon, 22 Aug 2016 14:48:46 +0000 (16:48 +0200)]
Added "yosys-smtbmc --dump-constr"

8 years agoAdded glob support to all front-ends
Clifford Wolf [Mon, 22 Aug 2016 13:05:57 +0000 (15:05 +0200)]
Added glob support to all front-ends

8 years agoFixed bug with memories that do not have a down-to-zero data width
Clifford Wolf [Mon, 22 Aug 2016 12:27:46 +0000 (14:27 +0200)]
Fixed bug with memories that do not have a down-to-zero data width

8 years agoFixed bug in memory_share for memory ports with different ABITS
Clifford Wolf [Mon, 22 Aug 2016 12:26:33 +0000 (14:26 +0200)]
Fixed bug in memory_share for memory ports with different ABITS

8 years agoyosys-smtbmc: improved --dump-vlogtb handling of memories
Clifford Wolf [Sun, 21 Aug 2016 13:56:22 +0000 (15:56 +0200)]
yosys-smtbmc: improved --dump-vlogtb handling of memories

8 years agoAdded another mem2reg test case
Clifford Wolf [Sun, 21 Aug 2016 11:45:46 +0000 (13:45 +0200)]
Added another mem2reg test case

8 years agoAnother bugfix in mem2reg code
Clifford Wolf [Sun, 21 Aug 2016 11:23:58 +0000 (13:23 +0200)]
Another bugfix in mem2reg code

8 years agoMinor improvements to AstNode::dumpAst() and AstNode::dumpVlog()
Clifford Wolf [Sun, 21 Aug 2016 11:18:09 +0000 (13:18 +0200)]
Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()

8 years agoAdded examples/smtbmc/demo2.v
Clifford Wolf [Sat, 20 Aug 2016 16:44:27 +0000 (18:44 +0200)]
Added examples/smtbmc/demo2.v

8 years agoAdded "yosys-smtbmc --dump-vlogtb"
Clifford Wolf [Sat, 20 Aug 2016 16:43:39 +0000 (18:43 +0200)]
Added "yosys-smtbmc --dump-vlogtb"

8 years agoAdded support for memories to smtio.py
Clifford Wolf [Sat, 20 Aug 2016 16:42:32 +0000 (18:42 +0200)]
Added support for memories to smtio.py

8 years agoDeprecated "write_smt2 -regs" (by default on now), and some other smt2 back-end impro...
Clifford Wolf [Sat, 20 Aug 2016 16:41:57 +0000 (18:41 +0200)]
Deprecated "write_smt2 -regs" (by default on now), and some other smt2 back-end improvements

8 years agoAdded "yosys-smtbmc -g"
Clifford Wolf [Sat, 20 Aug 2016 14:32:50 +0000 (16:32 +0200)]
Added "yosys-smtbmc -g"

8 years agoAdded smtbmc longopt support
Clifford Wolf [Sat, 20 Aug 2016 14:07:59 +0000 (16:07 +0200)]
Added smtbmc longopt support

8 years agoFixed finish_addr handling in $readmemh/$readmemb
Clifford Wolf [Sat, 20 Aug 2016 11:47:46 +0000 (13:47 +0200)]
Fixed finish_addr handling in $readmemh/$readmemb

8 years agoBugfix in partial mem write handling in verilog back-end
Clifford Wolf [Sat, 20 Aug 2016 11:06:06 +0000 (13:06 +0200)]
Bugfix in partial mem write handling in verilog back-end

8 years agoAdded "wreduce -memx"
Clifford Wolf [Sat, 20 Aug 2016 10:52:50 +0000 (12:52 +0200)]
Added "wreduce -memx"

8 years agoAdded memory_memx pass, "memory -memx", and "prep -memx"
Clifford Wolf [Fri, 19 Aug 2016 17:48:26 +0000 (19:48 +0200)]
Added memory_memx pass, "memory -memx", and "prep -memx"

8 years agoOptimize memory address port width in wreduce and memory_collect, not verilog front-end
Clifford Wolf [Fri, 19 Aug 2016 16:38:25 +0000 (18:38 +0200)]
Optimize memory address port width in wreduce and memory_collect, not verilog front-end

8 years agoAdded missing support for mem read enable ports to verilog back-end
Clifford Wolf [Thu, 18 Aug 2016 19:47:02 +0000 (21:47 +0200)]
Added missing support for mem read enable ports to verilog back-end

8 years agoBugfix in test_autotb
Clifford Wolf [Thu, 18 Aug 2016 11:43:12 +0000 (13:43 +0200)]
Bugfix in test_autotb

8 years agoImproved smtbmc vcd generation performance
Clifford Wolf [Thu, 18 Aug 2016 09:17:45 +0000 (11:17 +0200)]
Improved smtbmc vcd generation performance

8 years agoAdded printing of code loc of failed asserts to yosys-smtbmc
Clifford Wolf [Wed, 17 Aug 2016 18:10:02 +0000 (20:10 +0200)]
Added printing of code loc of failed asserts to yosys-smtbmc

8 years agoFixed default build config
Clifford Wolf [Tue, 16 Aug 2016 20:44:38 +0000 (22:44 +0200)]
Fixed default build config

8 years agoMerge pull request #203 from cr1901/master
Clifford Wolf [Tue, 16 Aug 2016 20:41:53 +0000 (22:41 +0200)]
Merge pull request #203 from cr1901/master

Add MSYS2-compatible build.

8 years agoAdd MSYS2-compatible build.
William D. Jones [Tue, 16 Aug 2016 18:41:37 +0000 (14:41 -0400)]
Add MSYS2-compatible build.

8 years agoUse _Exit(0) on win32, always use _Exit(1) in log_error()
Clifford Wolf [Tue, 16 Aug 2016 07:36:49 +0000 (09:36 +0200)]
Use _Exit(0) on win32, always use _Exit(1) in log_error()

8 years agoUpdated ABC to hg rev a86455b00da5
Clifford Wolf [Tue, 16 Aug 2016 07:08:26 +0000 (09:08 +0200)]
Updated ABC to hg rev a86455b00da5

8 years agoFixed use-after-free dict<> usage pattern in hierarchy.cc
Clifford Wolf [Tue, 16 Aug 2016 07:07:13 +0000 (09:07 +0200)]
Fixed use-after-free dict<> usage pattern in hierarchy.cc

8 years agoUpdated ABC to hg rev 760ba358e790
Clifford Wolf [Mon, 15 Aug 2016 22:56:42 +0000 (00:56 +0200)]
Updated ABC to hg rev 760ba358e790

8 years agoABC mxe cross-build fix
Clifford Wolf [Mon, 15 Aug 2016 22:52:10 +0000 (00:52 +0200)]
ABC mxe cross-build fix

8 years agoMinor fixes in show command
Clifford Wolf [Mon, 15 Aug 2016 22:36:24 +0000 (00:36 +0200)]
Minor fixes in show command

8 years agoAdded greenpak4_dffinv
Clifford Wolf [Mon, 15 Aug 2016 07:33:06 +0000 (09:33 +0200)]
Added greenpak4_dffinv

8 years agoFixed upto handling in verilog back-end
Clifford Wolf [Mon, 15 Aug 2016 06:26:20 +0000 (08:26 +0200)]
Fixed upto handling in verilog back-end

8 years agoMerge pull request #200 from azonenberg/master
Clifford Wolf [Sun, 14 Aug 2016 13:49:08 +0000 (15:49 +0200)]
Merge pull request #200 from azonenberg/master

Updates to GP_RCOSC, new GP_DFF*I cells

8 years agogreenpak4: Changed name of inverted output ports for consistency
Andrew Zonenberg [Sun, 14 Aug 2016 07:30:45 +0000 (00:30 -0700)]
greenpak4: Changed name of inverted output ports for consistency

8 years agogreenpak4: Added GP_DFFxI cells
Andrew Zonenberg [Sun, 14 Aug 2016 07:11:44 +0000 (00:11 -0700)]
greenpak4: Added GP_DFFxI cells

8 years agogreenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)
Andrew Zonenberg [Sun, 14 Aug 2016 05:27:58 +0000 (22:27 -0700)]
greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)

8 years agoMerge pull request #198 from whitequark/master
Clifford Wolf [Thu, 11 Aug 2016 09:17:44 +0000 (11:17 +0200)]
Merge pull request #198 from whitequark/master

synth_greenpak4: use attrmvcp to move LOC from wires to cells

8 years agosynth_greenpak4: use attrmvcp to move LOC from wires to cells.
whitequark [Wed, 10 Aug 2016 20:09:35 +0000 (20:09 +0000)]
synth_greenpak4: use attrmvcp to move LOC from wires to cells.

8 years agoOnly allow posedge/negedge with 1 bit wide signals
Clifford Wolf [Wed, 10 Aug 2016 17:32:11 +0000 (19:32 +0200)]
Only allow posedge/negedge with 1 bit wide signals

8 years agoFixed some compiler warnings in attrmap command
Clifford Wolf [Wed, 10 Aug 2016 11:44:08 +0000 (13:44 +0200)]
Fixed some compiler warnings in attrmap command

8 years agoAdded "attrmap" command
Clifford Wolf [Tue, 9 Aug 2016 17:56:55 +0000 (19:56 +0200)]
Added "attrmap" command

8 years agoAdded log_const() API
Clifford Wolf [Tue, 9 Aug 2016 17:56:10 +0000 (19:56 +0200)]
Added log_const() API

8 years agoAdded "attrmvcp" pass
Clifford Wolf [Tue, 9 Aug 2016 09:18:48 +0000 (11:18 +0200)]
Added "attrmvcp" pass

8 years agoUse /proc/self/exe on Cygwin as well.
Yury Gribov [Sun, 7 Aug 2016 20:34:33 +0000 (21:34 +0100)]
Use /proc/self/exe on Cygwin as well.

8 years agoUndo "preserve wire attributes in iopadmap" change (it was OK before)
Clifford Wolf [Mon, 8 Aug 2016 09:47:35 +0000 (11:47 +0200)]
Undo "preserve wire attributes in iopadmap" change (it was OK before)

8 years agoAdded "test_autotb -seed" (and "autotest.sh -S")
Clifford Wolf [Sat, 6 Aug 2016 11:32:29 +0000 (13:32 +0200)]
Added "test_autotb -seed" (and "autotest.sh -S")

8 years agopreserve wire attributes in iopadmap
Clifford Wolf [Sat, 6 Aug 2016 11:24:59 +0000 (13:24 +0200)]
preserve wire attributes in iopadmap

8 years agoFixed bug in parsing real constants
Clifford Wolf [Sat, 6 Aug 2016 11:16:23 +0000 (13:16 +0200)]
Fixed bug in parsing real constants

8 years agoAdded "insbuf" command
Clifford Wolf [Tue, 2 Aug 2016 08:37:19 +0000 (10:37 +0200)]
Added "insbuf" command

8 years agoMerge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Sat, 30 Jul 2016 10:50:39 +0000 (12:50 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys

8 years agoAdded "write_verilog -defparam"
Clifford Wolf [Sat, 30 Jul 2016 10:46:06 +0000 (12:46 +0200)]
Added "write_verilog -defparam"

8 years agoAdded "write_verilog -nodec -nostr"
Clifford Wolf [Sat, 30 Jul 2016 10:38:40 +0000 (12:38 +0200)]
Added "write_verilog -nodec -nostr"

8 years agoAdded $initstate support to smtbmc flow
Clifford Wolf [Wed, 27 Jul 2016 14:11:37 +0000 (16:11 +0200)]
Added $initstate support to smtbmc flow

8 years agoAdded SatGen support for $anyconst
Clifford Wolf [Wed, 27 Jul 2016 13:52:20 +0000 (15:52 +0200)]
Added SatGen support for $anyconst

8 years agoRemoved $predict support from SatGen
Clifford Wolf [Wed, 27 Jul 2016 13:44:11 +0000 (15:44 +0200)]
Removed $predict support from SatGen

8 years agoAdded $anyconst and $aconst
Clifford Wolf [Wed, 27 Jul 2016 13:41:22 +0000 (15:41 +0200)]
Added $anyconst and $aconst

8 years agoAdded "read_verilog -dump_rtlil"
Clifford Wolf [Wed, 27 Jul 2016 13:40:17 +0000 (15:40 +0200)]
Added "read_verilog -dump_rtlil"

8 years agoRenamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
Clifford Wolf [Mon, 25 Jul 2016 14:39:25 +0000 (16:39 +0200)]
Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()

8 years agoFixed a verilog parser memory leak
Clifford Wolf [Mon, 25 Jul 2016 14:37:58 +0000 (16:37 +0200)]
Fixed a verilog parser memory leak

8 years agoFixed parsing of empty positional cell ports
Clifford Wolf [Mon, 25 Jul 2016 10:48:03 +0000 (12:48 +0200)]
Fixed parsing of empty positional cell ports

8 years agoImprovements in CellEdgesDatabase
Clifford Wolf [Sun, 24 Jul 2016 15:21:53 +0000 (17:21 +0200)]
Improvements in CellEdgesDatabase

8 years agoAdded CellEdgesDatabase API
Clifford Wolf [Sun, 24 Jul 2016 11:59:57 +0000 (13:59 +0200)]
Added CellEdgesDatabase API

8 years agoMoved SatHelper::setup_init() code to SatHelper::setup()
Clifford Wolf [Sun, 24 Jul 2016 10:18:39 +0000 (12:18 +0200)]
Moved SatHelper::setup_init() code to SatHelper::setup()

8 years agoAdded $initstate support to "sat" command
Clifford Wolf [Sat, 23 Jul 2016 15:01:03 +0000 (17:01 +0200)]
Added $initstate support to "sat" command

8 years agoNo tristate warning message for "read_verilog -lib"
Clifford Wolf [Sat, 23 Jul 2016 09:56:53 +0000 (11:56 +0200)]
No tristate warning message for "read_verilog -lib"

8 years agoAdded satgen initstate support
Clifford Wolf [Fri, 22 Jul 2016 08:28:45 +0000 (10:28 +0200)]
Added satgen initstate support

8 years agoUsing $initstate in "initial assume" and "initial assert"
Clifford Wolf [Thu, 21 Jul 2016 12:37:28 +0000 (14:37 +0200)]
Using $initstate in "initial assume" and "initial assert"

8 years agoAdded $initstate cell type and vlog function
Clifford Wolf [Thu, 21 Jul 2016 12:23:22 +0000 (14:23 +0200)]
Added $initstate cell type and vlog function

8 years agoAfter reading the SV spec, using non-standard predict() instead of expect()
Clifford Wolf [Thu, 21 Jul 2016 11:34:33 +0000 (13:34 +0200)]
After reading the SV spec, using non-standard predict() instead of expect()

8 years agoAdded basic support for $expect cells
Clifford Wolf [Wed, 13 Jul 2016 14:56:17 +0000 (16:56 +0200)]
Added basic support for $expect cells

8 years agoAdded examples/smtbmc
Clifford Wolf [Wed, 13 Jul 2016 07:49:05 +0000 (09:49 +0200)]
Added examples/smtbmc

8 years agoMerge pull request #191 from whitequark/json-module-attributes
Clifford Wolf [Wed, 13 Jul 2016 07:39:27 +0000 (09:39 +0200)]
Merge pull request #191 from whitequark/json-module-attributes

write_json: also write module attributes

8 years agoMerge pull request #193 from azonenberg/master
Clifford Wolf [Wed, 13 Jul 2016 07:24:31 +0000 (09:24 +0200)]
Merge pull request #193 from azonenberg/master

Removed splitnets in synth_greenpak4, added GP_DAC, refactored GP_BANDGAP

8 years agoMerge https://github.com/cliffordwolf/yosys
Andrew Zonenberg [Tue, 12 Jul 2016 23:12:37 +0000 (16:12 -0700)]
Merge https://github.com/cliffordwolf/yosys

8 years agoMinor bugfix in FSM reset state detection
Clifford Wolf [Tue, 12 Jul 2016 07:46:15 +0000 (09:46 +0200)]
Minor bugfix in FSM reset state detection

8 years agowrite_json: also write module attributes.
whitequark [Tue, 12 Jul 2016 06:32:04 +0000 (06:32 +0000)]
write_json: also write module attributes.

8 years agoAdded GP_DAC cell
Andrew Zonenberg [Tue, 12 Jul 2016 05:45:55 +0000 (22:45 -0700)]
Added GP_DAC cell

8 years agoRemoved VOUT port of GP_BANDGAP
Andrew Zonenberg [Tue, 12 Jul 2016 05:45:42 +0000 (22:45 -0700)]
Removed VOUT port of GP_BANDGAP

8 years agoRemoved splitnets in prep for new gp4par parser
Andrew Zonenberg [Tue, 12 Jul 2016 05:42:25 +0000 (22:42 -0700)]
Removed splitnets in prep for new gp4par parser

8 years agoYosys-smtbmc: Support for hierarchical VCD dumping
Clifford Wolf [Mon, 11 Jul 2016 10:49:33 +0000 (12:49 +0200)]
Yosys-smtbmc: Support for hierarchical VCD dumping

8 years agoMoved smt2 yosys info parsing from smtbmc.py to smtio.py
Clifford Wolf [Mon, 11 Jul 2016 09:49:05 +0000 (11:49 +0200)]
Moved smt2 yosys info parsing from smtbmc.py to smtio.py

8 years agoAdded "prep -auto-top" and "synth -auto-top"
Clifford Wolf [Mon, 11 Jul 2016 09:40:55 +0000 (11:40 +0200)]
Added "prep -auto-top" and "synth -auto-top"

8 years agoMerge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Sun, 10 Jul 2016 16:17:09 +0000 (18:17 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys

8 years agoMerge pull request #189 from whitequark/master
Clifford Wolf [Sun, 10 Jul 2016 16:12:00 +0000 (18:12 +0200)]
Merge pull request #189 from whitequark/master

greenpak4: add GP_COUNT{8,14}_ADV cells

8 years agoSupport for hierarchical designs in smt2 back-end
Clifford Wolf [Sun, 10 Jul 2016 16:11:25 +0000 (18:11 +0200)]
Support for hierarchical designs in smt2 back-end

8 years agogreenpak4: add GP_COUNT{8,14}_ADV cells.
whitequark [Sun, 10 Jul 2016 14:41:34 +0000 (14:41 +0000)]
greenpak4: add GP_COUNT{8,14}_ADV cells.

8 years agoFurther improved fsm_detect output, attempt to detect self-resetting circuits
Clifford Wolf [Sat, 9 Jul 2016 12:02:49 +0000 (14:02 +0200)]
Further improved fsm_detect output, attempt to detect self-resetting circuits

8 years agoAdded printing of some warning messages to fsm_detect
Clifford Wolf [Sat, 9 Jul 2016 11:23:06 +0000 (13:23 +0200)]
Added printing of some warning messages to fsm_detect

8 years agoAdded warning about adding fsm_encoding attributes to wires to manual
Clifford Wolf [Fri, 8 Jul 2016 16:31:31 +0000 (18:31 +0200)]
Added warning about adding fsm_encoding attributes to wires to manual

8 years agoMinor fixes in ice40_ff* passes for sloppy SB_DFF instantiations
Clifford Wolf [Fri, 8 Jul 2016 12:41:36 +0000 (14:41 +0200)]
Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations

8 years agoFixed mem assignment in left-hand-side concatenation
Clifford Wolf [Fri, 8 Jul 2016 12:31:06 +0000 (14:31 +0200)]
Fixed mem assignment in left-hand-side concatenation

8 years agoMerge branch 'eddiehung-vtr'
Clifford Wolf [Fri, 8 Jul 2016 09:56:53 +0000 (11:56 +0200)]
Merge branch 'eddiehung-vtr'