Alberto Gonzalez [Tue, 14 Apr 2020 02:20:59 +0000 (02:20 +0000)]
Simplify `passes/techmap/abc.cc` and remove superfluous `RTLIL::SigSpec` constructions.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
Alberto Gonzalez [Sun, 5 Apr 2020 21:31:18 +0000 (21:31 +0000)]
Clean up pseudo-private member usage and simplify `passes/techmap/abc.cc`.
Eddie Hung [Fri, 3 Apr 2020 23:28:25 +0000 (16:28 -0700)]
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
Eddie Hung [Fri, 3 Apr 2020 21:25:04 +0000 (14:25 -0700)]
cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp
Eddie Hung [Thu, 6 Feb 2020 16:46:38 +0000 (08:46 -0800)]
cmp2lcu: fail if `LUT_WIDTH < 2
Eddie Hung [Thu, 6 Feb 2020 16:46:11 +0000 (08:46 -0800)]
synth: only techmap cmp2{lut,lcu} if -lut
Eddie Hung [Wed, 5 Feb 2020 22:31:51 +0000 (14:31 -0800)]
synth: use +/cmp2lcu.v in generic 'synth' too
Eddie Hung [Tue, 21 Jan 2020 17:14:03 +0000 (09:14 -0800)]
Cleanup +/cmp2lut.v
Eddie Hung [Tue, 21 Jan 2020 01:05:49 +0000 (17:05 -0800)]
synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'
Eddie Hung [Tue, 21 Jan 2020 01:00:35 +0000 (17:00 -0800)]
+/cmp2lcu.v to work efficiently for fully/partially constant inputs
Eddie Hung [Tue, 21 Jan 2020 00:42:17 +0000 (16:42 -0800)]
+/cmp2lcu.v to work efficiently for fully/partially constant inputs
Eddie Hung [Tue, 21 Jan 2020 00:42:08 +0000 (16:42 -0800)]
Refactor +/cmp2lcu.v into recursive techmap
Eddie Hung [Mon, 20 Jan 2020 23:06:50 +0000 (15:06 -0800)]
Cleanup
Eddie Hung [Mon, 20 Jan 2020 20:52:47 +0000 (12:52 -0800)]
Cleanup cmp2lcu.v
Eddie Hung [Fri, 17 Jan 2020 18:51:27 +0000 (10:51 -0800)]
techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu
Eddie Hung [Fri, 17 Jan 2020 18:21:22 +0000 (10:21 -0800)]
cmp2lut: comment out unused since
362f4f9
Eddie Hung [Thu, 2 Apr 2020 19:27:10 +0000 (12:27 -0700)]
Merge pull request #1853 from YosysHQ/eddie/fix_dynslice
ast: cap dynamic range select to size of signal, suppresses warnings
Eddie Hung [Thu, 2 Apr 2020 18:47:25 +0000 (11:47 -0700)]
Merge pull request #1767 from YosysHQ/eddie/idstrings
IdString: use more ID::*, make them easier to use, speed up IdString::in()
Eddie Hung [Thu, 2 Apr 2020 16:51:32 +0000 (09:51 -0700)]
kernel: big fat patch to use more ID::*, otherwise ID(*)
Marcin Kościelnicki [Thu, 26 Mar 2020 20:15:28 +0000 (21:15 +0100)]
simcells.v: Generate the fine FF cell types by a python script.
This makes adding more FF types in the future much more manageable.
Fixes #1824.
Claire Wolf [Thu, 2 Apr 2020 16:15:15 +0000 (18:15 +0200)]
Merge pull request #1846 from dh73/ast_fe
Adding error message for when size (width) of number literal is zero
Marcin Kościelnicki [Mon, 30 Mar 2020 13:35:31 +0000 (15:35 +0200)]
iopadmap: Fix z assignment to inout port
Fixes #1841.
Claire Wolf [Thu, 2 Apr 2020 16:14:34 +0000 (18:14 +0200)]
Merge pull request #1842 from YosysHQ/mwk/fix-deminout-xz
deminout: prevent any constant assignment from demoting to input
Eddie Hung [Wed, 1 Apr 2020 21:10:24 +0000 (14:10 -0700)]
kernel: IdString::in(const IdString &) as per @Tjoppen
Eddie Hung [Mon, 16 Mar 2020 19:58:55 +0000 (12:58 -0700)]
kernel: fix formatting (thanks @boqwxp)
Eddie Hung [Sun, 15 Mar 2020 16:47:20 +0000 (09:47 -0700)]
kernel: use C++11 fold hack to prevent recursion
Eddie Hung [Sun, 15 Mar 2020 16:11:44 +0000 (09:11 -0700)]
Revert "kernel: IdString:in() to use perfect forwarding"
This reverts commit
7b2a85aedf24affc2e1202c78e70e6a317f5bf29.
Eddie Hung [Sun, 15 Mar 2020 16:09:35 +0000 (09:09 -0700)]
Update backends/btor/btor.cc; credit @boqwxp
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
Eddie Hung [Thu, 12 Mar 2020 21:42:07 +0000 (14:42 -0700)]
kernel: separate IdString::put_reference() out to help inlining
Eddie Hung [Thu, 12 Mar 2020 21:41:27 +0000 (14:41 -0700)]
kernel: IdString:in() to use perfect forwarding
Eddie Hung [Thu, 12 Mar 2020 19:57:01 +0000 (12:57 -0700)]
kernel: use more ID::*
Eddie Hung [Thu, 12 Mar 2020 19:54:30 +0000 (12:54 -0700)]
kernel: Use constids.inc for global/constant IdStrings
Eddie Hung [Thu, 2 Apr 2020 14:13:33 +0000 (07:13 -0700)]
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
kernel: speedup by using more pass-by-const-ref
Claire Wolf [Thu, 2 Apr 2020 13:40:00 +0000 (15:40 +0200)]
Bump YOSYS_VER
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Thu, 2 Apr 2020 13:38:47 +0000 (15:38 +0200)]
Merge pull request #1770 from YosysHQ/claire/btor_symbols
Improve write_btor symbol handling
Claire Wolf [Thu, 2 Apr 2020 13:38:27 +0000 (15:38 +0200)]
Merge pull request #1765 from YosysHQ/claire/btor_info
Add info-file and cover features to write_btor
Claire Wolf [Thu, 2 Apr 2020 12:31:33 +0000 (14:31 +0200)]
Merge pull request #1777 from YosysHQ/claire/manyhot
Using LFSR counter for ezSAT::manyhot()
Claire Wolf [Thu, 2 Apr 2020 10:22:28 +0000 (12:22 +0200)]
Improve ezsat onehot encoding scheme
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Tue, 17 Mar 2020 13:15:08 +0000 (14:15 +0100)]
Using LFSR counter for ezSAT::manyhot()
The only user of this API right now is the puzzle3d benchmark and
it sees a slight reduction in CNF size from this, but the performance
difference is within the noise of measurement on my system.
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Eddie Hung [Wed, 1 Apr 2020 21:17:45 +0000 (14:17 -0700)]
Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup
kernel: share a single CellTypes within a pass
Eddie Hung [Wed, 1 Apr 2020 21:17:01 +0000 (14:17 -0700)]
Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor
opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
Eddie Hung [Wed, 1 Apr 2020 21:11:09 +0000 (14:11 -0700)]
Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu
opt_expr: improve performance on $alu and $sub
David Shah [Wed, 1 Apr 2020 19:55:24 +0000 (20:55 +0100)]
Merge pull request #1844 from YosysHQ/dave/gen-source-loc
verilog: Add location info for generate constructs
Eddie Hung [Wed, 1 Apr 2020 18:18:38 +0000 (11:18 -0700)]
Merge pull request #1852 from boqwxp/cleanup_synth_ice40
Fix indentation in `techlibs/ice40/synth_ice40.cc`.
David Shah [Mon, 30 Mar 2020 20:14:51 +0000 (21:14 +0100)]
verilog: Add location info for generate constructs
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Wed, 1 Apr 2020 16:59:23 +0000 (09:59 -0700)]
ast: cap dynamic range select to size of signal, suppresses warnings
Eddie Hung [Wed, 1 Apr 2020 16:35:35 +0000 (09:35 -0700)]
Merge pull request #1849 from boqwxp/cleanup_kernel_yosys
Clean up pseudo-private member usage in `kernel/yosys.cc`.
Eddie Hung [Wed, 1 Apr 2020 16:34:02 +0000 (09:34 -0700)]
Merge pull request #1850 from boqwxp/cleanup_backends
Cleanup pseudo-private member usage and outdated `RTLIL::id2cstr()` in backends
Alberto Gonzalez [Wed, 1 Apr 2020 16:29:56 +0000 (16:29 +0000)]
Fix indentation in `techlibs/ice40/synth_ice40.cc`.
Alberto Gonzalez [Wed, 1 Apr 2020 06:53:28 +0000 (06:53 +0000)]
Update `RTLIL::id2cstr()` usage to `log_id`.
Claire Wolf [Wed, 1 Apr 2020 06:38:14 +0000 (08:38 +0200)]
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
ast: simplify to fully populate dynamic slicing case transformation
Alberto Gonzalez [Wed, 1 Apr 2020 06:32:09 +0000 (06:32 +0000)]
Clean up pseudo-private member usage in `backends/intersynth/intersynth.cc`.
Alberto Gonzalez [Wed, 1 Apr 2020 05:50:48 +0000 (05:50 +0000)]
Clean up pseudo-private member usage in `backends/blif/blif.cc`.
Alberto Gonzalez [Wed, 1 Apr 2020 05:25:10 +0000 (05:25 +0000)]
Clean up pseudo-private member usage in `backends/verilog/verilog_backend.cc`.
Alberto Gonzalez [Wed, 1 Apr 2020 04:56:52 +0000 (04:56 +0000)]
Clean up pseudo-private member usage in `backends/spice/spice.cc`.
Alberto Gonzalez [Wed, 1 Apr 2020 04:37:07 +0000 (04:37 +0000)]
Clean up pseudo-private member usage in `backends/edif/edif.cc`.
Alberto Gonzalez [Wed, 1 Apr 2020 03:08:39 +0000 (03:08 +0000)]
Clean up pseudo-private member usage in `backends/ilang/ilang_backend.cc`.
Alberto Gonzalez [Wed, 1 Apr 2020 02:53:56 +0000 (02:53 +0000)]
Clean up pseudo-private member usage in `kernel/yosys.cc`.
Eddie Hung [Tue, 31 Mar 2020 21:50:32 +0000 (14:50 -0700)]
Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup
opt_merge: speedup
Eddie Hung [Tue, 31 Mar 2020 18:52:14 +0000 (11:52 -0700)]
ast: simplify to fully populate dynamic slicing case transformation
Eddie Hung [Tue, 31 Mar 2020 18:51:31 +0000 (11:51 -0700)]
Add dynamic slicing Verilog testcase
Diego H [Tue, 31 Mar 2020 18:01:29 +0000 (12:01 -0600)]
Replacing log_error for log_file_error due consistency
Diego H [Mon, 30 Mar 2020 23:18:13 +0000 (17:18 -0600)]
Adding error message for when size (width) of number literal is zero
Eddie Hung [Mon, 30 Mar 2020 20:06:10 +0000 (13:06 -0700)]
Merge pull request #1783 from boqwxp/astcc_cleanup
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
Eddie Hung [Mon, 30 Mar 2020 20:05:12 +0000 (13:05 -0700)]
Merge pull request #1835 from boqwxp/cleanup_sat_expose
Clean up pseudo-private member usage in `passes/sat/expose.cc`.
Eddie Hung [Mon, 30 Mar 2020 18:56:17 +0000 (11:56 -0700)]
Merge pull request #1832 from boqwxp/cleanup_passes_cmds_design
Clean up pseudo-private member usage in `passes/cmds/design.cc`.
Eddie Hung [Mon, 30 Mar 2020 18:37:51 +0000 (11:37 -0700)]
Merge pull request #1786 from boqwxp/hierarchycc_cleanup
Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.
Alberto Gonzalez [Mon, 30 Mar 2020 18:08:25 +0000 (18:08 +0000)]
Add explanatory comment about inefficient wire removal and remove superfluous call to `fixup_ports()`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
Eddie Hung [Mon, 30 Mar 2020 18:13:53 +0000 (11:13 -0700)]
Merge pull request #1831 from boqwxp/cleanup_sat_eval
Clean up pseudo-private member usage in `passes/sat/eval.cc`.
Eddie Hung [Mon, 30 Mar 2020 18:13:06 +0000 (11:13 -0700)]
Merge pull request #1833 from boqwxp/cleanup_sat_freduce
Clean up pseudo-private member usage in `passes/sat/freduce.cc`.
Alberto Gonzalez [Mon, 30 Mar 2020 18:00:19 +0000 (18:00 +0000)]
Remove unused function parameter.
Alberto Gonzalez [Mon, 30 Mar 2020 17:56:07 +0000 (17:56 +0000)]
Simplify iterating over selected modules or cells.
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
Alberto Gonzalez [Mon, 30 Mar 2020 16:50:36 +0000 (16:50 +0000)]
Replace `RTLIL::id2cstr()` with `log_id()`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
Alberto Gonzalez [Mon, 30 Mar 2020 16:43:54 +0000 (16:43 +0000)]
Fix double deletion in `passes/hierarchy/hierarchy.cc`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
Alberto Gonzalez [Mon, 30 Mar 2020 16:38:35 +0000 (16:38 +0000)]
Further clean up `passes/sat/eval.cc`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
Alberto Gonzalez [Mon, 30 Mar 2020 16:25:30 +0000 (16:25 +0000)]
Further clean up `passes/sat/freduce.cc`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
Alberto Gonzalez [Mon, 30 Mar 2020 16:16:16 +0000 (16:16 +0000)]
Clean up more in `passes/sat/expose.cc`.
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
Eddie Hung [Mon, 30 Mar 2020 15:35:40 +0000 (08:35 -0700)]
memory_share: fix stray brace
Eddie Hung [Mon, 30 Mar 2020 15:22:12 +0000 (08:22 -0700)]
Code review fixes
Eddie Hung [Mon, 30 Mar 2020 15:19:56 +0000 (08:19 -0700)]
Apply suggestions from code review
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
Marcin Kościelnicki [Mon, 30 Mar 2020 13:02:24 +0000 (15:02 +0200)]
deminout: prevent any constant assignment from demoting to input
Before this patch,
```
module top(inout io);
assign io = 1'bx;
endmodule
```
would have the `io` pin demoted to input (same happens for `1'bz`,
but not for `1'b0` or `1'b1`), resulting in check failures later on.
Part of fix for #1841.
N. Engelhardt [Mon, 30 Mar 2020 11:55:39 +0000 (13:55 +0200)]
Merge pull request #1811 from PeterCrozier/typedef_scope
Support module/package/interface/block scope for typedef names.
N. Engelhardt [Mon, 30 Mar 2020 11:51:12 +0000 (13:51 +0200)]
Merge pull request #1778 from rswarbrick/sv-defines
Add support for SystemVerilog-style `define to Verilog frontend
Miodrag Milanovic [Sat, 28 Mar 2020 08:49:08 +0000 (09:49 +0100)]
Explicit include of csignal
Miodrag Milanovic [Sat, 28 Mar 2020 08:09:11 +0000 (09:09 +0100)]
windows - there are no stopping signals
Alberto Gonzalez [Sat, 28 Mar 2020 06:18:09 +0000 (06:18 +0000)]
Clean up pseudo-private member usage in `passes/sat/expose.cc`.
Alberto Gonzalez [Sat, 28 Mar 2020 06:08:23 +0000 (06:08 +0000)]
Clean up pseudo-private member usage in `passes/sat/freduce.cc`.
Alberto Gonzalez [Sat, 28 Mar 2020 04:45:50 +0000 (04:45 +0000)]
Clean up pseudo-private member usage in `passes/cmds/design.cc`.
Alberto Gonzalez [Sat, 28 Mar 2020 03:11:23 +0000 (03:11 +0000)]
Clean up pseudo-private member usage in `passes/sat/eval.cc`.
Eddie Hung [Fri, 27 Mar 2020 19:21:09 +0000 (12:21 -0700)]
kernel: pass-by-value into Design::scratchpad_set_string() too
Claire Wolf [Fri, 27 Mar 2020 16:28:26 +0000 (17:28 +0100)]
Merge pull request #1607 from whitequark/simplify-simplify-meminit
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
Peter Crozier [Fri, 27 Mar 2020 16:21:45 +0000 (16:21 +0000)]
Inline productions to follow house style.
Rupert Swarbrick [Tue, 17 Mar 2020 09:34:31 +0000 (09:34 +0000)]
Add support for SystemVerilog-style `define to Verilog frontend
This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
Claire Wolf [Fri, 27 Mar 2020 15:48:38 +0000 (16:48 +0100)]
Merge pull request #1815 from boqwxp/fix-ef-optimize
Fix solver output parsing for exists-forall optimization
Alberto Gonzalez [Fri, 27 Mar 2020 09:46:40 +0000 (09:46 +0000)]
Revert over-aggressive change to a more modest cleanup.
Eddie Hung [Thu, 26 Mar 2020 23:21:30 +0000 (16:21 -0700)]
kernel: const Wire* overload -> Wire* !!!
Alberto Gonzalez [Thu, 26 Mar 2020 21:23:07 +0000 (21:23 +0000)]
Do not change solver output parsing for non-exists-forall problems.
Eddie Hung [Thu, 26 Mar 2020 22:05:45 +0000 (15:05 -0700)]
kernel: clear some more ShareWorker state
Eddie Hung [Thu, 26 Mar 2020 21:33:06 +0000 (14:33 -0700)]
kernel: Cell::set{Port,Param}() to pass by value, but use std::move
Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
Claire Wolf [Thu, 26 Mar 2020 18:03:37 +0000 (19:03 +0100)]
Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix
techmap: Fix cell names with _TECHMAP_REPLACE_.*