microwatt.git
4 years agoMerge pull request #137 from antonblanchard/hello-world
Anton Blanchard [Sun, 19 Jan 2020 07:40:34 +0000 (18:40 +1100)]
Merge pull request #137 from antonblanchard/hello-world

hello_world updates

4 years agohello_world updates
Anton Blanchard [Sun, 19 Jan 2020 05:15:22 +0000 (16:15 +1100)]
hello_world updates

Shrink hello_world a bit (from 12kB to 8kB).
Include the built images
Add 0x10 and 0x100 entry points

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoMerge pull request #133 from antonblanchard/ghdl-synth
Anton Blanchard [Sat, 11 Jan 2020 11:40:44 +0000 (22:40 +1100)]
Merge pull request #133 from antonblanchard/ghdl-synth

Ghdl synth

4 years agoMerge pull request #132 from antonblanchard/bin2hex-move
Anton Blanchard [Sat, 11 Jan 2020 11:07:42 +0000 (22:07 +1100)]
Merge pull request #132 from antonblanchard/bin2hex-move

Move bin2hex.py to scripts/

4 years agoMove bin2hex.py to scripts/
Anton Blanchard [Sat, 11 Jan 2020 10:31:48 +0000 (21:31 +1100)]
Move bin2hex.py to scripts/

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoFix a ghdlsynth issue in fast_spr_num
Anton Blanchard [Sat, 11 Jan 2020 06:13:23 +0000 (17:13 +1100)]
Fix a ghdlsynth issue in fast_spr_num

I've submitted a bug report for this, but we can work around it easily
for now.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoFix a ghdlsynth issue in icache
Anton Blanchard [Sat, 11 Jan 2020 03:49:06 +0000 (14:49 +1100)]
Fix a ghdlsynth issue in icache

ghdlsynth doesn't like the debug statement, so wrap it in a generate.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoRemoved unused core_terminated signal
Anton Blanchard [Sat, 11 Jan 2020 03:43:50 +0000 (14:43 +1100)]
Removed unused core_terminated signal

Right now it's unused. We can add it back when we add an LED to signify
the core has terminated.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoFix some ghdlsynth issues with fpga_bram
Anton Blanchard [Sat, 11 Jan 2020 03:34:25 +0000 (14:34 +1100)]
Fix some ghdlsynth issues with fpga_bram

Use to_integer() instead of conv_integer().

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoFix ghdlsynth issue in register file
Anton Blanchard [Sat, 11 Jan 2020 03:29:39 +0000 (14:29 +1100)]
Fix ghdlsynth issue in register file

We need to drive sim_dump_done to keep ghdlsynth happy.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoRemove unused signal
Anton Blanchard [Sat, 11 Jan 2020 03:28:20 +0000 (14:28 +1100)]
Remove unused signal

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoFix a ghdysynth inferred latch error in writeback
Anton Blanchard [Sat, 11 Jan 2020 03:20:35 +0000 (14:20 +1100)]
Fix a ghdysynth inferred latch error in writeback

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoFix a ghdysynth inferred latch error in execute
Anton Blanchard [Sat, 11 Jan 2020 02:24:14 +0000 (13:24 +1100)]
Fix a ghdysynth inferred latch error in execute

It should never happen in practise, but ghdlsynth is complaining about
an inferred latch here. Fix it

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoMerge pull request #131 from antonblanchard/new-tests
Anton Blanchard [Sat, 11 Jan 2020 01:32:57 +0000 (12:32 +1100)]
Merge pull request #131 from antonblanchard/new-tests

Dump CTR, LR and CR on sim termination, and update our tests

4 years agoUpper 32 bits of XER should read as 0s
Anton Blanchard [Sat, 11 Jan 2020 01:16:21 +0000 (12:16 +1100)]
Upper 32 bits of XER should read as 0s

From the architecture:

  bits 0:31 and 35:43 are treated as reserved and return 0s when read
  using mfxer

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoDump CTR, LR and CR on sim termination, and update our tests
Anton Blanchard [Wed, 11 Dec 2019 01:24:46 +0000 (12:24 +1100)]
Dump CTR, LR and CR on sim termination, and update our tests

Right now our test cases fold the SPRs into the GPRs. That makes
debugging fails more difficult than it needs to be, so print
out the CTR, LR and CR.

We still need to print the XER, but that is in two spots in microwatt
and will take some more work.

This also adds many instructions to the tests that we have added
lately including overflow instructions, CR logicals and mt/mfxer.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoMerge pull request #127 from tomtor/CR-PR
Anton Blanchard [Fri, 10 Jan 2020 23:10:13 +0000 (10:10 +1100)]
Merge pull request #127 from tomtor/CR-PR

Implement CRNOR and friends

4 years agoMerge pull request #130 from antonblanchard/build-fix
Anton Blanchard [Fri, 10 Jan 2020 22:02:43 +0000 (09:02 +1100)]
Merge pull request #130 from antonblanchard/build-fix

control: Fix build issue with Fedora 31 version of GHDL

4 years agoMerge pull request #129 from antonblanchard/update-micropython
Anton Blanchard [Fri, 10 Jan 2020 20:35:37 +0000 (07:35 +1100)]
Merge pull request #129 from antonblanchard/update-micropython

Point to upstream micropython

4 years agoPoint to upstream micropython
Anton Blanchard [Fri, 10 Jan 2020 20:20:21 +0000 (07:20 +1100)]
Point to upstream micropython

Our changes are now merged upstream, so point there instead.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoImplement CRNOR and friends
Tom Vijlbrief [Fri, 3 Jan 2020 14:25:00 +0000 (15:25 +0100)]
Implement CRNOR and friends

Signed-off-by: Tom Vijlbrief <tvijlbrief@gmail.com>
4 years agoMerge pull request #126 from sharkcz/docs
Anton Blanchard [Sat, 4 Jan 2020 06:05:37 +0000 (17:05 +1100)]
Merge pull request #126 from sharkcz/docs

document packaged fusesoc for Fedora users

4 years agodocument packaged fusesoc for Fedora users
Dan Horák [Fri, 3 Jan 2020 14:09:27 +0000 (15:09 +0100)]
document packaged fusesoc for Fedora users

Signed-off-by: Dan Horák <dan@danny.cz>
4 years agocontrol: Fix build issue with Fedora 31 version of GHDL
Anton Blanchard [Wed, 11 Dec 2019 01:02:06 +0000 (12:02 +1100)]
control: Fix build issue with Fedora 31 version of GHDL

I'm hitting an issue with the Fedora 31 version of GHDL that
appears to be fixed upstream:

control.vhdl:105:39:error: actual expression must be globally static

Add a signal to get rid of error.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoMerge pull request #122 from paulusmack/benh-sprs
Anton Blanchard [Mon, 9 Dec 2019 11:36:29 +0000 (22:36 +1100)]
Merge pull request #122 from paulusmack/benh-sprs

Benh sprs

4 years agoMerge pull request #123 from antonblanchard/spi-conf
Anton Blanchard [Mon, 9 Dec 2019 09:35:24 +0000 (20:35 +1100)]
Merge pull request #123 from antonblanchard/spi-conf

Add SPI configuration to Xilinx constraint files

4 years agoAdd SPI configuration to Xilinx constraint files
Anton Blanchard [Mon, 9 Dec 2019 05:12:37 +0000 (16:12 +1100)]
Add SPI configuration to Xilinx constraint files

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agodecode2: Minor cleanup
Paul Mackerras [Thu, 5 Dec 2019 01:42:31 +0000 (12:42 +1100)]
decode2: Minor cleanup

Remove unused variable is_reg in decode_input_reg_a.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agosprs: Store common SPRs in register file
Benjamin Herrenschmidt [Thu, 31 Oct 2019 02:48:43 +0000 (13:48 +1100)]
sprs: Store common SPRs in register file

This stores the most common SPRs in the register file.

This includes CTR and LR and a not yet final list of others.

The register file is set to 64 entries for now. Specific types
are defined that can represent a GPR index (gpr_index_t) or
a GPR/SPR index (gspr_index_t) along with conversion functions
between the two.

On order to deal with some forms of branch updating both LR and
CTR, we introduced a delayed update of LR after a branch link.

Note: We currently stall the pipeline on such a delayed branch,
but we could avoid stalling fetch in that specific case as we
know we have a branch delay. We could also limit that to the
specific case where we need to update both CTR and LR.

This allows us to make bcreg, mtspr and mfspr pipelined. decode1
will automatically force the single issue flag on mfspr/mtspr to
a "slow" SPR.

[paulus@ozlabs.org - fix direction of decode2.stall_in]

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agospr: Add translation from SPR to special GPR number
Benjamin Herrenschmidt [Thu, 31 Oct 2019 01:09:14 +0000 (12:09 +1100)]
spr: Add translation from SPR to special GPR number

We will want to store some SPRs in the register file using
a set of "extra" registers. This provides a function for
doing the translation along with some SPR definitions.

This isn't used yet

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agodivider: Fix overflow calculation
Paul Mackerras [Sat, 7 Dec 2019 04:26:25 +0000 (15:26 +1100)]
divider: Fix overflow calculation

We were signalling overflow when neg_result=1 but the result was zero.
Fix this.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agodecode1: Add OE=1 forms of add/sub, mul and div instructions
Paul Mackerras [Thu, 5 Dec 2019 21:25:28 +0000 (08:25 +1100)]
decode1: Add OE=1 forms of add/sub, mul and div instructions

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agoexecute: Copy XER[SO] to CR for cmp[i] and cmpl[i] instructions
Paul Mackerras [Sat, 7 Dec 2019 03:31:33 +0000 (14:31 +1100)]
execute: Copy XER[SO] to CR for cmp[i] and cmpl[i] instructions

We were copying in XER[SO] for the dot-form instructions but not the
explicit compare instructions.  Fix this.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agoAdd basic XER support
Benjamin Herrenschmidt [Wed, 30 Oct 2019 02:53:23 +0000 (13:53 +1100)]
Add basic XER support

The carry is currently internal to execute1. We don't handle any of
the other XER fields.

This creates type called "xer_common_t" that contains the commonly
used XER bits (CA, CA32, SO, OV, OV32).

The value is stored in the CR file (though it could be a separate
module). The rest of the bits will be implemented as a separate
SPR and the two parts reconciled in mfspr/mtspr in latter commits.

We always read XER in decode2 (there is little point not to)
and send it down all pipeline branches as it will be needed in
writeback for all type of instructions when CR0:SO needs to be
updated (such forms exist for all pipeline branches even if we don't
yet implement them).

To avoid having to track XER hazards, we forward it back in EX1. This
assumes that other pipeline branches that can modify it (mult and div)
are running single issue for now.

One additional hazard to beware of is an XER:SO modifying instruction
in EX1 followed immediately by a store conditional. Due to our writeback
latency, the store will go down the LSU with the previous XER value,
thus the stcx. will set CR0:SO using an obsolete SO value.

I doubt there exist any code relying on this behaviour being correct
but we should account for it regardless, possibly by ensuring that
stcx. remain single issue initially, or later by adding some minimal
tracking or moving the LSU into the same pipeline as execute.

Missing some obscure XER affecting instructions like addex or mcrxrx.

[paulus@ozlabs.org - fix CA32 and OV32 for OP_ADD, fix order of
 arguments to set_ov]

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agodecode1: Mark ALU ops using carry as pipelined
Benjamin Herrenschmidt [Thu, 14 Nov 2019 04:25:28 +0000 (15:25 +1100)]
decode1: Mark ALU ops using carry as pipelined

There is no reason not to that I can think of

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agocr_file: Check write_cr_enable
Benjamin Herrenschmidt [Wed, 30 Oct 2019 02:26:43 +0000 (13:26 +1100)]
cr_file: Check write_cr_enable

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agoMerge pull request #120 from antonblanchard/spr-decode-cleanup
Anton Blanchard [Mon, 18 Nov 2019 03:07:16 +0000 (14:07 +1100)]
Merge pull request #120 from antonblanchard/spr-decode-cleanup

spr: Cleanup decoding of SPR numbers

4 years agoMerge pull request #119 from antonblanchard/reduce-pipe-depth
Anton Blanchard [Mon, 18 Nov 2019 03:05:48 +0000 (14:05 +1100)]
Merge pull request #119 from antonblanchard/reduce-pipe-depth

control: Reduce pipeline depth to 1

4 years agoMerge pull request #118 from antonblanchard/bus-pipeline
Anton Blanchard [Fri, 15 Nov 2019 05:02:57 +0000 (16:02 +1100)]
Merge pull request #118 from antonblanchard/bus-pipeline

Bus pipeline

4 years agocontrol: Reduce pipeline depth to 1
Benjamin Herrenschmidt [Thu, 31 Oct 2019 08:43:58 +0000 (19:43 +1100)]
control: Reduce pipeline depth to 1

To match our one stage execute.

This might change back if we end up adding 2 stages to match the
LSU, but in that case we'll want forwards as well.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agospr: Cleanup decoding of SPR numbers
Benjamin Herrenschmidt [Thu, 31 Oct 2019 00:42:10 +0000 (11:42 +1100)]
spr: Cleanup decoding of SPR numbers

Use a function to obtain the integer number and use constants
with the architected numbers. Replace std_match with a case
statement.

This also has the side effect of returning 0 instead of some
random previous result on mfspr of an unknown SPR.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agowb_arbiter: Early master selection
Benjamin Herrenschmidt [Wed, 23 Oct 2019 04:06:39 +0000 (15:06 +1100)]
wb_arbiter: Early master selection

This flips the arbiter muxes on the same cycle as a new request
comes in, thus avoiding a cycle latency.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agowb_arbiter: Make arbiter size parametric
Benjamin Herrenschmidt [Wed, 23 Oct 2019 03:28:12 +0000 (14:28 +1100)]
wb_arbiter: Make arbiter size parametric

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agowb_arbiter: Avoid IDLE cycle when not changing master
Benjamin Herrenschmidt [Wed, 23 Oct 2019 03:01:48 +0000 (14:01 +1100)]
wb_arbiter: Avoid IDLE cycle when not changing master

Consecutive accesses from the same master shouldn't need an IDLE
cycle. Completely remove the IDLE state and switch master when
the bus is idle, but stay on the last selected one between cycles.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoram: Ack stores early
Benjamin Herrenschmidt [Wed, 23 Oct 2019 03:00:30 +0000 (14:00 +1100)]
ram: Ack stores early

Stores only need a single cycle, so we can ack them early if there
isn't an older ack already in the pipeline

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoram: Rework main RAM interface
Benjamin Herrenschmidt [Wed, 23 Oct 2019 01:08:55 +0000 (12:08 +1100)]
ram: Rework main RAM interface

This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoMove log2/ispow2 to a utils package
Benjamin Herrenschmidt [Tue, 22 Oct 2019 23:52:37 +0000 (10:52 +1100)]
Move log2/ispow2 to a utils package

(Out of icache and dcache)

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoram: Add block RAM pipelining
Benjamin Herrenschmidt [Tue, 22 Oct 2019 05:05:18 +0000 (16:05 +1100)]
ram: Add block RAM pipelining

This adds an output buffer to help with timing and allows the BRAMs
to actually pipeline.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agodecode: Reformat decode_types.vhdl
Benjamin Herrenschmidt [Mon, 21 Oct 2019 11:57:51 +0000 (22:57 +1100)]
decode: Reformat decode_types.vhdl

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoAdd option to not flatten hierarchy
Benjamin Herrenschmidt [Mon, 21 Oct 2019 04:15:07 +0000 (15:15 +1100)]
Add option to not flatten hierarchy

Vivado by default tries to flatten the module hierarchy to improve
placement and timing. However this makes debugging timing issues
really hard as the net names in the timing report can be pretty
bogus.

This adds a generic that can be used to control attributes to stop
vivado from flattening the main core components. The resulting design
will have worst timing overall but it will be easier to understand
what the worst timing path are and address them.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agowriteback: Slightly improve timing
Benjamin Herrenschmidt [Mon, 21 Oct 2019 04:11:47 +0000 (15:11 +1100)]
writeback: Slightly improve timing

The CR update currently depends on the complete data formatting
mux chain. This makes it source its inputs from a bit earlier in
the chian, thus improving timing a bit

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agosimple_ram: Turn on pipelining
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:34:48 +0000 (10:34 +1100)]
simple_ram: Turn on pipelining

With a 1 cycle delay

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agowb_debug: Add wishbone pipelining support
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:33:31 +0000 (10:33 +1100)]
wb_debug: Add wishbone pipelining support

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoicache: Add wishbone pipelining support
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:33:04 +0000 (10:33 +1100)]
icache: Add wishbone pipelining support

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agodcache: Add wishbone pipelining support
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:32:46 +0000 (10:32 +1100)]
dcache: Add wishbone pipelining support

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agofpga/bram: Generate stall signal
Benjamin Herrenschmidt [Sat, 19 Oct 2019 10:22:33 +0000 (21:22 +1100)]
fpga/bram: Generate stall signal

This doesn't yet pipeline the block RAM, just generate a valid stall
signal so it's compatible with a pipelined master

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agosimple_ram: Add pipelining support
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:30:39 +0000 (10:30 +1100)]
simple_ram: Add pipelining support

The generic PIPELINE_DEPTH can be set to 0 to keep it operating
as a non-pipelined slave, or a larger value indicating
the amount of extra cycles between requests and acks.

It will always generate a valid stall signal, so it can be used
in either mode with a pipelined master (but only in non-pipelined
mode with a non-pipelined master).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agointercon: Generate stall signals for non-pipelined slaves
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:27:56 +0000 (10:27 +1100)]
intercon: Generate stall signals for non-pipelined slaves

So far the UART and the "miss" case. Memory will be
pipelined

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agowb_arbiter: Forward stall signals
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:27:02 +0000 (10:27 +1100)]
wb_arbiter: Forward stall signals

They are set to '1' for non-selected devices

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoicache_tb: Initialize stop_mark
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:26:09 +0000 (10:26 +1100)]
icache_tb: Initialize stop_mark

Too much red in gtkwave..

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agowishbone: Add stall signal
Benjamin Herrenschmidt [Thu, 17 Oct 2019 09:07:18 +0000 (20:07 +1100)]
wishbone: Add stall signal

Pipelined wishbone needs it

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agopp_uart: reformat
Benjamin Herrenschmidt [Fri, 18 Oct 2019 22:21:42 +0000 (09:21 +1100)]
pp_uart: reformat

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoMerge pull request #115 from antonblanchard/reduce-wishbone
Anton Blanchard [Fri, 25 Oct 2019 06:10:01 +0000 (17:10 +1100)]
Merge pull request #115 from antonblanchard/reduce-wishbone

Reduce wishbone

5 years agoMerge pull request #113 from mikey/exec-sim-remove
Anton Blanchard [Fri, 25 Oct 2019 04:52:24 +0000 (15:52 +1100)]
Merge pull request #113 from mikey/exec-sim-remove

Remove SIM generic from execute1

5 years agoMerge pull request #114 from antonblanchard/dcache
Anton Blanchard [Fri, 25 Oct 2019 04:49:33 +0000 (15:49 +1100)]
Merge pull request #114 from antonblanchard/dcache

Dcache from Ben

5 years agoRemove SIM generic from execute1
Michael Neuling [Thu, 24 Oct 2019 06:07:58 +0000 (17:07 +1100)]
Remove SIM generic from execute1

This does nothing, so remove.

Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years agoReduce wishbone address size to 32-bit
Benjamin Herrenschmidt [Wed, 16 Oct 2019 23:21:41 +0000 (10:21 +1100)]
Reduce wishbone address size to 32-bit

For now ... it reduces the routing pressure on the FPGA

This needs manual adjustment of the address decoder in soc.vhdl, at
least until I can figure out how to deal with std_match

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
# Conflicts:
# soc.vhdl

# Conflicts:
# soc.vhdl

5 years agoMake it possible to change wishbone address size
Benjamin Herrenschmidt [Wed, 25 Sep 2019 06:54:25 +0000 (16:54 +1000)]
Make it possible to change wishbone address size

All that needs to be changed now is the size in wishbone_types.vhdl
and the address decoder in soc.vhdl

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agodcache: Add testbench
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:31:39 +0000 (10:31 +1100)]
dcache: Add testbench

A very simple one for now...

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoinsn: Simplistic implementation of icbi
Benjamin Herrenschmidt [Tue, 22 Oct 2019 03:56:31 +0000 (14:56 +1100)]
insn: Simplistic implementation of icbi

We don't yet have a proper snooper for the icache, so for now make
icbi just flush the whole thing

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoinsn: Implement isync instruction
Benjamin Herrenschmidt [Tue, 22 Oct 2019 03:49:35 +0000 (14:49 +1100)]
insn: Implement isync instruction

The instruction works by redirecting fetch to nia+4 (hopefully using
the same adder used to generate LR) and doing a backflush. Along with
being single issue, this should guarantee that the next instruction
only gets fetched after the pipe's been emptied.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoicache & dcache: Fix store way variable
Benjamin Herrenschmidt [Thu, 17 Oct 2019 05:41:19 +0000 (16:41 +1100)]
icache & dcache: Fix store way variable

We used the variable "way" in the wrong state in the cache when
updating a line valid bit after the end of the wishbone transactions,
we need to use the latched "store_way".

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agodcache: Cleanup (mostly cosmetic)
Benjamin Herrenschmidt [Wed, 16 Oct 2019 04:10:27 +0000 (15:10 +1100)]
dcache: Cleanup (mostly cosmetic)

Clearly separate the 2 stages of load hits, improve naming and
comments, clarify the writeback controls etc...

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoicache/dcache: Make both caches 32 lines, 2 ways
Benjamin Herrenschmidt [Tue, 15 Oct 2019 05:21:32 +0000 (16:21 +1100)]
icache/dcache: Make both caches 32 lines, 2 ways

Adding lines seems to add only little extra as the BRAMs aren't
full, 2 ways is our current comprimise to limit pressure on small
FPGAs. We could go to 64 lines for a little more, but timing is
becoming a bit too right to my linking on the tags/LRU path of
the icache, so let's leave it at 32 for now.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agodcache: Introduce an extra cycle latency to make timing
Benjamin Herrenschmidt [Thu, 10 Oct 2019 00:25:16 +0000 (11:25 +1100)]
dcache: Introduce an extra cycle latency to make timing

This makes the BRAMs use an output buffer, introducing an extra
cycle latency. Without this, Vivado won't make timing at 100Mhz.

We stash all the necessary response data in delayed latches, the
extra cycle is NOT a state in the state machine, thus it's fully
pipelined and doesn't involve stalling.

This introduces an extra non-pipelined cycle for loads with update
to avoid collision on the writeback output between the now delayed
load data and the register update. We could avoid it by moving
the register update in the pipeline bubble created by the extra
update state, but it's a bit trickier, so I leave that for a latter
optimization.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agodcache: Add a dcache
Benjamin Herrenschmidt [Wed, 9 Oct 2019 13:40:46 +0000 (00:40 +1100)]
dcache: Add a dcache

This replaces loadstore2 with a dcache

The dcache unit is losely based on the icache one (same basic cache
layout), but has some significant logic additions to deal with stores,
loads with update, non-cachable accesses and other differences due to
operating in the execution part of the pipeline rather than the fetch
part.

The cache is store-through, though a hit with an existing line will
update the line rather than invalidate it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoicache: Reduce simulation warnings
Benjamin Herrenschmidt [Wed, 9 Oct 2019 13:40:11 +0000 (00:40 +1100)]
icache: Reduce simulation warnings

This might slightly increase the logic in synthesis but avoids
us looking at uninitialized tags when not servicing an active
request

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agocache_ram: Add write-enables
Benjamin Herrenschmidt [Wed, 9 Oct 2019 13:38:03 +0000 (00:38 +1100)]
cache_ram: Add write-enables

They will be needed by the dcache

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoplru: Improve sensitivity list
Benjamin Herrenschmidt [Tue, 8 Oct 2019 12:26:23 +0000 (23:26 +1100)]
plru: Improve sensitivity list

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoMerge pull request #112 from hughhalf/patch-1
Anton Blanchard [Mon, 21 Oct 2019 09:15:37 +0000 (20:15 +1100)]
Merge pull request #112 from hughhalf/patch-1

Minor tweaks to README.md

5 years agoMinor tweaks to README.md
Hugh [Mon, 21 Oct 2019 05:51:59 +0000 (16:51 +1100)]
Minor tweaks to README.md

Few tweaks based on a newcomers experience getting an Arty A7-100 up and running

Forgot to add DCO in initial PR, now corrected.

Signed-off-by: Hugh Blemings <hugh@blemings.org>
5 years agoMerge pull request #110 from antonblanchard/misc
Anton Blanchard [Sat, 19 Oct 2019 23:09:42 +0000 (10:09 +1100)]
Merge pull request #110 from antonblanchard/misc

icache_tb: Improve test and include test file

5 years agoicache_tb: Improve test and include test file
Benjamin Herrenschmidt [Fri, 18 Oct 2019 05:41:05 +0000 (16:41 +1100)]
icache_tb: Improve test and include test file

The icache_test.bin file was missing. This adds it (along with a python3
script to generate it).

We also add better reporting on errors

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoMerge pull request #109 from antonblanchard/misc
Anton Blanchard [Thu, 17 Oct 2019 06:37:49 +0000 (17:37 +1100)]
Merge pull request #109 from antonblanchard/misc

Misc updates from Ben

5 years agoisel takes a CR bit, not a CR field
Anton Blanchard [Thu, 17 Oct 2019 06:16:09 +0000 (17:16 +1100)]
isel takes a CR bit, not a CR field

Fix a GHDL assert in isel.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agocommon: Reformat
Benjamin Herrenschmidt [Wed, 16 Oct 2019 06:47:08 +0000 (17:47 +1100)]
common: Reformat

No code change

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoexecute1: Remove mux on "write_data" and "rc" outputs
Benjamin Herrenschmidt [Wed, 16 Oct 2019 01:32:45 +0000 (12:32 +1100)]
execute1: Remove mux on "write_data" and "rc" outputs

Only "write_enable" needs to change, this shrinks the core a bit more

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agocrhelpers: Constraint "crnum" integer
Benjamin Herrenschmidt [Wed, 16 Oct 2019 01:11:16 +0000 (12:11 +1100)]
crhelpers: Constraint "crnum" integer

This seems to save quite a few LUTs

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoexecute1: Reformat
Benjamin Herrenschmidt [Wed, 16 Oct 2019 01:28:19 +0000 (12:28 +1100)]
execute1: Reformat

No functional change

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agowriteback: Remove a mux leg on data_in
Benjamin Herrenschmidt [Wed, 16 Oct 2019 01:05:36 +0000 (12:05 +1100)]
writeback: Remove a mux leg on data_in

Initialize to 0 forces the mux to have an extra leg fed with zeros.

Instead initialize data_in to one of the mux inputs

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoMerge pull request #105 from paulusmack/writeback
Anton Blanchard [Wed, 16 Oct 2019 20:40:36 +0000 (07:40 +1100)]
Merge pull request #105 from paulusmack/writeback

Writeback

5 years agowriteback: Eliminate inferred latch
Paul Mackerras [Tue, 15 Oct 2019 20:56:15 +0000 (07:56 +1100)]
writeback: Eliminate inferred latch

This initializes data_in to all zeroes so that it doesn't become a
set of 64 inferred latches.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years agoMerge pull request #106 from paulusmack/master
Anton Blanchard [Tue, 15 Oct 2019 10:05:10 +0000 (21:05 +1100)]
Merge pull request #106 from paulusmack/master

wishbone_debug_master: Improve timing

5 years agowishbone_debug_master: Improve timing
Paul Mackerras [Tue, 15 Oct 2019 07:16:07 +0000 (18:16 +1100)]
wishbone_debug_master: Improve timing

The current code has the possibility that we could set reg_addr
or reg_ctrl and then increment reg_addr in the same cycle, resulting
in some long timing paths.  Rearrange the code to make it clear
that we are not trying to add an auto-increment to data from
outside the module; in any given cycle we either set one of
reg_addr and reg_ctrl, or we possibly increment reg_addr.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years agoRemove execute2 stage
Paul Mackerras [Tue, 15 Oct 2019 05:26:36 +0000 (16:26 +1100)]
Remove execute2 stage

Since the condition setting got moved to writeback, execute2 does
nothing aside from wasting a cycle.  This removes it.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years agoMerge pull request #104 from paulusmack/master
Anton Blanchard [Tue, 15 Oct 2019 05:17:12 +0000 (16:17 +1100)]
Merge pull request #104 from paulusmack/master

Implement neg using OP_ADD

5 years agoDo sign-extension instructions in writeback instead of execute1
Paul Mackerras [Mon, 14 Oct 2019 03:39:23 +0000 (14:39 +1100)]
Do sign-extension instructions in writeback instead of execute1

This makes the exts[bhw] instructions do the sign extension in the
writeback stage using the sign-extension logic there instead of
having unique sign extension logic in execute1.  This requires
passing the data length and sign extend flag from decode2 down
through execute1 and execute2 and into writeback.  As a side bonus
we reduce the number of values in insn_type_t by two.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years agowriteback: Do data formatting and condition recording in writeback
Paul Mackerras [Mon, 14 Oct 2019 01:56:01 +0000 (12:56 +1100)]
writeback: Do data formatting and condition recording in writeback

This adds code to writeback to format data and test the result
against zero for the purpose of setting CR0.  The data formatter
is able to shift and mask by bytes and do byte reversal and sign
extension.  It can also put together bytes from two input
doublewords to support unaligned loads (including unaligned
byte-reversed loads).

The data formatter starts with an 8:1 multiplexer that is able
to direct any byte of the input to any byte of the output.  This
lets us rotate the data and simultaneously byte-reverse it.
The rotated/reversed data goes to a register for the unaligned
cases that overlap two doublewords.  Then there is per-byte logic
that does trimming, sign extension, and splicing together bytes
from a previous input doubleword (stored in data_latched) and the
current doubleword.  Finally the 64-bit result is tested to set
CR0 if rc = 1.

This removes the RC logic from the execute2, multiply and divide
units, and the shift/mask/byte-reverse/sign-extend logic from
loadstore2.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years agoMerge pull request #103 from paulusmack/divider
Anton Blanchard [Tue, 15 Oct 2019 04:20:34 +0000 (15:20 +1100)]
Merge pull request #103 from paulusmack/divider

Divider

5 years agoImplement neg using OP_ADD
Paul Mackerras [Mon, 14 Oct 2019 05:02:45 +0000 (16:02 +1100)]
Implement neg using OP_ADD

We have all the machinery in place to implement the neg instruction
as OP_ADD.  Doing that means we can ditch OP_NEG, and saves about
66 slice LUTs on the A7-100.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>