mesa.git
6 years agoautotools, meson: bump up required VA version
Juan A. Suarez Romero [Fri, 27 Apr 2018 08:38:09 +0000 (10:38 +0200)]
autotools, meson: bump up required VA version

Due using a new VP9 config we use, required VA API 0.39

Fixes: 413c5ca3727 ("travis: update libva required version")
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
6 years agodocs: update calendar, add news and link release notes to 18.0.2
Juan A. Suarez Romero [Sat, 28 Apr 2018 17:01:48 +0000 (17:01 +0000)]
docs: update calendar, add news and link release notes to 18.0.2

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
6 years agodocs: add sha256 checksums for 18.0.2
Juan A. Suarez Romero [Sat, 28 Apr 2018 16:57:30 +0000 (16:57 +0000)]
docs: add sha256 checksums for 18.0.2

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit b3eed3ad03fd1eb61474cd0a8a173ad40fb8a876)

6 years agodocs: add release notes for 18.0.2
Juan A. Suarez Romero [Sat, 28 Apr 2018 16:22:11 +0000 (16:22 +0000)]
docs: add release notes for 18.0.2

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit d38da7bd2d4387635fac8bc7f45e64f50dc43c43)

6 years agoradeonsi: increase the number of compiler threads depending on the CPU
Marek Olšák [Fri, 13 Apr 2018 22:09:11 +0000 (18:09 -0400)]
radeonsi: increase the number of compiler threads depending on the CPU

The compiler queue was limited to 3 threads, so shader-db running
on a 16-thread CPU would have a bottleneck on the 3-thread queue.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: avoid a crash in gallivm_dispose_target_library_info
Marek Olšák [Mon, 9 Apr 2018 23:55:10 +0000 (19:55 -0400)]
radeonsi: avoid a crash in gallivm_dispose_target_library_info

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: move data_layout into si_compiler
Marek Olšák [Mon, 9 Apr 2018 23:23:55 +0000 (19:23 -0400)]
radeonsi: move data_layout into si_compiler

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: move passmgr into si_compiler
Marek Olšák [Mon, 9 Apr 2018 23:13:37 +0000 (19:13 -0400)]
radeonsi: move passmgr into si_compiler

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: move target_library_info into si_compiler
Marek Olšák [Mon, 9 Apr 2018 22:43:54 +0000 (18:43 -0400)]
radeonsi: move target_library_info into si_compiler

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: use si_compiler::triple in si_llvm_optimize_module
Marek Olšák [Mon, 9 Apr 2018 22:36:58 +0000 (18:36 -0400)]
radeonsi: use si_compiler::triple in si_llvm_optimize_module

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: add triple into si_compiler
Marek Olšák [Mon, 9 Apr 2018 22:35:45 +0000 (18:35 -0400)]
radeonsi: add triple into si_compiler

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: add struct si_compiler containing LLVMTargetMachineRef
Marek Olšák [Mon, 9 Apr 2018 22:26:05 +0000 (18:26 -0400)]
radeonsi: add struct si_compiler containing LLVMTargetMachineRef

It will contain more variables.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: rename r600_texture::resource to buffer
Marek Olšák [Mon, 9 Apr 2018 01:53:25 +0000 (21:53 -0400)]
radeonsi: rename r600_texture::resource to buffer

r600_resource could be renamed to si_buffer.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: use r600_resource() typecast helper
Marek Olšák [Mon, 9 Apr 2018 01:52:05 +0000 (21:52 -0400)]
radeonsi: use r600_resource() typecast helper

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: remove unused atom parameter from si_atom::emit
Marek Olšák [Mon, 9 Apr 2018 01:20:53 +0000 (21:20 -0400)]
radeonsi: remove unused atom parameter from si_atom::emit

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: inline 2 trivial state structures
Marek Olšák [Mon, 9 Apr 2018 01:12:24 +0000 (21:12 -0400)]
radeonsi: inline 2 trivial state structures

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: remove function si_init_atom
Marek Olšák [Mon, 9 Apr 2018 01:07:29 +0000 (21:07 -0400)]
radeonsi: remove function si_init_atom

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: remove si_atom::id
Marek Olšák [Mon, 9 Apr 2018 01:03:51 +0000 (21:03 -0400)]
radeonsi: remove si_atom::id

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: don't use an indirect table for state atoms
Marek Olšák [Mon, 9 Apr 2018 00:54:02 +0000 (20:54 -0400)]
radeonsi: don't use an indirect table for state atoms

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: rename r600_atom -> si_atom
Marek Olšák [Mon, 9 Apr 2018 00:26:14 +0000 (20:26 -0400)]
radeonsi: rename r600_atom -> si_atom

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: remove r600_pipe_common.h
Marek Olšák [Mon, 9 Apr 2018 00:20:39 +0000 (20:20 -0400)]
radeonsi: remove r600_pipe_common.h

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi/gfx9: workaround for INTERP with indirect indexing
Marek Olšák [Fri, 13 Apr 2018 21:15:06 +0000 (17:15 -0400)]
radeonsi/gfx9: workaround for INTERP with indirect indexing

and clean up the conditions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
6 years agoradeonsi: rewrite DCC format compatibility checking code
Marek Olšák [Thu, 12 Apr 2018 01:21:28 +0000 (21:21 -0400)]
radeonsi: rewrite DCC format compatibility checking code

It might be better to use a slow compressed clear when clearing to 1.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: implement DCC fast clear swizzle constraints more accurately
Marek Olšák [Thu, 5 Apr 2018 01:43:28 +0000 (21:43 -0400)]
radeonsi: implement DCC fast clear swizzle constraints more accurately

Reduce swizzle constraints to the ALPHA_IS_ON_MSB constraint and the clear
value of 1.

This significantly changes the DCC fast clear code, and fixes fast clear
for RGB formats without alpha.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: rename variables and document stuff around DCC fast clear
Marek Olšák [Wed, 11 Apr 2018 15:30:58 +0000 (11:30 -0400)]
radeonsi: rename variables and document stuff around DCC fast clear

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: fully enable 2x DCC MSAA for array and non-array textures
Marek Olšák [Sun, 8 Apr 2018 03:40:26 +0000 (23:40 -0400)]
radeonsi: fully enable 2x DCC MSAA for array and non-array textures

The clear code is exactly the same as for 1 sample buffers -
just clear the whole thing.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: enable fast color clear for level 0 of mipmapped textures on <= VI
Marek Olšák [Sun, 8 Apr 2018 04:19:50 +0000 (00:19 -0400)]
radeonsi: enable fast color clear for level 0 of mipmapped textures on <= VI

GFX9 is more complicated and needs a compute shader that we should just
copy from amdvlk.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoac/surface: handle DCC subresource fast clear restriction on VI
Marek Olšák [Mon, 16 Apr 2018 20:34:56 +0000 (16:34 -0400)]
ac/surface: handle DCC subresource fast clear restriction on VI

v2: require the previous level to be clearable for determining whether
    the last unaligned level is clearable

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoswr/rast: No need to export GetSimdValidIndicesGfx
George Kyriazis [Tue, 24 Apr 2018 22:03:00 +0000 (17:03 -0500)]
swr/rast: No need to export GetSimdValidIndicesGfx

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Small editorial changes
George Kyriazis [Tue, 24 Apr 2018 21:44:19 +0000 (16:44 -0500)]
swr/rast: Small editorial changes

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Use new processor detection mechanism
George Kyriazis [Tue, 24 Apr 2018 16:13:54 +0000 (11:13 -0500)]
swr/rast: Use new processor detection mechanism

Use specific avx512 selection mechanism based on avx512er bit instead of
getHostCPUName().  LLVM 6.0.0 has a bug that reports wrong string for KNL
(fixed in 6.0.1).

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Output rasterizer dir to console since it's process specific
George Kyriazis [Mon, 23 Apr 2018 23:14:59 +0000 (18:14 -0500)]
swr/rast: Output rasterizer dir to console since it's process specific

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Add TranslateGfxAddress for shader
George Kyriazis [Mon, 23 Apr 2018 23:00:10 +0000 (18:00 -0500)]
swr/rast: Add TranslateGfxAddress for shader

Also add GFX_MEM_CLIENT_SHADER

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: jit PRINT improvements.
George Kyriazis [Mon, 23 Apr 2018 21:34:44 +0000 (16:34 -0500)]
swr/rast: jit PRINT improvements.

Sign-extend integer types to 32bit when specifying "%d" and add new %u
which zero-extends to 32bit. Improves  printing of sub 32bit integer types
(i1 specifically).

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Fix regressions.
George Kyriazis [Mon, 23 Apr 2018 21:31:38 +0000 (16:31 -0500)]
swr/rast: Fix regressions.

Bump jit cache revision number to force recompile.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Cleanup old cruft.
George Kyriazis [Mon, 23 Apr 2018 16:22:50 +0000 (11:22 -0500)]
swr/rast: Cleanup old cruft.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Package events.proto with core output
George Kyriazis [Fri, 20 Apr 2018 18:29:39 +0000 (13:29 -0500)]
swr/rast: Package events.proto with core output

However only if the file exists in DEBUG_OUTPUT_DIR. The expectation is
that AR rasterizerLauncher will start placing it there when launching
a workload (which is in a subsequent checkin)

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Fix init in EventHandlerWorkerStats
George Kyriazis [Thu, 19 Apr 2018 22:59:08 +0000 (17:59 -0500)]
swr/rast: Fix init in EventHandlerWorkerStats

Make sure we initialize variables.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Fix return type of VCVTPS2PH.
George Kyriazis [Thu, 19 Apr 2018 18:15:31 +0000 (13:15 -0500)]
swr/rast: Fix return type of VCVTPS2PH.

expecting <8xi16> return.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: WIP Translation handling
George Kyriazis [Wed, 18 Apr 2018 20:17:04 +0000 (15:17 -0500)]
swr/rast: WIP Translation handling

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Use different handing for stream masks
George Kyriazis [Tue, 17 Apr 2018 04:18:28 +0000 (23:18 -0500)]
swr/rast: Use different handing for stream masks

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Silence warnings
George Kyriazis [Mon, 16 Apr 2018 23:54:45 +0000 (18:54 -0500)]
swr/rast: Silence warnings

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Add support for TexelMask evaluation
George Kyriazis [Sun, 15 Apr 2018 16:57:47 +0000 (11:57 -0500)]
swr/rast: Add support for TexelMask evaluation

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Internal core change
George Kyriazis [Sat, 14 Apr 2018 08:34:44 +0000 (03:34 -0500)]
swr/rast: Internal core change

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Fix x86 lowering 64-bit float handling
George Kyriazis [Fri, 13 Apr 2018 21:21:24 +0000 (16:21 -0500)]
swr/rast: Fix x86 lowering 64-bit float handling

- 64-bit cvt-to-float needs to be explicitly handled
- gathers need the right parameter types to work with doubles

Fixes draw-vertices piglit tests

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Add some SIMD_T utility functors
George Kyriazis [Fri, 13 Apr 2018 21:14:42 +0000 (16:14 -0500)]
swr/rast: Add some SIMD_T utility functors

VecEqual and VecHash

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Fix wrong type allocation
George Kyriazis [Thu, 12 Apr 2018 18:10:05 +0000 (13:10 -0500)]
swr/rast: Fix wrong type allocation

ALLOCA pointer elements, not pointers.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr: touch generated files to update timestamp
George Kyriazis [Tue, 24 Apr 2018 18:29:41 +0000 (13:29 -0500)]
swr: touch generated files to update timestamp

previous change in generators necessitates this change

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Fix byte offset for non-indexed draws
George Kyriazis [Tue, 10 Apr 2018 23:43:31 +0000 (18:43 -0500)]
swr/rast: Fix byte offset for non-indexed draws

for the case when USE_SIMD16_SHADERS == FALSE

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoutil/u_queue: fix a deadlock in util_queue_finish
Marek Olšák [Tue, 24 Apr 2018 21:01:35 +0000 (17:01 -0400)]
util/u_queue: fix a deadlock in util_queue_finish

Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agomeson: fix race condition revealed by using 0.44
Dylan Baker [Thu, 26 Apr 2018 17:20:57 +0000 (10:20 -0700)]
meson: fix race condition revealed by using 0.44

Previously there was a special target that blocked for the generation of
anv_entrypoints.h, with meson 0.44 we don't need this, we can use a new
language feature instead. The problem is that previously that blocking
target would hide a race condition for the generation of another header,
anv_extensions.h. Now the build sometimes fails when anv_extensions.h is
not generated in time.

v2: - clarify the race condition in the commit message (Emil)

CC: Mark Janes <mark.a.janes@intel.com>
Fixes: 92550d9b16d2b295bdac087f31b1fd6d0f808e02
       ("meson: remove workaround for custom target creating .h and .c files")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
6 years agobin: force git show to use default pretty setting
Dylan Baker [Thu, 26 Apr 2018 17:44:00 +0000 (10:44 -0700)]
bin: force git show to use default pretty setting

I have pretty default to short, which breaks this script.

v2: - Fix both places that don't define a --pretty (Emil)

cc: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Andres Gomez <agomez@igalia.com> (v1)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
6 years agomesa: add TBO support for GL_EXT_texture_norm16
Tapani Pälli [Fri, 27 Apr 2018 06:52:33 +0000 (09:52 +0300)]
mesa: add TBO support for GL_EXT_texture_norm16

Earlier plumbing missed interaction with texture buffer objects.

Fixes: 7f467d4f73 "mesa: GL_EXT_texture_norm16 extension plumbing"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoac: fix texture query LOD for 1D textures on GFX9
Samuel Pitoiset [Wed, 25 Apr 2018 16:15:52 +0000 (18:15 +0200)]
ac: fix texture query LOD for 1D textures on GFX9

1D textures are allocated as 2D which means we only need
one coordinate for texture query LOD.

Fixes: 625dcbbc456 ("amd/common: pass address components individually to
ac_build_image_intrinsic")
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoetnaviv: remove not needed includes
Christian Gmeiner [Fri, 20 Apr 2018 12:55:53 +0000 (14:55 +0200)]
etnaviv: remove not needed includes

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
6 years agoetnaviv: remove redundant include
Christian Gmeiner [Fri, 20 Apr 2018 12:55:52 +0000 (14:55 +0200)]
etnaviv: remove redundant include

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
6 years agoglsl: replace some asserts with unreachable when processing the ast
Timothy Arceri [Tue, 10 Apr 2018 04:34:26 +0000 (14:34 +1000)]
glsl: replace some asserts with unreachable when processing the ast

Reviewed-by: Matt Turner <mattst88@gmail.com>
6 years agomesa: drop the buffer mode param from the DrawBuffer driver function
Timothy Arceri [Fri, 27 Apr 2018 00:03:56 +0000 (10:03 +1000)]
mesa: drop the buffer mode param from the DrawBuffer driver function

No drivers used it.

Reviewed-by: Brian Paul <brianp@vmware.com>
6 years agoanv/icl: Enable Vulkan on Ice Lake
Anuj Phogat [Mon, 16 Apr 2018 22:48:41 +0000 (15:48 -0700)]
anv/icl: Enable Vulkan on Ice Lake

This patch enables the Vulkan driver on Ice Lake h/w
with added warning about preliminary support.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
6 years agoanv: enable VK_EXT_shader_viewport_index_layer
Caio Marcelo de Oliveira Filho [Thu, 26 Apr 2018 19:11:20 +0000 (12:11 -0700)]
anv: enable VK_EXT_shader_viewport_index_layer

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoanv/allocator: Don't shrink either end of the block pool
Jason Ekstrand [Sat, 21 Apr 2018 04:52:41 +0000 (21:52 -0700)]
anv/allocator: Don't shrink either end of the block pool

Previously, we only tried to ensure that we didn't shrink either end
below what was already handed out.  However, due to the way we handle
relocations with block pools, we can't shrink the back end at all.  It's
probably best to not shrink in either direction.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105374
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106147
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Cc: mesa-stable@lists.freedesktop.org
6 years agobroadcom/vc5: Add support for centroid varyings.
Eric Anholt [Thu, 26 Apr 2018 16:24:32 +0000 (09:24 -0700)]
broadcom/vc5: Add support for centroid varyings.

It would be nice to share the flags packet emit logic with flat shade
flags, but I couldn't come up with a good way while still using our pack
macros.  We need to refactor this to shader record setup at compile time,
anyway.

Fixes ext_framebuffer_multisample-interpolation * centroid-*

6 years agobroadcom/vc5: Add an assert about GFXH-1559.
Eric Anholt [Wed, 25 Apr 2018 23:30:20 +0000 (16:30 -0700)]
broadcom/vc5: Add an assert about GFXH-1559.

Our TF outputs always start at 6 or 7 currently, so we don't hit the
broken 8 case.  Let's make sure that doesn't change somehow.

6 years agobroadcom/vc5: Add validation that we don't violate GFXH-1633 requirements.
Eric Anholt [Wed, 25 Apr 2018 23:24:15 +0000 (16:24 -0700)]
broadcom/vc5: Add validation that we don't violate GFXH-1633 requirements.

We don't use ldunifa yet, but we will eventually for UBOs.

6 years agobroadcom/vc5: Add validation that we don't violate GFXH-1625 requirements.
Eric Anholt [Wed, 25 Apr 2018 23:16:27 +0000 (16:16 -0700)]
broadcom/vc5: Add validation that we don't violate GFXH-1625 requirements.

We don't use TMUWT yet, but we will once we do SSBOs.

6 years agobroadcom/vc5: Implement GFXH-1742 workaround (emit 2 dummy stores on 4.x).
Eric Anholt [Wed, 25 Apr 2018 21:18:52 +0000 (14:18 -0700)]
broadcom/vc5: Implement GFXH-1742 workaround (emit 2 dummy stores on 4.x).

This should fix help with intermittent GPU hangs in tests switching
formats while rendering small frames.  Unfortunately, it didn't help with
the tests I'm having troubles with.

6 years agobroadcom/vc5: Add QPU validation for register writes after thrend.
Eric Anholt [Wed, 25 Apr 2018 20:51:47 +0000 (13:51 -0700)]
broadcom/vc5: Add QPU validation for register writes after thrend.

The next shader gets to start writing the register file during these
slots, so make sure we don't stomp over them.

The only case of hitting this that I could imagine would be dead writes.

6 years agost: Choose a 2101010 format for GL_RGB/GL_RGBA with a 2_10_10_10 type.
Eric Anholt [Wed, 25 Apr 2018 18:40:40 +0000 (11:40 -0700)]
st: Choose a 2101010 format for GL_RGB/GL_RGBA with a 2_10_10_10 type.

GLES's GL_EXT_texture_type_2_10_10_10_REV allows uploading this type to an
unsized internalformat, and it should be non-color-renderable.
fbobject.c's implementation of the check for color-renderable is checks
that the texture has a 2101010 mesa format, so make sure that we have
chosen a 2101010 format so that check can do what it meant to.

Fixes KHR-GLES3.packed_pixels.pbo_rectangle.rgb on vc5.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agost/mesa: fix missing setting of _ElementSize in new_draw_rasterpos_stage
Charmaine Lee [Thu, 26 Apr 2018 16:21:52 +0000 (09:21 -0700)]
st/mesa: fix missing setting of _ElementSize in new_draw_rasterpos_stage

With this patch, _ElementSize is initialized along with the rest
of the vertex array attributes in new_draw_rasterpos_stage().
This fixes a crash in st_pipe_vertex_format() when running
topogun-1.06-orc-84k-resize trace file with VMware svga driver.

Reviewed-by: Brian Paul <brianp@vmware.com>
6 years agost/va: Fix typos
Drew Davenport [Wed, 25 Apr 2018 15:32:31 +0000 (09:32 -0600)]
st/va: Fix typos

s/attibute/attribute/
s/suface/surface/

v2: rebased(Leo)

Reviewed-by: Leo Liu <leo.liu@amd.com>
6 years agost/va: Fix potential buffer overread
Drew Davenport [Tue, 24 Apr 2018 23:01:32 +0000 (17:01 -0600)]
st/va: Fix potential buffer overread

VASurfaceAttribExternalBuffers.pitches is indexed by
plane. Current implementation only supports single plane layout.

Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Leo Liu <leo.liu@amd.com>
6 years agoradeon/vcn: fix mpeg4 msg buffer settings
Boyuan Zhang [Wed, 25 Apr 2018 15:49:52 +0000 (11:49 -0400)]
radeon/vcn: fix mpeg4 msg buffer settings

Previous bit-fields assignments are incorrect and will result certain mpeg4
decode failed due to wrong flag values. This patch fixes these assignments.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
6 years agoradeon: Drop broken front_buffer_reading/drawing optimization
Ian Romanick [Fri, 18 Sep 2015 16:00:28 +0000 (12:00 -0400)]
radeon: Drop broken front_buffer_reading/drawing optimization

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agoradeon: Use _mesa_is_front_buffer_drawing
Ian Romanick [Thu, 17 Sep 2015 14:56:15 +0000 (10:56 -0400)]
radeon: Use _mesa_is_front_buffer_drawing

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agoradv: set ac_surf_info::num_channels correctly
Samuel Pitoiset [Wed, 25 Apr 2018 09:22:17 +0000 (11:22 +0200)]
radv: set ac_surf_info::num_channels correctly

num_channels has been introduced since "ac/surface: don't set
the display flag for obviously unsupported cases".

Based on RadeonSI.

Fixes: e29facff315 ("ac/surface: don't set the display flag for obviously unsupported cases (v2)")
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoradv: fix DCC enablement since partial MSAA implementation
Samuel Pitoiset [Wed, 25 Apr 2018 08:56:15 +0000 (10:56 +0200)]
radv: fix DCC enablement since partial MSAA implementation

dcc_msaa_allowed is always false on GFX9+ and only true on VI
if RADV_PERFTEST=dccmsaa is set. This means DCC was disabled
in some situations where it should not.

This is likely going to fix a performance regression.

Fixes: 2f63b3dd09 ("radv: enable DCC for MSAA 2x textures on VI under an option")
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agonir/opt_constant_folding: fix folding of 8 and 16 bit ints
Karol Herbst [Sun, 22 Apr 2018 01:29:07 +0000 (03:29 +0200)]
nir/opt_constant_folding: fix folding of 8 and 16 bit ints

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agonir: print 8 and 16 bit constants correctly
Karol Herbst [Sat, 21 Apr 2018 23:31:22 +0000 (01:31 +0200)]
nir: print 8 and 16 bit constants correctly

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agonir: support converting to 8-bit integers in nir_type_conversion_op
Karol Herbst [Sat, 21 Apr 2018 15:27:17 +0000 (17:27 +0200)]
nir: support converting to 8-bit integers in nir_type_conversion_op

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agospirv: Don’t check for NaN for most OpFOrd* comparisons
Neil Roberts [Tue, 24 Apr 2018 10:17:56 +0000 (12:17 +0200)]
spirv: Don’t check for NaN for most OpFOrd* comparisons

For all of the OpFOrd* comparisons except OpFOrdNotEqual the hardware
should probably already return false if one of the operands is NaN so
we don’t need to have an explicit check for it. This seems to at least
work on Intel hardware. This should reduce the number of instructions
generated for the most common comparisons.

For what it’s worth, the original code to handle this was added in
e062eb6415de3a. The commit message for that says that it was to fix
some CTS tests for OpFUnord* opcodes. Even if the hardware doesn’t
handle NaNs this patch shouldn’t affect those tests. At any rate they
have since been moved out of the mustpass list. Incidentally those
tests fail on the nvidia proprietary driver so it doesn’t seem like
handling NaNs correctly is a priority.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoIntel: Add a Kaby Lake PCI ID
Matt Atwood [Wed, 25 Apr 2018 16:23:04 +0000 (09:23 -0700)]
Intel: Add a Kaby Lake PCI ID

v2: Branding changed

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
6 years agogallium/util: Fix incorrect refcounting of separate stencil.
Eric Anholt [Wed, 25 Apr 2018 16:47:40 +0000 (09:47 -0700)]
gallium/util: Fix incorrect refcounting of separate stencil.

The driver may have a reference on the separate stencil buffer for some
reason (like an unflushed job using it), so we can't directly free the
resource and should instead just decrement the refcount that we own.
Fixes double-free in KHR-GLES3.packed_depth_stencil.blit.depth32f_stencil8
on vc5.

Fixes: e94eb5e6000e ("gallium/util: add u_transfer_helper")
Reviewed-by: Rob Clark <robdclark@gmail.com>
6 years agobroadcom/vc5: Fix reloads of separate stencil buffers.
Eric Anholt [Wed, 25 Apr 2018 00:50:50 +0000 (17:50 -0700)]
broadcom/vc5: Fix reloads of separate stencil buffers.

Like for stores, we need to emit a separate load_general packet.

6 years agobroadcom/vc5: Fix cpp of MSAA surfaces on 4.x.
Eric Anholt [Tue, 24 Apr 2018 21:56:23 +0000 (14:56 -0700)]
broadcom/vc5: Fix cpp of MSAA surfaces on 4.x.

The internal-type-bpp path is for surfaces that get stored in the raw TLB
format.  For 4.x, we're storing MSAA as just 2x width/height at the
original format.

6 years agobroadcom/vc5: Implement stencil blits using RGBA.
Eric Anholt [Tue, 24 Apr 2018 18:11:40 +0000 (11:11 -0700)]
broadcom/vc5: Implement stencil blits using RGBA.

Fixes piglit fbo-depthstencil blit default_fb

6 years agobroadcom/vc5: Remove leftover vc4 MSAA lowering setup in the FS key.
Eric Anholt [Tue, 24 Apr 2018 22:23:27 +0000 (15:23 -0700)]
broadcom/vc5: Remove leftover vc4 MSAA lowering setup in the FS key.

6 years agobroadcom/vc5: Fix tile load/store of MSAA surfaces on 4.x.
Eric Anholt [Tue, 24 Apr 2018 20:22:41 +0000 (13:22 -0700)]
broadcom/vc5: Fix tile load/store of MSAA surfaces on 4.x.

For single-sample we have to always program SAMPLE_0, but for multisample
we want to store all the samples.

6 years agotravis: update libva required version
Juan A. Suarez Romero [Fri, 20 Apr 2018 14:34:14 +0000 (14:34 +0000)]
travis: update libva required version

Commit fa328456e8f29 added VP9 config support, but this needs a newer
libva version, 1.7.0 or above.

Fixes: fa328456e8f ("st/va: add VP9 config to enable profile2")
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
6 years agomesa: GL_EXT_texture_norm16 extension plumbing
Tapani Pälli [Fri, 6 Apr 2018 07:57:57 +0000 (10:57 +0300)]
mesa: GL_EXT_texture_norm16 extension plumbing

Patch enables use of short and unsigned short data for texture uploads,
rendering and reading of framebuffers within the restrictions specified
in GL_EXT_texture_norm16 spec.

Patch also enables those 16bit format layout qualifiers listed in
GL_NV_image_formats that depend on EXT_texture_norm16.

v2: expose extension with dummy_true
    fix layout qualifier map changes (Ilia Mirkin)

v3: use _mesa_has_EXT_texture_norm16, other fixes
    and cleanup (Ilia Mirkin)

v4: fix rest of the issues found

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agomeson: Fix with_intel_vk and with_amd_vk variables
Jordan Justen [Wed, 25 Apr 2018 01:12:51 +0000 (18:12 -0700)]
meson: Fix with_intel_vk and with_amd_vk variables

Fixes: 5608d0a2cee "meson: use array type options"
Cc: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
6 years agodraw: fix different sign logic when clipping
Roland Scheidegger [Tue, 24 Apr 2018 16:25:55 +0000 (18:25 +0200)]
draw: fix different sign logic when clipping

The logic was flawed, since mul(x,y) will be <= 0 (exactly 0) when
the sign is the same but both numbers are sufficiently small
(if the product is smaller than 2^-128).
This could apparently lead to emitting a sufficient amount of
additional bogus vertices to overflow the allocated array for them,
hitting an assertion (still safe with release builds since we just
aborted clipping after the assertion in this case - I'm however unsure
if this is now really no longer possible, so that code stays).
Not sure if the additional vertices could cause other grief, I didn't
see anything wrong even when hitting the assertion.

Essentially, both +-0 are treated as positive (the vertex is considered
to be inside the clip volume for this plane), so integrate the logic
determining different sign into the branch there.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
6 years agodraw: simplify clip null tri logic
Roland Scheidegger [Tue, 24 Apr 2018 16:12:34 +0000 (18:12 +0200)]
draw: simplify clip null tri logic

Simplifies the logic when to emit null tris (albeit the reasons why we
have to do this remain unclear).
This is strictly just logic simplification, the behavior doesn't change
at all.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
6 years agonvc0/ir: all short immediates are sign-extended, adjust LIMM test
Ilia Mirkin [Sat, 21 Apr 2018 17:08:51 +0000 (13:08 -0400)]
nvc0/ir: all short immediates are sign-extended, adjust LIMM test

Some analysis suggests that all short immediates are sign-extended. The
insnCanLoad logic already accounted for this, but we could still pick
the wrong form when emitting actual instructions that support both short
and long immediates (with the long form usually having additional
restrictions that insnCanLoad should be aware of).

This also reverses a bunch of commits that had previously "worked
around" this issue in various emitters:

9c63224540ef: gm107/ir: make use of ADD32I for all immediates
83a4f28dc27b: gm107/ir: make use of LOP32I for all immediates
b84c97587b4a: gm107/ir: make use of IMUL32I for all immediates
d30768025a22: gk110/ir: make use of IMUL32I for all immediates

as well as the original import for UMUL in the nvc0 emitter.

Reported-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Karol Herbst <kherbst@redhat.com>
6 years agomesa: call DrawBufferAllocate driver hook in update_framebuffer for windows-system FB
Boyan Ding [Sat, 14 Apr 2018 04:45:23 +0000 (14:45 +1000)]
mesa: call DrawBufferAllocate driver hook in update_framebuffer for windows-system FB

When draw buffers are changed on a bound framebuffer, DrawBufferAllocate()
hook should be called. However, it is missing in update_framebuffer with
window-system framebuffer, in which FB's draw buffer state should match
context state, potentially resulting in a change.

Note: This is needed because gallium delays creating the front buffer,
      i965 works fine without this change.

V2 (Timothy Arceri):
 - Rebased on merged/simplified DrawBuffer driver function
 - Move DrawBuffer call outside fb->ColorDrawBuffer[0] !=
   ctx->Color.DrawBuffer[0] check to make piglit pass.

v3 (Timothy Arceri):
 - Call new DrawBuffaerAllocate() driver function.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> (v2)
Reviewed-by: Brian Paul <brianp@vmware.com> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99116

6 years agost/mesa: add new driver function DrawBufferAllocate
Timothy Arceri [Tue, 24 Apr 2018 04:19:48 +0000 (14:19 +1000)]
st/mesa: add new driver function DrawBufferAllocate

Unlike some of the classic drivers the st was only using DrawBuffer()
to allocated some buffers on-demand. Creating a separate function
will allow us to call it from update_framebuffer() in the following
patch without regressing some of the older classic drivers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agomesa: some C99 tidy ups for framebuffer.c
Timothy Arceri [Tue, 24 Apr 2018 04:06:00 +0000 (14:06 +1000)]
mesa: some C99 tidy ups for framebuffer.c

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agomeson: Fix no-rtti in llvm detection
Dylan Baker [Tue, 24 Apr 2018 21:15:47 +0000 (14:15 -0700)]
meson: Fix no-rtti in llvm detection

Because I clearly wasn't thinking and clearly didn't do a good job
testing. Sigh

Fixes: c5a97d658ec19cc02719d7f86c1b0715e3d9ffc4
       ("meson: fix builds against LLVM built without rtti")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agomeson: use new warning function
Dylan Baker [Mon, 16 Apr 2018 22:19:54 +0000 (15:19 -0700)]
meson: use new warning function

Instead of emulating it with message.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
6 years agomeson: use array type options
Dylan Baker [Mon, 16 Apr 2018 22:18:08 +0000 (15:18 -0700)]
meson: use array type options

This option type is nice since it involves less converting strings into
lists, and because it validates the values that are provided.

v2: - Set with_any_vk to true if any vulkan driver is built (Eric)

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
6 years agomeson: fix builds against LLVM built without rtti
Dylan Baker [Mon, 16 Apr 2018 21:47:58 +0000 (14:47 -0700)]
meson: fix builds against LLVM built without rtti

Building without rtti is a frought with peril, but it's something that
autotools supports so we need to support it too.

Since we've moved to version 0.44 as a whole we can use the meson
functionality for accessing random llvm-config options we can check for
rtti and add -fno-rtti to all C++ code accordingly.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>