Luke Kenneth Casson Leighton [Sat, 15 May 2021 12:44:34 +0000 (13:44 +0100)]
add FP store op names to power_enums.py opcode list
Luke Kenneth Casson Leighton [Sat, 15 May 2021 12:41:39 +0000 (13:41 +0100)]
whitespace on instruction mnemonics
Luke Kenneth Casson Leighton [Sat, 15 May 2021 11:40:05 +0000 (12:40 +0100)]
add FP LD/ST D-Form operations to major.csv
Luke Kenneth Casson Leighton [Sat, 15 May 2021 11:29:46 +0000 (12:29 +0100)]
add load/store FP indexed instructions to minor_31.csv
Luke Kenneth Casson Leighton [Fri, 14 May 2021 21:18:25 +0000 (22:18 +0100)]
add FP load test lfsx
Luke Kenneth Casson Leighton [Fri, 14 May 2021 20:29:21 +0000 (21:29 +0100)]
when setting x <- GPR(RA) make sure read_regs is added to in parser
Luke Kenneth Casson Leighton [Fri, 14 May 2021 20:19:15 +0000 (21:19 +0100)]
add GPR-underscore read of regs
Luke Kenneth Casson Leighton [Fri, 14 May 2021 19:54:29 +0000 (20:54 +0100)]
add FRA ISACaller name decoding
Luke Kenneth Casson Leighton [Fri, 14 May 2021 19:36:19 +0000 (20:36 +0100)]
add FRA-FRT to power enums
Luke Kenneth Casson Leighton [Fri, 14 May 2021 19:29:35 +0000 (20:29 +0100)]
add first FP load test, still a lot TODO
Luke Kenneth Casson Leighton [Fri, 14 May 2021 19:13:06 +0000 (20:13 +0100)]
add FPR (FP Regfile) to ISACaller
Luke Kenneth Casson Leighton [Fri, 14 May 2021 19:07:00 +0000 (20:07 +0100)]
add in FPR.getz and support for FPR(x) in ISA parser
Luke Kenneth Casson Leighton [Fri, 14 May 2021 18:53:52 +0000 (19:53 +0100)]
add FRA-FRT fp reg names to ISACaller parser
Luke Kenneth Casson Leighton [Fri, 14 May 2021 17:59:20 +0000 (18:59 +0100)]
add fpmove.mdwn from v3.0B p150 book I section 4.6.5
Luke Kenneth Casson Leighton [Fri, 14 May 2021 17:50:08 +0000 (18:50 +0100)]
clarify, comments
Luke Kenneth Casson Leighton [Fri, 14 May 2021 17:49:10 +0000 (18:49 +0100)]
add FPADD, FPSUB, FPMUL, FPDIV quick hacked functions
Luke Kenneth Casson Leighton [Fri, 14 May 2021 17:28:31 +0000 (18:28 +0100)]
add very quick float convert to SelectableInt
Luke Kenneth Casson Leighton [Fri, 14 May 2021 16:56:06 +0000 (17:56 +0100)]
add import of DOUBLE/SINGLE to pywriter
Luke Kenneth Casson Leighton [Fri, 14 May 2021 16:47:48 +0000 (17:47 +0100)]
add SINGLE function to helpers, for FP Store
Luke Kenneth Casson Leighton [Fri, 14 May 2021 16:31:35 +0000 (17:31 +0100)]
add first pass at DOUBLE helper function for FP ISACaller simulation
Luke Kenneth Casson Leighton [Fri, 14 May 2021 16:13:09 +0000 (17:13 +0100)]
add zero-variant (RA|0) in fpload pseudocode, cleaner, clearer
Luke Kenneth Casson Leighton [Fri, 14 May 2021 16:11:42 +0000 (17:11 +0100)]
add fpstore.mdwn
Luke Kenneth Casson Leighton [Fri, 14 May 2021 15:49:24 +0000 (16:49 +0100)]
add fpload.mdwn for FP simulation
Luke Kenneth Casson Leighton [Tue, 11 May 2021 11:27:00 +0000 (12:27 +0100)]
add setting of MSR "PR" bit for when running MMU test
Luke Kenneth Casson Leighton [Mon, 10 May 2021 17:13:29 +0000 (18:13 +0100)]
extra checks on ldst exception unit test
Luke Kenneth Casson Leighton [Mon, 10 May 2021 17:03:24 +0000 (18:03 +0100)]
fix MemException, return correct address in DAR
Luke Kenneth Casson Leighton [Mon, 10 May 2021 17:01:01 +0000 (18:01 +0100)]
testing load misaligned
Luke Kenneth Casson Leighton [Mon, 10 May 2021 17:00:47 +0000 (18:00 +0100)]
test_maxint, add zero onto 0xffffffffffffff
Luke Kenneth Casson Leighton [Mon, 10 May 2021 16:49:19 +0000 (17:49 +0100)]
add first LD/ST exceptions test case for ISACaller
Luke Kenneth Casson Leighton [Mon, 10 May 2021 15:24:57 +0000 (16:24 +0100)]
save SVSRR0 in trap, if SVP64 mode enabled
Luke Kenneth Casson Leighton [Mon, 10 May 2021 15:22:34 +0000 (16:22 +0100)]
create new call_trap function in ISACaller
Luke Kenneth Casson Leighton [Mon, 10 May 2021 15:10:14 +0000 (16:10 +0100)]
add catch of MemException in ISACaller to raise unaligned exception 0x600
DAR is set as the address raised from the exception
Luke Kenneth Casson Leighton [Mon, 10 May 2021 14:42:04 +0000 (15:42 +0100)]
include Error keyword in message
Luke Kenneth Casson Leighton [Mon, 10 May 2021 14:41:14 +0000 (15:41 +0100)]
allow unaligned access exception to be raised in ISACaller mem simulator
Luke Kenneth Casson Leighton [Sun, 9 May 2021 14:57:09 +0000 (15:57 +0100)]
add ld/st misalignment test case
Luke Kenneth Casson Leighton [Thu, 6 May 2021 17:51:33 +0000 (18:51 +0100)]
add relevant pred source/dest mask bits and create appropriate zeroing
signal for predicate source/dest
Luke Kenneth Casson Leighton [Thu, 6 May 2021 16:26:52 +0000 (17:26 +0100)]
add first SVP64 predicate dest-zeroing unit test
Luke Kenneth Casson Leighton [Thu, 6 May 2021 16:19:46 +0000 (17:19 +0100)]
remove non-predicated svp64 ISACaller tests
Luke Kenneth Casson Leighton [Thu, 6 May 2021 16:17:19 +0000 (17:17 +0100)]
improve format of docstrings for ISACaller SVP64 tests
Luke Kenneth Casson Leighton [Thu, 6 May 2021 13:36:45 +0000 (14:36 +0100)]
reformat SVP64 docstrings to vaguely resemble something useful in sphinx-doc
Luke Kenneth Casson Leighton [Thu, 6 May 2021 13:16:48 +0000 (14:16 +0100)]
sphinx docstring highlight of SVP64 listings
Luke Kenneth Casson Leighton [Thu, 6 May 2021 12:39:46 +0000 (13:39 +0100)]
move logical SVP64 test cases to separate file/directory
Luke Kenneth Casson Leighton [Thu, 6 May 2021 12:34:08 +0000 (13:34 +0100)]
whoops error in docstring
Luke Kenneth Casson Leighton [Thu, 6 May 2021 12:31:36 +0000 (13:31 +0100)]
tidy up svp64 cases to make it better suited to documentation
https://bugs.libre-soc.org/show_bug.cgi?id=639
Luke Kenneth Casson Leighton [Wed, 5 May 2021 13:12:23 +0000 (14:12 +0100)]
update about Copyright law when it comes to facts
Luke Kenneth Casson Leighton [Wed, 5 May 2021 13:03:43 +0000 (14:03 +0100)]
add symlink to license
Luke Kenneth Casson Leighton [Wed, 5 May 2021 13:02:43 +0000 (14:02 +0100)]
add saturate SVP64 RM mode decode
Luke Kenneth Casson Leighton [Wed, 5 May 2021 12:52:36 +0000 (13:52 +0100)]
split PowerDecodeSubset do_copy into do_copy and do_get
Luke Kenneth Casson Leighton [Wed, 5 May 2021 12:37:22 +0000 (13:37 +0100)]
explicitly copy SV RM decoded fields in PowerDecodeSubset
Luke Kenneth Casson Leighton [Wed, 5 May 2021 12:32:13 +0000 (13:32 +0100)]
move SVP64 RM mode decoder into PowerDecodeSubset
this allows individual (satellite) decoders to get SVP64 characteristics
such as predication zeroing, saturation and other modes
Luke Kenneth Casson Leighton [Wed, 5 May 2021 11:49:24 +0000 (12:49 +0100)]
remove another verbose debug print
Luke Kenneth Casson Leighton [Wed, 5 May 2021 11:46:56 +0000 (12:46 +0100)]
add sv_input_record_layout to match SVP64RMModeDecode
Luke Kenneth Casson Leighton [Tue, 4 May 2021 17:33:36 +0000 (18:33 +0100)]
whoops must include SVSTATE in STATE regfile regspec read/write map
Luke Kenneth Casson Leighton [Tue, 4 May 2021 17:30:44 +0000 (18:30 +0100)]
IssuerDecode2ToOperand needs svstate (matching msr and cia)
Luke Kenneth Casson Leighton [Tue, 4 May 2021 17:09:54 +0000 (18:09 +0100)]
add more ALUHelper routines for fast3
Luke Kenneth Casson Leighton [Tue, 4 May 2021 16:56:03 +0000 (17:56 +0100)]
add ALUHelpers check_fast_spr3 for SVSRR0 checking
Luke Kenneth Casson Leighton [Tue, 4 May 2021 16:51:16 +0000 (17:51 +0100)]
add SVSRR0 to OP_RFID and OP_TRAP reg read/write
Luke Kenneth Casson Leighton [Tue, 4 May 2021 16:38:52 +0000 (17:38 +0100)]
add fast3 to PowerDecoder and regspec map
needed for SVSRR0
Luke Kenneth Casson Leighton [Tue, 4 May 2021 16:38:18 +0000 (17:38 +0100)]
add SVSRR0 spr_to_fast lookup
Luke Kenneth Casson Leighton [Tue, 4 May 2021 16:29:38 +0000 (17:29 +0100)]
copy over svstate from core state in PowerDecoder2
add SVSRR0 to FastRegsEnum
Luke Kenneth Casson Leighton [Tue, 4 May 2021 16:11:31 +0000 (17:11 +0100)]
comment out a bit more of the insanely high debug info
Luke Kenneth Casson Leighton [Tue, 4 May 2021 16:10:29 +0000 (17:10 +0100)]
rename PowerDecoder2 exc field to ldst_exc
Luke Kenneth Casson Leighton [Tue, 4 May 2021 12:48:37 +0000 (13:48 +0100)]
move "happened" field to end of LDSTException
Luke Kenneth Casson Leighton [Tue, 4 May 2021 12:34:33 +0000 (13:34 +0100)]
disable some of the extreme verbose debug printing
Luke Kenneth Casson Leighton [Sun, 2 May 2021 05:59:01 +0000 (06:59 +0100)]
add astor to setup.py dependencies
Luke Kenneth Casson Leighton [Sun, 2 May 2021 05:51:07 +0000 (06:51 +0100)]
change dependency name to libresoc-nmutil
Luke Kenneth Casson Leighton [Sat, 1 May 2021 15:18:33 +0000 (16:18 +0100)]
clean up MMU ROM test case
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 16:59:20 +0000 (17:59 +0100)]
add single regression test for bc_ctr in branch cases
Jacob Lifshay [Fri, 30 Apr 2021 02:01:44 +0000 (19:01 -0700)]
fix executable names
Luke Kenneth Casson Leighton [Mon, 26 Apr 2021 12:14:32 +0000 (13:14 +0100)]
add additional unit tests
Luke Kenneth Casson Leighton [Mon, 26 Apr 2021 11:37:16 +0000 (12:37 +0100)]
add cross-reference to gem5 power tests
Cesar Strauss [Sun, 25 Apr 2021 18:08:27 +0000 (15:08 -0300)]
Add a reentrant CR predication test case
Cesar Strauss [Sun, 25 Apr 2021 17:01:43 +0000 (14:01 -0300)]
Add test case for reentrant CR predication in ISACAller
This is derived from the intpred reentrant test.
It uses the new facility for easily setting individual CR bits.
Cesar Strauss [Sun, 25 Apr 2021 14:41:03 +0000 (11:41 -0300)]
Move creation of CR fields to its own class
This will ease setting and checking CR fields from test cases.
The old attribute names were kept as aliases, so it shouldn't have any
impact.
Cesar Strauss [Sun, 25 Apr 2021 14:18:29 +0000 (11:18 -0300)]
Improve debug information on mtcrf test case
Cesar Strauss [Sun, 25 Apr 2021 13:50:39 +0000 (10:50 -0300)]
Match CR size on ISACaller mtcrf test case
The underlying register for CR seems to be 64 bits for some reason. See:
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/caller.py;h=
2f9dfa8746625f74fccaf9cd8a86f5503837009d;hb=HEAD#l495
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 15:35:28 +0000 (16:35 +0100)]
add missing __init__.py to get sphinxdoc working
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 15:06:56 +0000 (16:06 +0100)]
correct heading
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 15:04:58 +0000 (16:04 +0100)]
correct errors for sphinx doc build
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 14:59:18 +0000 (15:59 +0100)]
add sphinx doc config
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 03:31:02 +0000 (04:31 +0100)]
add ply and pygdbmi dependencies
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 03:24:20 +0000 (04:24 +0100)]
update version 0.0.1
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 03:08:00 +0000 (04:08 +0100)]
update news
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 19:54:56 +0000 (20:54 +0100)]
update README
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 19:27:20 +0000 (20:27 +0100)]
add logical test cases
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 19:23:24 +0000 (20:23 +0100)]
add TRAP test cases
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 19:06:30 +0000 (20:06 +0100)]
add spr tests
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:53:57 +0000 (19:53 +0100)]
add branch test cases
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:48:29 +0000 (19:48 +0100)]
add LDST test cases
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:42:15 +0000 (19:42 +0100)]
add mul test cases
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:37:43 +0000 (19:37 +0100)]
add div test cases
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:18:06 +0000 (19:18 +0100)]
add mmu test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:13:27 +0000 (19:13 +0100)]
add CR test cases
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:09:16 +0000 (19:09 +0100)]
update install comments
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:06:04 +0000 (19:06 +0100)]
update README
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:05:16 +0000 (19:05 +0100)]
update README
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:03:45 +0000 (19:03 +0100)]
update README
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:01:05 +0000 (19:01 +0100)]
choose alternative name of pypi package
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 17:55:50 +0000 (18:55 +0100)]
add ShiftRotTestCases
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 16:47:24 +0000 (17:47 +0100)]
add a MASK32 function which offsets by 32 on the inputs
also fix ROTL32 so it selects value from its input