Eddie Hung [Wed, 19 Jun 2019 16:20:31 +0000 (09:20 -0700)]
Merge branch 'xaig' into xc7mux
Eddie Hung [Tue, 18 Jun 2019 19:47:12 +0000 (12:47 -0700)]
Remove iterator based Module::remove as per @cliffordwolf
Eddie Hung [Tue, 18 Jun 2019 19:37:46 +0000 (12:37 -0700)]
Remove unncessary header
Eddie Hung [Tue, 18 Jun 2019 19:32:42 +0000 (12:32 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Tue, 18 Jun 2019 19:19:22 +0000 (12:19 -0700)]
Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung [Tue, 18 Jun 2019 18:49:54 +0000 (11:49 -0700)]
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung [Tue, 18 Jun 2019 18:48:48 +0000 (11:48 -0700)]
Really permute Xilinx LUT mappings as default LUT6.I5:A6
Eddie Hung [Tue, 18 Jun 2019 18:35:21 +0000 (11:35 -0700)]
Revert "Fix (do not) permute LUT inputs, but permute mux selects"
This reverts commit
da3d2eedd2b6391621e81b3eaaa28a571e058f9d.
Eddie Hung [Tue, 18 Jun 2019 16:51:28 +0000 (09:51 -0700)]
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung [Tue, 18 Jun 2019 16:50:37 +0000 (09:50 -0700)]
Clean up
Eddie Hung [Tue, 18 Jun 2019 16:49:57 +0000 (09:49 -0700)]
Fix (do not) permute LUT inputs, but permute mux selects
Clifford Wolf [Tue, 18 Jun 2019 14:52:08 +0000 (16:52 +0200)]
Merge pull request #1086 from udif/pr_elab_sys_tasks2
Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks)
Eddie Hung [Tue, 18 Jun 2019 05:29:34 +0000 (22:29 -0700)]
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung [Tue, 18 Jun 2019 05:29:22 +0000 (22:29 -0700)]
Fix copy-pasta issue
Eddie Hung [Tue, 18 Jun 2019 05:25:14 +0000 (22:25 -0700)]
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung [Tue, 18 Jun 2019 05:24:35 +0000 (22:24 -0700)]
Permute INIT for +/xilinx/lut_map.v
Eddie Hung [Tue, 18 Jun 2019 02:14:41 +0000 (19:14 -0700)]
Simplify comment
Eddie Hung [Tue, 18 Jun 2019 01:25:35 +0000 (18:25 -0700)]
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung [Tue, 18 Jun 2019 00:06:01 +0000 (17:06 -0700)]
Update LUT7/8 delays to take account for [ABC]OUTMUX delay
Eddie Hung [Mon, 17 Jun 2019 20:33:47 +0000 (13:33 -0700)]
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung [Mon, 17 Jun 2019 20:32:08 +0000 (13:32 -0700)]
&scorr before &sweep, remove &retime as recommended
Eddie Hung [Mon, 17 Jun 2019 20:20:29 +0000 (13:20 -0700)]
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung [Mon, 17 Jun 2019 20:19:45 +0000 (13:19 -0700)]
Copy not move parameters/attributes
Eddie Hung [Mon, 17 Jun 2019 19:59:05 +0000 (12:59 -0700)]
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung [Mon, 17 Jun 2019 19:54:24 +0000 (12:54 -0700)]
Fix leak removing cells during ABC integration; also preserve attr
Eddie Hung [Mon, 17 Jun 2019 17:38:54 +0000 (10:38 -0700)]
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung [Sun, 16 Jun 2019 19:08:03 +0000 (12:08 -0700)]
Try -W 300
Eddie Hung [Mon, 17 Jun 2019 17:28:51 +0000 (10:28 -0700)]
Re-enable &dc2
Clifford Wolf [Sun, 16 Jun 2019 21:12:03 +0000 (23:12 +0200)]
Add timescale and generated-by header to yosys-smtbmc MkVcd
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Sun, 16 Jun 2019 19:08:03 +0000 (12:08 -0700)]
Try -W 300
Eddie Hung [Sun, 16 Jun 2019 19:05:07 +0000 (12:05 -0700)]
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung [Sun, 16 Jun 2019 16:34:26 +0000 (09:34 -0700)]
Cleanup
Eddie Hung [Sat, 15 Jun 2019 12:48:47 +0000 (05:48 -0700)]
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung [Sat, 15 Jun 2019 12:45:16 +0000 (05:45 -0700)]
Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O
Eddie Hung [Fri, 14 Jun 2019 21:20:36 +0000 (14:20 -0700)]
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung [Fri, 14 Jun 2019 20:34:40 +0000 (13:34 -0700)]
Leave breadcrumb behind
Eddie Hung [Fri, 14 Jun 2019 20:31:18 +0000 (13:31 -0700)]
Remove redundant condition
Eddie Hung [Fri, 14 Jun 2019 20:28:47 +0000 (13:28 -0700)]
Revert "Cleanup/optimise toposort in write_xaiger"
This reverts commit
1948e7c846ea318d003148974945d917701a4452.
Restores old toposort with optimisations
Eddie Hung [Fri, 14 Jun 2019 20:28:47 +0000 (13:28 -0700)]
Revert "Cleanup/optimise toposort in write_xaiger"
This reverts commit
1948e7c846ea318d003148974945d917701a4452.
Restores old toposort with optimisations
Eddie Hung [Fri, 14 Jun 2019 20:15:12 +0000 (13:15 -0700)]
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung [Fri, 14 Jun 2019 20:10:46 +0000 (13:10 -0700)]
Update comment
Eddie Hung [Fri, 14 Jun 2019 20:08:38 +0000 (13:08 -0700)]
Check that whiteboxes are synthesisable
Eddie Hung [Fri, 14 Jun 2019 20:07:56 +0000 (13:07 -0700)]
Get rid of compiler warnings
Eddie Hung [Fri, 14 Jun 2019 19:50:30 +0000 (12:50 -0700)]
Update CHANGELOG
Eddie Hung [Fri, 14 Jun 2019 19:50:24 +0000 (12:50 -0700)]
Revert "Remove wide mux inference"
This reverts commit
738fdfe8f55e18ac7f315cd68c117eae370004ca.
Eddie Hung [Fri, 14 Jun 2019 19:46:52 +0000 (12:46 -0700)]
Merge branch 'xaig' into xc7mux
Eddie Hung [Fri, 14 Jun 2019 19:43:20 +0000 (12:43 -0700)]
As per @daveshah1 remove async DFF timing from xilinx
Eddie Hung [Fri, 14 Jun 2019 19:40:51 +0000 (12:40 -0700)]
Cover __APPLE__ too for little to big endian
Eddie Hung [Fri, 14 Jun 2019 19:29:46 +0000 (12:29 -0700)]
Update abc9 -D doc
Eddie Hung [Fri, 14 Jun 2019 19:28:01 +0000 (12:28 -0700)]
Enable "abc9 -D <num>" for timing-driven synthesis
Eddie Hung [Fri, 14 Jun 2019 19:25:06 +0000 (12:25 -0700)]
Further cleanup based on @daveshah1
Eddie Hung [Fri, 14 Jun 2019 19:00:02 +0000 (12:00 -0700)]
Resolve comments from @daveshah1
Eddie Hung [Fri, 14 Jun 2019 18:38:22 +0000 (11:38 -0700)]
Add XC7_WIRE_DELAY macro to synth_xilinx.cc
Eddie Hung [Fri, 14 Jun 2019 18:33:10 +0000 (11:33 -0700)]
Update delays based on SymbiFlow/prjxray-db
Eddie Hung [Fri, 14 Jun 2019 17:51:11 +0000 (10:51 -0700)]
Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
Eddie Hung [Fri, 14 Jun 2019 17:42:30 +0000 (10:42 -0700)]
Comment out dist RAM boxing on ECP5 for now
Eddie Hung [Fri, 14 Jun 2019 17:37:52 +0000 (10:37 -0700)]
Remove WIP ABC9 flop support
Eddie Hung [Fri, 14 Jun 2019 17:33:27 +0000 (10:33 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Fri, 14 Jun 2019 17:32:46 +0000 (10:32 -0700)]
Make doc consistent
Eddie Hung [Fri, 14 Jun 2019 17:29:27 +0000 (10:29 -0700)]
Cleanup
Eddie Hung [Fri, 14 Jun 2019 17:29:16 +0000 (10:29 -0700)]
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung [Fri, 14 Jun 2019 17:28:30 +0000 (10:28 -0700)]
Merge pull request #1097 from YosysHQ/dave/xaig_ecp5
Add ECP5 ABC9 support (to xaig branch)
Eddie Hung [Fri, 14 Jun 2019 17:27:30 +0000 (10:27 -0700)]
Cleanup
Eddie Hung [Fri, 14 Jun 2019 17:13:17 +0000 (10:13 -0700)]
Cleanup/optimise toposort in write_xaiger
Eddie Hung [Fri, 14 Jun 2019 17:11:34 +0000 (10:11 -0700)]
Remove extra semicolon
Eddie Hung [Fri, 14 Jun 2019 17:11:13 +0000 (10:11 -0700)]
Add TODO to parse_xaiger
David Shah [Fri, 14 Jun 2019 11:02:12 +0000 (12:02 +0100)]
ecp5: Add abc9 option
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Fri, 14 Jun 2019 00:02:58 +0000 (17:02 -0700)]
Optimise some more
Eddie Hung [Thu, 13 Jun 2019 23:28:11 +0000 (16:28 -0700)]
Move ConstEvalAig to aigerparse.cc
Eddie Hung [Thu, 13 Jun 2019 21:27:07 +0000 (14:27 -0700)]
Fix name clash
Eddie Hung [Thu, 13 Jun 2019 20:29:03 +0000 (13:29 -0700)]
More slimming
Eddie Hung [Thu, 13 Jun 2019 20:13:48 +0000 (13:13 -0700)]
Add ConstEvalAig specialised for AIGs
Eddie Hung [Thu, 13 Jun 2019 16:15:30 +0000 (09:15 -0700)]
Update CHANGELOG with "synth -abc9"
Eddie Hung [Thu, 13 Jun 2019 15:24:33 +0000 (08:24 -0700)]
Fix LP SB_LUT4 timing
Eddie Hung [Thu, 13 Jun 2019 15:22:22 +0000 (08:22 -0700)]
More accurate CHANGELOG
Serge Bazanski [Thu, 13 Jun 2019 10:14:37 +0000 (12:14 +0200)]
Merge pull request #829 from abdelrahmanhosny/master
Dockerfile for Yosys
Eddie Hung [Wed, 12 Jun 2019 23:54:12 +0000 (16:54 -0700)]
Update CHANGELOG
Eddie Hung [Wed, 12 Jun 2019 23:53:12 +0000 (16:53 -0700)]
Rip out all non FPGA stuff from abc9
Eddie Hung [Wed, 12 Jun 2019 23:52:09 +0000 (16:52 -0700)]
Fix spelling
Eddie Hung [Wed, 12 Jun 2019 23:51:37 +0000 (16:51 -0700)]
Revert "For 'stat' do not count modules with abc_box_id"
This reverts commit
b89bb744529fc8a5e4cd38522f86a797117f2abc.
Eddie Hung [Wed, 12 Jun 2019 23:33:05 +0000 (16:33 -0700)]
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
This reverts commit
2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing
changes made to
eaee250a6e63e58dfef63fa30c4120db78223e24.
Eddie Hung [Sun, 28 Apr 2019 19:36:04 +0000 (12:36 -0700)]
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung [Wed, 12 Jun 2019 23:04:33 +0000 (16:04 -0700)]
Be more precise when connecting during ABC9 re-integration
Eddie Hung [Wed, 12 Jun 2019 22:55:02 +0000 (15:55 -0700)]
Remove unnecessary undriven_bits.insert
Eddie Hung [Wed, 12 Jun 2019 22:52:49 +0000 (15:52 -0700)]
Remove hacky wideports_split from abc9
Eddie Hung [Wed, 12 Jun 2019 22:47:39 +0000 (15:47 -0700)]
Fix compile errors when #if 1 for debug
Eddie Hung [Wed, 12 Jun 2019 22:45:46 +0000 (15:45 -0700)]
parse_xaiger to cope with inouts
Eddie Hung [Wed, 12 Jun 2019 22:44:30 +0000 (15:44 -0700)]
write_xaiger to preserve POs even if driven by constant
Eddie Hung [Wed, 12 Jun 2019 22:43:43 +0000 (15:43 -0700)]
Add a couple more tests
Eddie Hung [Wed, 12 Jun 2019 17:18:44 +0000 (10:18 -0700)]
Do not call abc9 if no outputs
Eddie Hung [Wed, 12 Jun 2019 17:00:57 +0000 (10:00 -0700)]
More write_xaiger cleanup
Eddie Hung [Wed, 12 Jun 2019 16:53:14 +0000 (09:53 -0700)]
Cleanup write_xaiger
Eddie Hung [Wed, 12 Jun 2019 16:40:51 +0000 (09:40 -0700)]
Consistency
Eddie Hung [Wed, 12 Jun 2019 16:34:41 +0000 (09:34 -0700)]
Reduce diff with master
Eddie Hung [Wed, 12 Jun 2019 16:29:30 +0000 (09:29 -0700)]
Remove abc_flop{,_d} attributes from ice40/cells_sim.v
Eddie Hung [Wed, 12 Jun 2019 16:21:52 +0000 (09:21 -0700)]
Fix spacing
Eddie Hung [Wed, 12 Jun 2019 16:20:46 +0000 (09:20 -0700)]
Remove wide mux inference
Eddie Hung [Wed, 12 Jun 2019 16:14:27 +0000 (09:14 -0700)]
Merge branch 'xc7mux' into xaig
Eddie Hung [Wed, 12 Jun 2019 16:14:12 +0000 (09:14 -0700)]
Merge branch 'xc7mux' of github.com:YosysHQ/yosys into xc7mux
Eddie Hung [Wed, 12 Jun 2019 16:13:53 +0000 (09:13 -0700)]
Typo: wire delay is -W argument
projects / yosys.git / log