mem-ruby: Standardize Bloom Filter deletion support

Standard Bloom Filters do not support element deletion by default,
however some variants do. Allow calling the unset function with
all filters, and do nothing by default.

Change-Id: Icf4b0f8b997c4c70fa714b2576474810275db78b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18730
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-ruby: Bloom filters - Remove in/decrement

Increment and decrement were functions created to supply the
different naming convention used by the counting bloom filter.
They were removed, and the set and unset functions were used
in their place instead, as in the other filters.

Change-Id: I45732bdfa3083add0a975f374a0f3560003e9d09
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18729
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

dev-arm: Use global import path for MemObject

Change-Id: I66e0ca6df689ec6aeb831ef5545e8e5842bb0418
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19348
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add argument to Coroutine class to not run on creation

In some cases, the point where you create a Coroutine is not the same as
where you want to start running it (and want it to switch back to). This
leads to the unnecessary overhead of switching in and out of the
Coroutine. This change adds an optional boolean argument to the
constructor for the Coroutine class to allow for overriding the default
behavior of running the Coroutine upon creation, which in specific cases
can be used to avoid the unnecessary overhead and improve simulator
performance.

Change-Id: I044698f85e81ee4144208aee30d133bcb462d35d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18588
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, arm: Update miscRegs in getTE

Normally, a translation will start via translateTiming/functional
which will check if the miscRegs have been updated and if so,
will update the TLB state accordingly.  However, in a 2 stage
system, if there is a hit in stage 1, the resulting IPA will be
sent to the S2-TLB for translation via a getTE() function call
(via the stage2_lookup object).  This will cause the state of the
S2-TLB to be out of sync.

Change-Id: I117e4032fc76d7d31f4f999887b5573a7e5811e6
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14995
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

dev-arm: Remove un-needed Q_CONS_PROD_MASK macro

Change-Id: I858d7eea088bbdd2dc12123e21e59991c896597f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19310
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: drain implementation for SMMUv3

SMMUv3 is drained when (1) no SMMU translations are pending
on any of its slave interfaces and (2) no commands are stored
in the Command Queue waiting to be processed.

Change-Id: I81cef5fd821fa5e509e130af02aece5239493df5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19309
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: pending SMMU transl update on constructor/destructor

Change-Id: I6f61651123aab129cfbe5a88aa6355cd21544a5e
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19308
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Fix NULL dram-lowp regressions

The problem arises since there are some scripts (like NULL dram
regressions) which are making use of MemConfig.py without using
Opions.py so they won't have the new enable-dram-powerdown option

Change-Id: Id9769cce2e8a25b57da76f07eeebd279a6e00440
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19268
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Add support for exporting static class methods from c++

This change adds support for exporting static methods in a c++
SimObject from the coressponsing python wrapper class. This will allow
us to define and use c++ methods without the need to instantiate an
object of the corresponding class.

Change-Id: Iaf24c1aa6f20feb5c91241f46ec8db005a6a0c0c
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19168
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: dot_writer fixup

In large configs the tooltip may be greater then the maximum line
size graphviz supports when parsing the dot file (typically 16k).
Adding '/' causes graphviz to break the string in multiple lines
while parsing and works around this limitation.

Change-Id: I16a0030127de4165080de97f5213309eed9fdeca
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19208
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Fix AddrRange legacy ParamValue wrapper

This change fixes a bug that would manifest if a user would
instantiate an AddrRange ParamValue using the kwargs 'intlvBits' and
'intlvHighBit' without specifying the optional 'xorHighBit'.

Change-Id: I2091c432234df9cf907d52af6ba7f0cadd8c37a8
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19248
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Move the memacc_code before op_wb in fp loads

This is trying to fix the bug that arises when a memory exception
is generated during a fp flavoured load (A memory load targeting
a SIMD & FP register).
With the previous template a fault was not stopping the register
value to be modified (wrong)

if (fault == NoFault) {
    fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
    %(memacc_code)s;
}

if (fault == NoFault) {
    %(op_wb)s;
}

The patch introduces a Load64FpExecute template which is moving the
register write (memacc_code) just before the op_wb

Change-Id: I1c89c525dfa7a4ef489abe0872cd7baacdd6ce3c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19228
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Reapply GICv3 changes that were lost during refactoring

The GICv3 code refactoring performed by:

https://gem5-review.googlesource.com/c/public/gem5/+/16484

reverted the following patches

https://gem5-review.googlesource.com/c/public/gem5/+/16544
https://gem5-review.googlesource.com/c/public/gem5/+/16545/3

This commit is reintroducing them

Change-Id: I2c875c11570ed66ec9203449446faca3864c64d6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19229
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: AddrRange does not merge single interleaved ranges

AddrRange does not attempt to merge interleaved address ranges if it
has only one of the ranges.

This is needed to allow XBars to accept request targeting only one
part of a interleaved address range. A use case for this would be
modeling distributed LLCs in which a XBar is used solely to
encapsulate the snoop filter of a single LLC slice.

Change-Id: If71c9cf1444ee11916611afb51eab3a4f1d93985
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18788
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Additional TrafficGen stats

Additional stats to keep track of read/write latencies and throughput.

Change-Id: I7684cd33cf68fffdef4ca9c3a6db360a0f531c18
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18418
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Limit TrafficGen outstanding reqs

Parameter to limit the number of requests waiting for a response.

Change-Id: I6cf9e8782a06ae978fb66f7c4278f4c9e9980c79
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18417
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: TrafficGen as BaseCPU

TrafficGen has additional attributes to behave like a BaseCPU. Python
scripts that expect sim. objects derived from BaseCPU can now be used with
TrafficGen without additional modifications.

Change-Id: Iee848b2ba0ac1851c487b1003da9bd96253d291a
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18416
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Fix cxx_ini_parse for ScopedEnum

Change-Id: I69534bbbc16b2d24a65fa1dee4926f213c3618ef
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19152
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Fix read_config to work with new AddrRange serialization

Change-Id: I122c77c34c2f8c75f8b32682be858f651112ce89
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19151
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add python3 workarounds in read_config

Change-Id: Ib065f41b87e5ada9535b9c2645067162aa69234b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19150
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Add binding for the new AddrRange c++ constructor

Change-Id: I5b3fb59a11d8587a753759310dd3b2748ac13a0b
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19132
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Extend unit tests for AddrRange

Change-Id: Ia154c3a17c3c8254a0e3d622568ac34f0d62fc9e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19131
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Extend AddrRange to support more flexible addressing

Previously an AddrRange could express interleaving using a number of
consecutive bits and in additional optionally a second number of
consecutive bits. The two sets of consecutive bits would be xored and
matched against a value to determine if an address is in the
AddrRange. For example:

sel[0] = a[8] ^ a[12]
sel[1] = a[9] ^ a[13]
where sel == intlvMatch

This change extends AddrRange to allow more flexible interleavings
with an abritary number of set of bits which do not need be
consecutive. For example:

sel[0] = a[8] ^ a[11] ^ a[13]
sel[1] = a[15] ^ a[17] ^ a[19]
where sel == intlvMatch

Change-Id: I42220a6d5011a31f0560535762a25bfc823c3ebb
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19130
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

base: Fix ctz32 for systems where unsigned int is not 32bit

The implementation of ctz32 uses __builtin_ctz to count the number of
trailing zeros and therefore makes the assumption that an unsigned int
is 32bit. This change checks whether that's the case and if not it
uses __builtin_ctzl instead.

Change-Id: Ic3ed3ada25fd0a93c7eb91d75b954e9924bdbb77
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19129
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add function to count trailing zeros in a 64-bit integer

Change-Id: Iaad0679b403bc5015ffeacbf7284313e41a36cd0
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19128
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: allow passing arbitrary CCFLAGS and LDFLAGS from the CLI

The flags may be passed as:

scons CCFLAGS_EXTRA='-Wno-error -pedantic' \
      LDFLAGS_EXTRA='-g -g' build/<arch>/gem5.opt

The initial motivation for this commit is to help disable warning that
have become errors while bisecting.

scons orders the flags by Append call order, and ideally these flags
should be added last to override the others, since the last GCC flags
take precedence. However I haven't found a simple way to put them at
the very end.

Change-Id: Ida24dfb9604d88b99f113392ab5e47d578ba7259
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19048
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: implement VMINNM scalar thumb

VMINNM was implemented at Iabbbca2932557cf6c98ce36690c385c3ddf39ed8 but
the thumb scalar encoding was missing. This patch implements it.

Change-Id: Ia29ec77dbd82f6be6b3d040a0e737794f52c33bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19108
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Provide a getter for Fiber::started boolean variable

This can be used to check if the fiber has started its execution.

Change-Id: Ie9222b8076756363c9f82c1333c76a352bcaf817
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18648
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Rename TestFiber into SwitchingFiber

This is done since TestFiber is too generic and it is not the only
Fiber's testing subclass in the unit test

Change-Id: Idc386f487091ae9bdadae865090a6719a25583da
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19153
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix WalkerState,Descriptors default constructor

Those POD strutures are not initializing all members at construction.
This could lead to undefined behaviour

Change-Id: Iaa8afb126382b6bfbef686883a026262f24d5ca1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Javier Setoain <javier.setoain@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19149
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Implement a SMMUv3 model

This is an implementation of the SMMUv3 architecture.

What can it do?
- Single-stage and nested translation with 4k or 64k granule.  16k would
  be straightforward to add.
- Large pages are supported.
- Works with any gem5 device as long as it is issuing packets with a
  valid (Sub)StreamId

What it can't do?
- Fragment stage 1 page when the underlying stage 2 page is smaller.  S1
  page size > S2 page size is not supported
- Invalidations take zero time. This wouldn't be hard to fix.
- Checkpointing is not supported
- Stall/resume for faulting transactions is not supported

Additional contributors:
- Michiel W. van Tol <Michiel.VanTol@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Change-Id: Ibc606fccd9199b2c1ba739c6335c846ffaa4d564
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19008
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Option to toggle DRAM low-power states

Adding an option to enable DRAM low-power states. The low power
states can have a significant impact on application performance
(sim_ticks) on the order of 2-3x, especially for compute-gpu apps.
The options allows for it to easily be enabled/disabled to compare
performance numbers. The option is disabled by default.

Change-Id: Ib9bddbb792a1a6a4afb5339003472ff8f00a5859
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18548
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Enable set size increase

Add NUMBER_BITS_PER_SET environment variable to control
the size of the bitmask in Set.hh (default=64).
Necessary for configs which require >64 instances of a given
machine type. This can be set in the build_opts file, e.g.
by adding the following line:
NUMBER_BITS_PER_SET = <number>

Change-Id: I314a3cadca8ce975fcf4a60d9022494751688e88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18968
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Fix missing headers to CircularQueue

CircularQueue is currently throwing compilation errors when creating
a derived class.

assert() needs <cassert>
ptrdiff_t needs <cstddef>
(u)intX_t need <cstdint>
random_access_iterator_tag needs <iterator>
is_same, enable_if and others need <type_traits>

Change-Id: I77a78e7b13f7a8b8e7e8b2b872065d78d1ab815a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19089
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

Revert "mem-cache: Remove writebacks packet list"

This reverts commit bf0a722acdd8247602e83720a5f81a0b69c76250.

Reason for revert: This patch introduces a bug:

The problem here is that the insertion of block A may cause the
eviction of block B, which on the lower level may cause the
eviction of block A. Since A is not marked as present yet, A is
"safely" removed from the snoop filter

However, by reverting it, using atomic and a Tags sub-class that
can generate multiple evictions at once becomes broken when using
Atomic mode and shall be fixed in a future patch.

Change-Id: I5b27e54b54ae5b50255588835c1a2ebf3015f002
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19088
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)

Described by the following article:
  Jiménez, D. "Multiperspective perceptron predictor."
  Championship Branch Prediction (CBP-5) (2016).

Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: fix movsd bug on %xmm register

The movsd instruction should zero out half the register, but
does not do it. This changeset adds the necessary microop to
the instruction to cause correct behavior.

Change-Id: I5278da3634c78a97ed0586f687a36c6dc5a34c60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19068
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

config, arm: memoryMode test

Commit 9a13acaa367769c38859342de9bc35aac59a6710 doesn't comply with the
same behaviour. The conditional test the memory mode on the same cluster,
while it should test the other cluster.

Change-Id: If3a7863f0905e66a548001d8e74689f5dd07179c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17748
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm: Fix decoding of CRC32 instructions in thumb32

The CRC32 and CRC32C instructions are incorrectly decoded in thumb32
mode according to the latest manual:
https://developer.arm.com/docs/ddi0597/latest/top-level-encodings-for-t32/16-bit#dpint_2r

Change-Id: I9c6684f1ec7fe14d3b4cdf13f117a9819e046578
Signed-off-by: Chun-Chen TK Hsu
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19028
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: Increase LSQ buffer sizes to match max vector length

Change-Id: I5890c7cfa147125ce3389001f85d56d4b5a9911d
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13525
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch-arm: Treat SVE prefetch instructions as no-ops

Change-Id: Ife0424e274dd65d6dc4f6e5cc5e37d17b03be0d8
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13522
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Add initial support for SVE gather/scatter loads/stores

Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13521
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Fix rescheduling of progress check events

noRequestEvent needs to be rescheduled on recvRetry, otherwise the timeout
may be triggered even though packets are being eventually sent.
noResponseEvent scheduling is also fixed. This timeout should not be
active when we are not expecting a response.

Change-Id: If9edb75b5b803caf9f99bf41ea3948b15a3f3d71
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18793
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Add include guards to auto-gen. decode header

Change-Id: I03bfc9035b82bc1a42e799cf645d43cb5dafb4cb
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18911
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu-o3: Add support for pinned writes

This patch adds support for pinning registers for a certain number of
consecutive writes.  This is only relevant for timing CPU models
(functional-only models are unaffected), and it is primarily needed to
provide a realistic execution model for micro-coded operations whose
microops can write to non-overlapping portions of a destination
register, e.g. vector gather loads.  In those cases, this mechanism
can disable renaming for a sequence of consecutive writes, thus making
the resulting execution more efficient: allocating a new physical
register for each microop would introduce a read-modify-write chain of
dependencies, while with these modifications the microops can write
back in parallel.

Please note that this new feature is only leveraged by O3CPU for the
time being.

Additional authors:
- Gabor Dozsa <gabor.dozsa@arm.com>

Change-Id: I07eb5fdbd1fa0b748c9bdc1174d9f330fda34f81
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13520
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

These two functions were performing the same function but had two
different names for historical reasons. This change merges them
together, keeping the getVirtProxy name to be consistent with the
getPhysProxy method used to get a non-translating proxy port.

Change-Id: Idd83c6b899f9343795075b030ccbc723a79e52a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18581
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Store the translating proxy with the same pointer in SE or FS mode.

Only one is active at a time, so they can share the same pointer.

Change-Id: Ie4ae1f0ffbf9448f6730f9c7d072bc85d6d423da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18580
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

cpu, sim: Return PortProxy &s from all the proxy accessors.

This is a step towards merging the accessors for SE and FS modes.

Change-Id: I76818ab88b97097ac363e243be9cc1911b283090
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18579
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

kern: Replace an explicitly instantiated port proxy with one from the tc.

That avoids having to know what type of proxy to create.

Change-Id: I311e770ab720061b52f29df0dcc2273e028aa34a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18578
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.

Al(most) all of the interesting differences between the two classes
have been removed. There are some control methods which are still
specific to each type which may require treating them as their true
type, but most code that consumes them doesn't need to worry about
which is which.

Change-Id: Ie592676f1e496c7940605b66e55cd7fae18e59d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18577
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Remove the now unused Copy* methods from the FS port proxy.

Change-Id: Ie433a9e4c9ee748911060eb7b1b47e617aa297a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18576
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.

This expands those functions into code which extracts the virt proxy
and then uses the appropriate method on it. This has two benefits.
First, the Copy* functions where mostly redundant wrappers around the
methods the proxy port already had. Second, using them forced a
particular port which might not actually be what the user wanted.

Change-Id: I62084631dd080061e3c74997125164f40da2d77c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18575
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: const for loader's loadSection param

The port proxy can be declared as a reference to a const proxy
rather than just a reference to a proxy.

Change-Id: I4640b0c5f33e2334c1e7630131f78607ced40a34
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12301
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Added correct return type for ROB::countInsts

- return size_t (unsigned) according to the .size() return type
- fixed typo in doc (source of warning with some compilers)

Change-Id: I48ee2e317cf41011a6fcb5ca45aef67e75329bfa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18948
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Accuracy-based rate control for prefetchers

Added a mechanism to control the number of prefetches generated
based in the effectiveness of the prefetches generated so far.

Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18808
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

sim-se: add a release parameter to Process.py

Set the default release to that single value for all ISAs.

glibc has checks for the kernel version based on uname, and refuses
to start any syscall emulation programs if those checks don't pass with
error:

FATAL: kernel too old

The ideal solution to this problem is to actually implement all missing
system calls for the required kernel version and bumping the release
accordingly.

However, it is very hard to implement all missing syscalls and verify
compliance.

Previously, we have simply bumped the version manually from time to
time when major glibc versions started breaking.

This commit alleviates the problem in two ways.

Firstly, having a single kernel version for all versions means that it is
easier to bump all versions at once.

Secondly, it makes it is possible to set the release with a parameter,
which in turn can be set from the command line with:

se.py --param 'system.cpu[:].workload[:].release = "4.18.0"'

Change-Id: I9e3c31073bfe68735f7b0775c8e299aa62b98222
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17849
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Support for page crossing prefetches

Prefetchers can now issue hardware prefetch requests that go beyond
the boundaries of the system page. Page crossing references will need
to look up the TLBs to be able to compute the physical address to be
prefetched.

Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14620
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Add a readString method to the PortProxy which takes a char *.

This version takes a char * instead of an std::string &, and a maximum
length to fill in like strncpy. This is intended to be a replacement
for the CopyStringOut function.

Change-Id: Ib661924a3fa7e05761d572ffecbe2c0cc8659d48
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18574
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Use a const T & in write<> to avoid an unnecessary copy.

If the type T is complex/large, the it makes sense to access it in place
and not copy it and then not modify it.

Change-Id: Idd24be4fbba636375637ff72b1ba5ee32eb76215
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18573
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.

Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem, arm: Replace the pointer type in PortProxy with void *.

The void * type is for pointers which point to an unknown type. We
should use that when handling anonymous buffers in the PortProxy
functions, instead of uint8_t * which points to bytes.

Importantly, C/C++ doesn't require you to do any casting to turn an
arbitrary pointer type into a void *. This will get rid of lots of
tedious, verbose casting throughout the code base.

Change-Id: Id1adecc283c866d8e24524efd64f37b079088bd9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18571
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem, arm: Move some helper methods into the base PortProxy class.

These were originally in the SETranslatingPortProxy class, but they're
not specific to SE mode in any way and are an unnecessary divergence
between the SE and FS mode translating port proxies.

Change-Id: I8cb77531cc287bd15b2386410ffa7b43cdfa67d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18570
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm, mem: Move the SecurePortProxy subclass into it's own file.

The idea of a "secure" memory area/access is specific to ARM and
shouldn't be in the common mem directory, although it's built in to the
generic memory protocol at this point.

Regardless, it should minimially be in its own file like the virtual
and physical port proxy classes are.

Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18569
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Parameterize coherent xbar sanity checks

Parameters can be used to change coherent xbar limits for the routing
table and outstanding snoops. We need the ability to tweak these values
as the current defaults may be violated in simulations with large core
counts.

Change-Id: Idb64b8c105683d02d8beba5bce13b815181ba824
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18789
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Snoop filter support for large systems

Changed SnoopMask to use std::bitset instead of uint64 so we can simulate
larger systems without having to workaround limitations on the number of
ports. No noticeable performance drop was observed after this change.
The size of the bitset is currently set to 256 which should fit most
needs.

Change-Id: I216882300500e2dcb789889756e73a1033271621
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18791
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add warn_if_once macro

Change-Id: Ie68f3b07a35ed2e6b0eee20b3b34050542fcdc6c
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18420
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Remove assert causing issues with x86 Linux boot

Change-Id: I5e0b189ced0dd59ac6dbbb2c498c068e132b9b93
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18910
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix fallthrough when trapping at EL2

This had been caused by the introduction of GICv3 registers trapping in
commit 32a23114c14cebc5ec0067ac739144b50e412219

Change-Id: I5073e2891f3ff5c5a9e05d3456dad6f4f8ffba0d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18909
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Trap virtual accesses to GICv3 SGI registers

According to GICv3 documentation, a virtual write (which means
HCR.IMO/FMO = 1) to ICC_SGI0R_EL1, ICC_SGI1R_EL1, ICC_ASGI1R_EL1 should
trap to EL2.

Change-Id: Ie7a952c2ff08590bb0c6e3854df567d714c2dc94
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17990
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Expose haveGicv3CPUInterface to the ISA interface

Change-Id: I36232b7618ad875983f34b741c51f12ddb9ae166
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17989
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Change mcrMrc15TrapToHyp signature

This patch is moving MiscRegs reading inside the mcrMrc15TrapToHyp
helper function. Rather than passing registers as arguments,
we are just passing a ThreadContext pointer

Change-Id: I6636dd3a4f92f757479d8a8d2c47de050a0b9eae
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17988
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Add invalid context id check on LLSC checks

If the request's address is in the LLSC list, its context Id was being
fetched unconditionally, which could cause the assert at
Request::contextId() to fail.

Change-Id: Iae9791f81c8fe9a7fcd842cd8ab7db18f34f2808
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18792
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: remove comment for code that moved

The page table code must have moved from this class, because
the comment no longer accurately reflects upon any of the
surrounding code.

Change-Id: If08a4298c1237a541d9875ddeaf3d3ecfd98e9db
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12300
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

dev-arm: Provide a GICv3 ITS Implementation

This patch introduces the GICv3 ITS module, which is in charge of
translating MSIs into physical (GICv3) and virtual (GICv4) LPIs.  The
patch is only GICv3 compliant, which means that there is no direct
virtual LPI injection (this also means V* commands are unimplemented)
Other missing features are:

* No 2level ITS tables (only flat table supported)

* Command errors: when there is an error in the ITS, it is
IMPLEMENTATION DEFINED on how the ITS behaves.  There are three possible
scenarios (see GICv3 TRM) and this implementation only supports one of
these (which is, aborting the command and jumping to the next one).
Furter patches could make it possible to select different reactions

* Invalidation commands (INV, INVALL) are only doing the memory table
walks, assuming the current Gicv3Redistributor is not caching any
configuration table entry.

Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: change syscall function signature

The system calls had four parameters. One of the parameters
is ThreadContext and another is Process. The ThreadContext
holds the value of the current process so the Process parameter
is redundant since the system call functions already have
indirect access.

With the old API, it is possible to call into the functions with
the wrong supplied Process which could end up being a confusing
error.

This patch removes the redundancy by forcing access through the
ThreadContext field within each system call.

Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: remove /sys from special paths

Currently, the open system call implementation in SE mode
treats /sys/ as a special path that is opened using a
special open handler. The ROC runtime, however, reads
several files in /sys/ that are supported via path
redirection. Here we remove /sys/ from the special files
so that the necessary files may be read via path
redirection.

Change-Id: Ifdab38ea1e6cc486ad43aec96b6e032fe63f137d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12127
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Move the marshal binary to the build directory

The current marshal binary is in $BUILD/python/ directory which makes
the dynamic linker fail to find shared libraries with rpath information
when the marshal is executing. Moving $BUILD/python/marshal to
$BUILD/marshal solves this problem.

This is because the marshal binary is built with the same flags as gem5
binary. And if one adds rpath information with add_local_rpath() in some
SConscripts, the marshal binary will also link to those shared libraries
and have the same rpath information.  So it must be in the same
directory as gem5 binary such that the dynamic linker could find those
shared libraries with the rpath information.

Signed-off-by: Chun-Chen TK Hsu
Change-Id: I98d9c3e0180abefe6b2b6a78ee5a96324038eb53
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18888
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added dot_writer for Ruby's network topology

Change-Id: Ic71ca7bc2eb4174d70afa368bc9cc987f3df89e9
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17548
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add multi-prefetcher adaptor

This patch adds a meta-prefetcher that enables gem5's cache models to
connect to multiple prefetchers. Sub-prefetchers still use the
probes-based interface and training can be controlled
independently. However, when the cache requests a prefetch packet, the
adaptor traverses the priority list of prefetchers and uses the first
prefetcher that is able to generate a prefetch.

Kudos to Mitch Hayenga for the original version of this patch.

Change-Id: I25569a834997e5404c7183ec995d212912c5dcdf
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18868
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Make the Process create function use the object loader mechanism.

This gets rid of the big mass of #if-s around headers and around the
code which creates an object file.

As a nice side bonus, this also means that in addition to supporting
multiple OS/arch combinations simultaneously, the object file loader
could support multiple ISAs simultaneously as well, since each could
load and set up its object file loaders indepedently and without the
base process classes knowledge/involvement.

Change-Id: I0a19ad06e30e9062a96d27f00b66756eb3a595ba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18631
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

x86: Add an object file loader for linux.

Change-Id: I283dd1f52fd020ad3c226eb00fc9216ee034c67f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18630
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Add an object file loader for linux and solaris.

Change-Id: I76bcbc06714f7d538f03a8311994a868de3640f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18629
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

riscv: Add an object file loader for linux.

Change-Id: I3accca91cc4e02fa8e3a1169590cbe6696cf05e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18628
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

power: Add an object file loader for linux.

Change-Id: I64ce81e98a6dc96754554d0fdcd7d16b8a2752d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18587
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>

mips: Add an object file loader for linux.

Change-Id: Icae6430a210076117cf2ceadce52d6efbe58a5f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18586
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Add an object file loader for linux and freebsd.

Change-Id: Ie5fd187a4897aa608ffc12278b23d3ee8c0f323c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18585
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

alpha: Add an object file loader for linux.

Change-Id: I91c4019567bdf74b2517fda597121a6ad107cb86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18584
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add a type for keeping track of object file loaders.

This avoids having a big pile of #if-s in sim/process.cc and allows
dynamically adding new types of object file loaders which might
recognize new arch/OS combinations.

Change-Id: Ie3b9c1aa2974d30a61afc4fcc529ffd6a74d43e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18583
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.

This code will be preserved through version control, but otherwise
creates clutter and will rot in place since it's never compiled.

Change-Id: Id265f6deac445116843956ea5cf1210d8127274e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Generalize FileSystemConfig for non se.py

This patch updates the FileSystemConfig so it works with more kinds of
config scripts (e.g., the Learning gem5 scripts).

There are 4 main changes:
- Added system as a parameter to the config_filesystem function so the
function can search the system for the number of CPUs instead of relying
on options from Options.py
- Instead of calling redirect_paths everywhere config_filesystem is
used, now it is implicitly called.
- Cleaned up the Ruby scripts a bit to remove redundant calls to
config_filesystem
- Added a config_filesystem call to the Ruby Learning gem5 script
(currently the only Learning gem5 script that requires it).

In the future, I think it would be better to move the config_filesystem
call into simulate.py, probably into the instantiate function. I tried to
use the per-CPU configuration parameters instead of options from
Options.py, but that's not possible until after the SimObject params
have been finalized in instantiate.

Change-Id: Ie6501a7435cfb3ac9d2b45be3722388b34063b1e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18848
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: implement VMINNM and VMAXNM scalar version

ARMv8.2 16-bit versions have not yet been implemented, but a placeholders
were created for them.

Refactor the nearby decoding tree to closely match the ARM spec A32 decode
table.

That piece of the tree can also be called from thumb which decodes it in
the same way, although the thumb decode table has a different terminology

The old code didn't match neither A32 or T32 terminologies, so it is
better to at least match one of them to help verify correctness.

Change-Id: Iabbbca2932557cf6c98ce36690c385c3ddf39ed8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18690
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: implement VMINNM and VMAXNM SIMD version

This instruction is backported from aarch64.

In order to use the existing fplibMinNum backend, we first move
VMIN and VPMIN to use fplib. Adding VMINNM is then trivial.

Change-Id: I404daabeb6079f60e51a648a06d5b3e54f1c24a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18689
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: rename operands to match spec in isa/formats/fp.isa

Matches ARM DDI 0487D.a decoding tables.

Change-Id: I48338ef956a04308d55d1022229ebe0962a8fe5d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18688
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: MOESI_CMP_dir cleanup

Removed unused states and actions

Change-Id: I3dc684c78d4b92d219e71522ddb706a13f9874d1
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18415
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-ruby: Cache latencies for MOESI_CMP_dir

Modified both L1 and L2 controllers to take into account the cache
latency parameters. Default values in the configuration script updated
as well.

Change-Id: I72bb8dd29ee0b02da06e1addf13b266fe4d1e979
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18414
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-ruby: Hit latencies defined by the controllers

Removed the icache/dcache hit latency parameters from the Sequencer.
They were replaced by the mandatory queue enqueue latency that is now
defined by the top-level cache controller. By default, the latency is
defined by the mandatory_queue_latency parameter. When the latency
depends on specific protocol states or on the request type, the protocol
may override the mandatoryQueueLatency function.

Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18413
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-ruby: Do not change blocked msg enqueue info

Updating the message counter and enqueue times when adding blocked
messages back to the queue does not make a lot of sense since these
messages are not new arrivals.
More importantly, this may lead to starvation. See the scenario below:

1) Request A for a blocked line X arrives
2) A is handled; X is blocked so A is stalled
3) Request B for X arrives; Reponse for X arrives
4) Response is handled; X unblocked; A added back to the request queue
5) B is handled ahead of A (since A's arrival was updated);
   X may become blocked again

If new requests keep comming for X, A may will be stalled forever.

Change-Id: Icad79f3f716a870e91cb3455437b8b3c35f130ac
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18412
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-ruby: Unique ranks for MOESI_CMP_dir in ports

Setting different values for the rank parameter for all inputs ports.
If left unset, it defaults to 0. This may cause issues since the rank is
used as an index in the controller's list of stalled buffers.

Change-Id: Ie8ff660b7450df959292311040aebf802657efcf
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18411
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-ruby: Change MOESI_CMP_Dir L2 addressing

L1 controller selects the L2 to message based on the assigned address
ranges instead of explicitly interleaving bits in the L1 controller. This
simplifies the L1 controller implementation a bit and allows for more
flexibility when changing the address->controller mapping.

Change-Id: Ie67999bb977566939432a5045f65dbd2da81816a
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18410
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>