write_json to not write contents (cells/wires) of whiteboxes

Ignore 'whitebox' attr in flatten with "-wb" option

Add "whitebox" attribute, add "read_verilog -wb"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update to ABC d1b6413

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #939 from YosysHQ/revert895

Revert #895 (mux-to-shiftx optimisation)

Revert #895

Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch

Revert "Recognise default entry in case even if all cases covered (fix for #931)"

Revert "Recognise default entry in case even if all cases covered (fix for #931)"

Merge pull request #936 from YosysHQ/README-fix-quotes

README: fix some incorrect quoting

README: fix some incorrect quoting.

Merge pull request #928 from litghost/add_xc7_sim_models

Add additional cells sim models for core 7-series primitives.

Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Merge pull request #933 from dh73/master

Fixing issues in CycloneV cell sim

Merge pull request #932 from YosysHQ/eddie/fixdlatch

Recognise default entry in case even if all cases covered (fix for #931)

Fixing issues in CycloneV cell sim

Add default entry to testcase

Recognise default entry in case even if all cases covered (#931)

Fix LUT6_2 definition.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Add additional cells sim models for core 7-series primatives.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Fix a few typos

Merge pull request #919 from YosysHQ/multiport_transp

memory_bram: Fix multiport make_transp

memory_bram: Fix multiport make_transp

Signed-off-by: David Shah <dave@ds0.me>

Add "read_ilang -lib"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Added missing argument checking to "mutate" command

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #913 from smunaut/fix_proc_mux

proc_mux: Fix crash when trying to optimize non-existant mux to shiftx

proc_mux: Fix crash when trying to optimize non-existant mux to shiftx

last_mux_cell can be NULL ...

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

Merge pull request #912 from YosysHQ/bram_addr_en

memory_bram: Consider read enable for address expansion register

Merge pull request #910 from ucb-bar/memupdates

Refine memory support to deal with general Verilog memory definitions.

memory_bram: Consider read enable for address expansion register

Signed-off-by: David Shah <dave@ds0.me>

Merge pull request #895 from YosysHQ/pmux2shiftx

RFC: Add a pmux-to-shiftx optimisation to proc_mux

Refine memory support to deal with general Verilog memory definitions.

Merge pull request #907 from YosysHQ/clifford/fix906

Build Verilog parser with -DYYMAXDEPTH=100000

Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #901 from trcwm/libertyfixes

Libertyfixes: accept superfluous ; at end of group.

Merge pull request #903 from YosysHQ/bram_reset_transp

memory_bram: Reset make_transp when growing read ports

memory_bram: Reset make_transp when growing read ports

Signed-off-by: David Shah <dave@ds0.me>

Liberty file parser now accepts superfluous ;

Liberty file parser now accepts superfluous ;

Liberty file parser now accepts superfluous ;

Add "read -verific" and "read -noverific"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "rename -output"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve "rename" help message

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "cutpoint -undef"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "hdlname" attribute

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix "verific -extnets" for more complex situations

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "cutpoint" pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Create one $shiftx per bit in width

Merge pull request #896 from YosysHQ/transp_fixes

memory_bram: Fix multiclock make_transp

Merge pull request #897 from trcwm/libertyfixes

Liberty parser: Accept ranges [A:B], and ignore missing ';'.

spaces -> tabs

EOL is now accepted as ';' replacement on lines that look like: feature_xyz(option)

Updated the liberty parser to accept [A:B] ranges (AST has not been updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.

memory_bram: Fix multiclock make_transp

Signed-off-by: David Shah <dave@ds0.me>

Add a pmux-to-shiftx optimisation to proc_mux

Add "mutate -none -mode", "mutate -mode none"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "mutate -s <filename>"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #893 from YosysHQ/clifford/btormeminit

Memory init support in write_btor

Add support for memory initialization to write_btor

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix BTOR output tags syntax in writye_btor

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #889 from YosysHQ/clifford/fix888

Fix mem2reg handling of memories with upto data ports

Merge pull request #890 from YosysHQ/clifford/fix887

Trim init attributes when resizing FFs in "wreduce"

Merge pull request #891 from YosysHQ/xilinx_keep

xilinx: Add keep attribute where appropriate

xilinx: Add keep attribute where appropriate

Signed-off-by: David Shah <dave@ds0.me>

Trim init attributes when resizing FFs in "wreduce", fixes #887

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix mem2reg handling of memories with upto data ports, fixes #888

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve "read_verilog -dump_vlog[12]" handling of upto ranges

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve read_verilog debug output capabilities

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #885 from YosysHQ/clifford/fix873

Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873

Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #808 from eddiehung/read_aiger

Add new read_aiger frontend

Merge https://github.com/YosysHQ/yosys into read_aiger

Add author name

Merge pull request #884 from zachjs/master

fix local name resolution in prefix constructs

fix local name resolution in prefix constructs

Update issue template

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update issue template

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #877 from FelixVi/master

Add note about test requirements in README

Add note about test requirements in README

Improve mix of src/wire/wirebit coverage in "mutate -list"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #876 from YosysHQ/clifford/fmcombine

Add fmcombine pass

Add "fmcombine -fwd -bwd -nop"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add fmcombine pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #875 from YosysHQ/clifford/mutate

Add "mutate" pass

Disable realmath tests

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improvements in "mutate" list-reduce algorithm

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "mutate -cfg", improve pick_cover behavior

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add a strictly coverage-driven mutation selection strategy

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve "mutate" wire coverage metric

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add more mutation types, improve mutation src cover

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix smtbmc.py handling of zero appended steps

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "mutate" command DB reduce functionality

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add hashlib "<container>::element(int n)" methods

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "mutate -mode inv", various other mutate improvements

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add basic "mutate -list N" framework

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #874 from YosysHQ/clifford/andopt

Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327

Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #872 from YosysHQ/clifford/pmuxfix

Improve handling of "full_case" attributes

Improve handling of "full_case" attributes

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix a syntax bug in ilang backend related to process case statements

Signed-off-by: Clifford Wolf <clifford@clifford.at>