mesa: trim down #includes in compiler.h

Don't include stuff we don't need.  Fix a few #includes elsewhere to
keep thing building.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

r300g: remove dependency on compiler.h

It only needs typical stdio.h and stdlib.h functions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

mesa: don't include limits.h in compiler.h

Not needed.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

mesa: don't include float.h in compiler.h

Not needed.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

mesa: only include ctype.h where it's used

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

mesa: include stdarg.h only where it's used

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

mesa: remove M_PI, M_E, M_LOG2E macro definitions

Should be defined in math.h.  If not, we can add them to c99_math.h

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

glsl: #include c99_math.h instead of core.h

We only need the M_LOG2E definition.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

gallium: whitespace, comment formatting fixes in p_defines.h

Just to keep things consistent.

Reviewed-by: José Fonseca <jfonseca@vmware.com>

util: add debug_print_bind_flags() debug helper

Reviewed-by: José Fonseca <jfonseca@vmware.com>

gallium: renumber PIPE_BIND_ flags

Note that PIPE_BIND_COMMAND_ARGS_BUFFER and PIPE_BIND_LINEAR were both
bit 21 before.

Reviewed-by: José Fonseca <jfonseca@vmware.com>

meta: In pbo_{Get,}TexSubImage don't repeatedly rebind the source tex

A layered PBO image is now interpreted as a single tall 2D image so
the z argument in _mesa_meta_bind_fbo_image is ignored. Therefore this
was just redundantly rebinding the same image repeatedly.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

mesa: use fi_type in vertex attribute code

For 32-bit builds, floating point operations use x86 FPU registers,
not SSE registers.  If we're actually storing an integer in a float
variable, the value might get modified when written to memory.  This
patch changes the VBO code to use the fi_type (float/int union) to
store/copy vertex attributes.

Also, this can improve performance on x86 because moving floats with
integer registers instead of FP registers is faster.

Neil Roberts review:
- include changes on all places that are storing attribute values.
- check with and without -O3 compiler flag.
Brian Paul review:
- use fi_type type instead gl_constant_value type
- fix a bunch of nit-picks.
- fix compiler warnings

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82668
Signed-off-by: Marius Predut <marius.predut@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRT

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

i965: Pass pointer to miptree as function parameter in intel_horizontal_texture_alignment_unit

This will be used by next patch in the series.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

i965: Allocate texture buffer in intelTexImage

before calling _mesa_meta_pbo_TexSubImage(). This will be used in
later patches and will be required in Skylake to get the tile
resource mode of miptree before calling _mesa_meta_pbo_TexSubImage().

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

i965: Make a function to check the conditions to use the blitter

No functional changes in the patch. Just makes the code look cleaner.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

i965: Move the comment to the right place

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

i965: Fix condition to use Y tiling in blitter in intel_miptree_create()

Y tiling is supported in blitter on SNB+.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

meta: Pass null pointer for the pixel data to avoid unnecessary data upload

to a temporary pbo created in _mesa_meta_pbo_GetTexSubImage().

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

meta: Fix buffer object assignment to account for both pack and unpack bo's

create_texture_for_pbo() is shared by _mesa_meta_pbo_GetTexSubImage()
and _mesa_meta_pbo_TexSubImage() functions. So, we need to account
for both pack and unpack buffer objects.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

meta: Use GL_STREAM_READ for pbo created with GL_PIXEL_PACK_BUFFER

create_texture_for_pbo() is used by both _mesa_meta_pbo_GetTexSubImage()
and _mesa_meta_pbo_TexSubImage() functions with different PBO targets.
Use GL_STREAM_READ with GL_PIXEL_PACK_BUFFER and GL_STREAM_DRAW with
GL_PIXEL_UNPACK_BUFFER.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

meta: Add assertion check for ctx->Meta->SaveStackDepth

before using it for derefrencing.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

meta: Do power of two samples check only for samples > 0

otherwise samples=0 passes the check, which is invalid.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

glsl: Rewrite and fix min/max to saturate optimization.

There were some bugs, and the code was really difficult to follow. We
would optimize

   min(max(x, b), 1.0) into max(sat(x), b)

but not pay attention to the order of min/max and also do

   max(min(x, b), 1.0) into max(sat(x), b)

Corrects four shaders from Champions of Regnum that do

   min(max(x, 1), 10)

and corrects rendering of Mass Effect under VMware Workstation.

Cc: "10.4 10.5" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89180
Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

freedreno: drop ARRAY_SIZE macro

Since now ARRAY_SIZE has been added to util/macros.h.  Fixes a bunch of:

  freedreno_util.h:79:0: warning: "ARRAY_SIZE" redefined
   #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
   ^
  In file included from ../../../../src/gallium/include/pipe/p_compiler.h:36:0,
                   from ../../../../src/gallium/include/pipe/p_context.h:31,
                   from freedreno_context.h:32,
                   from freedreno_context.c:29:
  ../../../../src/util/macros.h:29:0: note: this is the location of the previous definition
   #  define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
   ^

Signed-off-by: Rob Clark <robclark@freedesktop.org>

i965: Don't force x-tiling for 16-bpp formats on Gen>7

Sandybridge doesn't support y-tiling for surface formats with 16 or
more bpp. There was previously an override to explicitly allow this
for Gen7. However, this restriction is also removed in Gen8+ so we
should use y-tiling there too.

This is important to do for Skylake which doesn't support x-tiling for
3D surfaces.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

glx: Fix returned values of GLX_RENDERER_PREFERRED_PROFILE_MESA

If the renderer supports the core profile the query returned incorrectly
0x8 as value, because it was using (1U << __DRI_API_OPENGL_CORE) for the
returned value.

The same happened with the compatibility profile. It returned 0x1
(1U << __DRI_API_OPENGL) instead of 0x2.

Internal DRI defines:
   dri_interface.h: #define __DRI_API_OPENGL       0
   dri_interface.h: #define __DRI_API_OPENGL_CORE  3

Those two bits are supposed for internal usage only and should be
translated to GLX_CONTEXT_CORE_PROFILE_BIT_ARB (0x1) for a preferred
core context profile and GLX_CONTEXT_COMPATIBILITY_PROFILE_BIT_ARB (0x2)
for a preferred compatibility context profile.

This patch implements the above translation in the glx module.

v2: Fix the incorrect behavior in the glx module

Cc: "10.3 10.4 10.5" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

dri/common: Update comment about driQueryRendererIntegerCommon

Since 87d3ae0b45b6b6bb50b583dafa55eb109449a005
driQueryRendererIntegerCommon handles __DRI2_RENDERER_PREFFERED_PROFILE
too.

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: add double support for packing varyings

Doubles are always packed, but a single double will never cross a slot
boundary -- single slots can still be wasted in some situations.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

common: Fix PBOs for 1D_ARRAY.

Corrects the way that _mesa_meta_pbo_TexSubImage and
_mesa_meta_pbo_GetTexSubImage handle 1D_ARRAY textures.  Fixes a failure in
the Piglit arb_direct_state_access/gettextureimage-targets test.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Tested-by: Laura Ekstrand <laura@jlekstrand.net>
Cc: "10.4, 10.5" <mesa-stable@lists.freedesktop.org>

common: Correct PBO 2D_ARRAY handling.

Changes PBO uploads and downloads to use a tall (height * depth) 2D texture
for blitting. This fixes the bug where 2D_ARRAY, 3D, and CUBE_MAP_ARRAY
textures are not properly uploaded and downloaded.

Removes the option to use a 2D ARRAY texture for the PBO during upload and
download.  This option didn't work because the miptree couldn't be set up
reliably.

v2: Review from Jason Ekstrand and Neil Roberts:
   -Delete the depth parameter from create_texture_for_pbo
   -Abandon the option to create a 2D ARRAY texture in create_texture_for_pbo

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.4, 10.5" <mesa-stable@lists.freedesktop.org>

common: Correct texture init for meta pbo uploads and downloads.

This moves the line setting immutability for the texture to after
_mesa_initialize_texture_object so that the initializer function will not
cancel it out. Moreover, because of the ARB_texture_view extension, immutable
textures must have NumLayers > 0, or depth will equal (0-1)=0xFFFFFFFF during
SURFACE_STATE setup, which triggers assertions.

v2: Review from Kenneth Graunke:
   - Include more explanation in the commit message.
   - Make texture setup bug fixes into a separate patch.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.4, 10.5" <mesa-stable@lists.freedesktop.org>

mesa: remove DEG2RAD macro

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove MAX_GLUSHORT, move MAX_GLUINT

The later is only used in one place in swrast.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: move signbit() macro to c99_math.h

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove unused isblank() function

Reviewed-by: Matt Turner <mattst88@gmail.com>

glcpp: remove unneeded #include of core.h

isblank() is not used in the code.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove sqrtf macro

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Remove redundant discard jumps.

With the previous optimization in place, some shaders wind up with
multiple discard jumps in a row, or jumps directly to the next
instruction.  We can remove those.

Without NIR on Haswell:
total instructions in shared programs: 5777258 -> 5775872 (-0.02%)
instructions in affected programs:     20312 -> 18926 (-6.82%)
helped:                                716

With NIR on Haswell:
total instructions in shared programs: 5773163 -> 5771785 (-0.02%)
instructions in affected programs:     21040 -> 19662 (-6.55%)
helped:                                717

v2: Use the CFG rather than the old instructions list.  Presumably
    the placeholder halt will be in the last basic block.

v3: Make sure placeholder_halt->prev isn't the head sentinel (caught
    twice by Eric Anholt).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: Optimize "if (cond) discard;" to a conditional discard.

st_glsl_to_tgsi and ir_to_mesa have handled conditional discards for a
long time; the previous patch added that capability to i965.

i965 (Haswell) shader-db stats:

Without NIR:
total instructions in shared programs: 5792133 -> 5776360 (-0.27%)
instructions in affected programs:     737585 -> 721812 (-2.14%)
helped:                                6300
HURT:                                  68
GAINED:                                2

With NIR:
total instructions in shared programs: 5787538 -> 5769569 (-0.31%)
instructions in affected programs:     767843 -> 749874 (-2.34%)
helped:                                6522
HURT:                                  35
GAINED:                                6

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965/fs: Handle conditional discards.

The discard condition tells us which channels we want killed.  We want
to invert that condition to get the channels that should survive (remain
live) in f0.1.  Emit a CMP to negate it.

Nothing generates these today, but that will change shortly.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

nir: Introduce nir_intrinsic_discard_if.

This is a conditional discard, which takes a boolean source.

Note that we don't generate ir_discard::condition today, so this
shouldn't break drivers (since none implement this intrinsic yet).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: Delete dead discard conditions in constant folding.

opt_constant_folding() already detects conditional assignments where the
condition is constant, and either deletes the assignment or the
condition.

Make it handle discards in the same fashion.

Spotted happening in the wild in Tropico 5 shaders.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: Handle conditional discards in lower_discard_flow().

This pass wasn't prepared to handle conditional discards.

Instead of initializing the "discarded" temporary to "true", set it to
the condition.  Then, refer to the variable for the condition, to avoid
duplicating the expression tree.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: Make ir_rvalue_visitor visit ir_discard::condition.

This was forgotten.

I omitted the NULL check since we don't check ir_assignment::condition
either.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: Make ir_validate check the type of ir_discard::condition.

Copy and pasted from the ir_if::condition handling, plus a NULL check.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

Revert "i965/fs: Remove force_writemask_all assertion for execsize < 8."

This reverts commit 0d8f27eab7b7e8b7a16e76aabd3f6a0ab4880497.

"This doesn't seem to be necessary." <- I was wrong!

Tested-by: Markus Wick <markus@selfnet.de>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Emit MOV(1) instructions with force_writemask_all.

Fixes rendering with Dolphin.

Tested-by: Markus Wick <markus@selfnet.de>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Optimize (gl_FrontFacing ? x : y) where x and y are ±1.0.

total instructions in shared programs: 5695356 -> 5689775 (-0.10%)
instructions in affected programs:     486231 -> 480650 (-1.15%)
helped:                                2604
LOST:                                  1

i965/fs/nir: Optimize integer multiply by a 16-bit constant.

Gen8+ support was just broken, since MUL now consumes 32-bits from both
sources. Fixes 986 piglit tests on my BDW.

total instructions in shared programs: 7753873 -> 7753522 (-0.00%)
instructions in affected programs:     28164 -> 27813 (-1.25%)
helped:                                77
GAINED:                                47

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/fs/nir: Optimize (gl_FrontFacing ? x : y) where x and y are ±1.0.

total instructions in shared programs: 7756214 -> 7753873 (-0.03%)
instructions in affected programs:     455452 -> 453111 (-0.51%)
helped:                                2333

Reviewed-by: Eric Anholt <eric@anholt.net>

nir/register: Add a parent_instr field

This adds a parent_instr field similar to the one for ssa_def.  The
difference here is that the parent_instr field on a nir_register can be
NULL if the register does not have a unique definition or if that
definition does not dominate all its uses.  We set this field in the
out-of-SSA pass so that backends can get SSA-like information even after
they have gone out of SSA.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

st/mesa: remove unused/broken function st_print_shaders

Reviewed-by: Dave Airlie <airlied@redhat.com>

st/mesa: remove struct qualifier from st_src_reg parameter

It's a class.  Silences MSVC warning.

mesa: remove INV_SQRTF() macro

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove ceilf, floorf macros

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove expf macro

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove logf macro

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove powf macro

Use the wrapper in c99_math.h if needed.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove unused exp2f, log2f, truncf wrappers

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove unused acosf, asinf, atan2f, etc. macros

Not used anywhere.  If any of these are needed, they should be added
to c99_math.h

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: replace FABSF with fabsf

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: replace FLOORF with floorf

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove unused CEILF macro

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: replace LOGF, EXPF with logf, expf

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: replace FREXPF, LDEXPF with frexpf, ldexpf

Start getting rid of some imports.h macros.  Use the c99 functions instead.

Reviewed-by: Matt Turner <mattst88@gmail.com>

targets/libgl-xlib: add src/ include dir to fix build

swrast: fix a few release build warnings

r600g,radeonsi: fix streamout after pipeline stats have been used

EVENT_TYPE_PIPELINESTAT_STOP disables streamout queries too.

Luckily, pipeline stats are enabled by default, so we don't even have to
emit EVENT_TYPE_PIPELINESTAT_START.

Tested on Hawaii, Bonaire, Redwood, RV730.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: small cleanup around current_rast_prim

- remove the last parameter of si_emit_rasterizer_prim_state
- remove the last unused parameter of si_emit_draw_registers
- use current_rast_prim in si_emit_draw_registers

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: set current_rast_prim in the right place

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: simplify obtaining a shader property in si_emit_clip_regs

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: only preload VertexID for the GS copy shader

The copy shader doesn't use any other preloaded VGPRs.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: dump the shader key when dumping shaders

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600g,radeonsi: cleanup of hex literals

0x3F800000 -> fui(1.0)
0x00000000 -> 0

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: set PA_SU_HARDWARE_SCREEN_OFFSET to 0

It was probably 0 already, but it doesn't hurt to set it.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

st/mesa: cleanup st_translate_geometry_program

Mostly dead code or code that didn't do anything.

Computing gs_num_outputs at the end was also useless. It's already set
correctly.

Reviewed-by: Dave Airlie <airlied@redhat.com>

st/mesa: inline st_free_tokens

Reviewed-by: Dave Airlie <airlied@redhat.com>

st/mesa: cleanup st_geometry_program structure

It's full of unused variables and variables only used
in st_translate_geometry_program.

Reviewed-by: Dave Airlie <airlied@redhat.com>

mesa: add a missing GS support check in GetActiveUniformBlockiv

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

r600g: Implement GL_ARB_draw_indirect for EG/CM

Requires Evergreen/Cayman and radeon kernel module
2.41.0 or newer.

Expected piglit fails due to hardware limitations:
* arb_draw_indirect-draw-arrays-prim-restart
  Restarts not applied for DrawArrays commands
* arb_draw_indirect-vertexid
  Base vertex offset is not included in vertex id

Marek: bump vgt_state num_dw by 3 (= space needed for one register write)

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

freedreno/a4xx: aniso filtering

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: update generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: add ARB_instanced_arrays support

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: handle index_bias (i.e. base_vertex)

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: add support for vertexid and instanceid sysvals

ir3 bits of it already in place from a3xx patch..

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: pass number of instances to draw

a4xx has it's own draw packet, so needs equivalent update to what a3xx
already got.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

docs: add news item and link release notes for mesa 10.4.5

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

docs: Add sha256 sums for the 10.4.5 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 41bdeda10210b8f1d358c04b25af2fbfe3335531)

Add release notes for the 10.4.5 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit a5c608e951c7d41be99a1f84450a1d5aaf6ccadd)

st/omx/dec/h264: fix picture out-of-order with poc type 0 v2

poc counter should be reset with IDR frame,
otherwise there would be a re-order issue with
frames before and after IDR

v2: add commit message

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: "10.4 10.5" <mesa-stable@lists.freedesktop.org>

install-lib-links: remove the .install-lib-links file

With earlier commit (install-lib-links: don't depend on .libs directory)
we moved the location of the file from .libs/ to the current dir.
Although we did not attribute that in the former case autotools was
doing us a favour and removing the file. Explicitly remove the file at
clean-local time, otherwise we'll end up with dangling files.

Cc: "10.3 10.4 10.5" <mesa-stable@lists.freedesktop.org>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

clover: Set appropriate flag defaults on memory object creation.

According to the spec when no device access mode is specified
clCreateBuffer and clCreateImage* should default to read/write, and
clCreateSubBuffer should default to the parent's device access flags.

clCreateSubBuffer is also required to inherit the host access and
host pointer flags from the parent.

Reviewed-and-tested-by: EdB <edb+mesa@sigluy.net>

clover: Add CL_MEM_HOST_* flag checks.

Those flags have been introduced in OpenCL 1.2.

[ Francisco Jerez: Rebase.  Throw CL_INVALID_VALUE from
  clCreateSubBuffer if the subbuffer drops access flags from its
  parent.  Use single function taking the set of allowed host access
  flags to validate memory transfer operands. ]

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

clover: Factor out memory object flags validation to a helper function.

And define constants for commonly used subsets of flags to save some
typing.

Reviewed-and-tested-by: EdB <edb+mesa@sigluy.net>

vc4: Update to current kernel sources.

New BO create and mmap ioctls are added.  The submit ABI gains a flags
argument, and the pointers are fixed at 64-bit.  Shaders are now fixed at
the start of their BOs.

r600: Fix build after 984f3069370cd4a347cb38269d430b428385affd

Same as for the CLAMP macro, undef it before including a header file that
tries to make fields with that name.

st/nine: Mark end of non-void function unreachable

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Eric Anholt <eric@anholt.net>

gallium: include util/macros.h

The most common macros are defined there, no use to duplicate these
Clean up the already redefinded macros

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Eric Anholt <eric@anholt.net>